x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.h

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 81d045eded8447c85b7b2acd3f760fd79346ea54..709d5192b023336c9f021fb76d717936b68580f2 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -1,5 +1,5 @@
 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.

-   Copyright (C) 2012-2018 Free Software Foundation, Inc.
+   Copyright (C) 2012-2020 Free Software Foundation, Inc.

    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.


@@ -70,6 +70,7 @@ enum aarch64_field_kind
   FLD_imm6_2,
   FLD_imm4,
   FLD_imm4_2,
   FLD_imm6_2,
   FLD_imm4,
   FLD_imm4_2,

+  FLD_imm4_3,

   FLD_imm5,
   FLD_imm7,
   FLD_imm8,
   FLD_imm5,
   FLD_imm7,
   FLD_imm8,


@@ -120,6 +121,9 @@ enum aarch64_field_kind
   FLD_SVE_Zt,
   FLD_SVE_i1,
   FLD_SVE_i3h,
   FLD_SVE_Zt,
   FLD_SVE_i1,
   FLD_SVE_i3h,

+  FLD_SVE_i3l,
+  FLD_SVE_i3h2,
+  FLD_SVE_i2h,

   FLD_SVE_imm3,
   FLD_SVE_imm4,
   FLD_SVE_imm5,
   FLD_SVE_imm3,
   FLD_SVE_imm4,
   FLD_SVE_imm5,


@@ -135,7 +139,10 @@ enum aarch64_field_kind
   FLD_SVE_prfop,
   FLD_SVE_rot1,
   FLD_SVE_rot2,
   FLD_SVE_prfop,
   FLD_SVE_rot1,
   FLD_SVE_rot2,

+  FLD_SVE_rot3,

   FLD_SVE_sz,
   FLD_SVE_sz,

+  FLD_SVE_size,
+  FLD_SVE_sz2,

   FLD_SVE_tsz,
   FLD_SVE_tszh,
   FLD_SVE_tszl_8,
   FLD_SVE_tsz,
   FLD_SVE_tszh,
   FLD_SVE_tszl_8,


@@ -145,7 +152,8 @@ enum aarch64_field_kind
   FLD_rotate1,
   FLD_rotate2,
   FLD_rotate3,
   FLD_rotate1,
   FLD_rotate2,
   FLD_rotate3,

-  FLD_SM3_imm2
+  FLD_SM3_imm2,
+  FLD_sz

 };
 
 /* Field description.  */
 };
 
 /* Field description.  */


@@ -183,6 +191,10 @@ typedef struct aarch64_operand aarch64_operand;
 
 extern const aarch64_operand aarch64_operands[];
 
 
 extern const aarch64_operand aarch64_operands[];
 

+enum err_type
+verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
+                   bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
+

 /* Operand flags.  */
 
 #define OPD_F_HAS_INSERTER     0x00000001
 /* Operand flags.  */
 
 #define OPD_F_HAS_INSERTER     0x00000001


@@ -195,6 +207,38 @@ extern const aarch64_operand aarch64_operands[];
 #define OPD_F_OD_MASK          0x000000e0      /* Operand-dependent data.  */
 #define OPD_F_OD_LSB           5
 #define OPD_F_NO_ZR            0x00000100      /* ZR index not allowed.  */
 #define OPD_F_OD_MASK          0x000000e0      /* Operand-dependent data.  */
 #define OPD_F_OD_LSB           5
 #define OPD_F_NO_ZR            0x00000100      /* ZR index not allowed.  */

+#define OPD_F_SHIFT_BY_4       0x00000200      /* Need to left shift the field
+                                                  value by 4 to get the value
+                                                  of an immediate operand.  */
+
+
+/* Register flags.  */
+
+#undef F_DEPRECATED
+#define F_DEPRECATED   (1 << 0)  /* Deprecated system register.  */
+
+#undef F_ARCHEXT
+#define F_ARCHEXT      (1 << 1)  /* Architecture dependent system register.  */
+
+#undef F_HASXT
+#define F_HASXT                (1 << 2)  /* System instruction register <Xt>
+                                    operand.  */
+
+#undef F_REG_READ
+#define F_REG_READ     (1 << 3)  /* Register can only be used to read values
+                                    out of.  */
+
+#undef F_REG_WRITE
+#define F_REG_WRITE    (1 << 4)  /* Register can only be written to but not
+                                    read from.  */
+
+/* HINT operand flags.  */
+#define HINT_OPD_F_NOPRINT     (1 << 0)  /* Should not be printed.  */
+
+/* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
+#define HINT_ENCODE(flag, val) ((flag << 8) | val)
+#define HINT_FLAG(val) (val >> 8)
+#define HINT_VAL(val) (val & 0xff)

 
 static inline bfd_boolean
 operand_has_inserter (const aarch64_operand *operand)
 
 static inline bfd_boolean
 operand_has_inserter (const aarch64_operand *operand)


@@ -220,6 +264,12 @@ operand_need_shift_by_two (const aarch64_operand *operand)
   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 }
 
   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 }
 

+static inline bfd_boolean
+operand_need_shift_by_four (const aarch64_operand *operand)
+{
+  return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
+}
+

 static inline bfd_boolean
 operand_maybe_stack_pointer (const aarch64_operand *operand)
 {
 static inline bfd_boolean
 operand_maybe_stack_pointer (const aarch64_operand *operand)
 {


@@ -435,7 +485,7 @@ enum aarch64_modifier_kind
 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 
 
 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 
 

-bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
+bfd_boolean aarch64_wide_constant_p (uint64_t, int, unsigned int *);

 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 int aarch64_shrink_expanded_imm8 (uint64_t);
 
 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 int aarch64_shrink_expanded_imm8 (uint64_t);