Prevent address violation when attempting to disassemble a corrupt score binary.

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.h

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 087376e09c054f5f50ec003bab476cebf5d64b3f..9f73ebac4ab4fddcd0622090ad8d26f312009f0a 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -1,5 +1,5 @@
 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.

-   Copyright (C) 2012-2016 Free Software Foundation, Inc.
+   Copyright (C) 2012-2017 Free Software Foundation, Inc.

    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.


@@ -80,6 +80,7 @@ enum aarch64_field_kind
   FLD_immr,
   FLD_immb,
   FLD_immh,
   FLD_immr,
   FLD_immb,
   FLD_immh,

+  FLD_S_imm10,

   FLD_N,
   FLD_index,
   FLD_index2,
   FLD_N,
   FLD_index,
   FLD_index2,


@@ -91,6 +92,9 @@ enum aarch64_field_kind
   FLD_b5,
   FLD_b40,
   FLD_scale,
   FLD_b5,
   FLD_b40,
   FLD_scale,

+  FLD_SVE_M_4,
+  FLD_SVE_M_14,
+  FLD_SVE_M_16,

   FLD_SVE_N,
   FLD_SVE_Pd,
   FLD_SVE_Pg3,
   FLD_SVE_N,
   FLD_SVE_Pd,
   FLD_SVE_Pg3,


@@ -100,6 +104,11 @@ enum aarch64_field_kind
   FLD_SVE_Pm,
   FLD_SVE_Pn,
   FLD_SVE_Pt,
   FLD_SVE_Pm,
   FLD_SVE_Pn,
   FLD_SVE_Pt,

+  FLD_SVE_Rm,
+  FLD_SVE_Rn,
+  FLD_SVE_Vd,
+  FLD_SVE_Vm,
+  FLD_SVE_Vn,

   FLD_SVE_Za_5,
   FLD_SVE_Za_16,
   FLD_SVE_Zd,
   FLD_SVE_Za_5,
   FLD_SVE_Za_16,
   FLD_SVE_Zd,


@@ -107,6 +116,8 @@ enum aarch64_field_kind
   FLD_SVE_Zm_16,
   FLD_SVE_Zn,
   FLD_SVE_Zt,
   FLD_SVE_Zm_16,
   FLD_SVE_Zn,
   FLD_SVE_Zt,

+  FLD_SVE_i1,
+  FLD_SVE_i3h,

   FLD_SVE_imm3,
   FLD_SVE_imm4,
   FLD_SVE_imm5,
   FLD_SVE_imm3,
   FLD_SVE_imm4,
   FLD_SVE_imm5,


@@ -120,9 +131,18 @@ enum aarch64_field_kind
   FLD_SVE_msz,
   FLD_SVE_pattern,
   FLD_SVE_prfop,
   FLD_SVE_msz,
   FLD_SVE_pattern,
   FLD_SVE_prfop,

+  FLD_SVE_rot1,
+  FLD_SVE_rot2,
+  FLD_SVE_sz,
+  FLD_SVE_tsz,

   FLD_SVE_tszh,
   FLD_SVE_tszh,

+  FLD_SVE_tszl_8,
+  FLD_SVE_tszl_19,

   FLD_SVE_xs_14,
   FLD_SVE_xs_22,
   FLD_SVE_xs_14,
   FLD_SVE_xs_22,

+  FLD_rotate1,
+  FLD_rotate2,
+  FLD_rotate3,

 };
 
 /* Field description.  */
 };
 
 /* Field description.  */


@@ -169,9 +189,9 @@ extern const aarch64_operand aarch64_operands[];
                                                   value by 2 to get the value
                                                   of an immediate operand.  */
 #define OPD_F_MAYBE_SP         0x00000010      /* May potentially be SP.  */
                                                   value by 2 to get the value
                                                   of an immediate operand.  */
 #define OPD_F_MAYBE_SP         0x00000010      /* May potentially be SP.  */

-#define OPD_F_OD_MASK          0x00000060      /* Operand-dependent data.  */
+#define OPD_F_OD_MASK          0x000000e0      /* Operand-dependent data.  */

 #define OPD_F_OD_LSB           5
 #define OPD_F_OD_LSB           5

-#define OPD_F_NO_ZR            0x00000080      /* ZR index not allowed.  */
+#define OPD_F_NO_ZR            0x00000100      /* ZR index not allowed.  */

 
 static inline bfd_boolean
 operand_has_inserter (const aarch64_operand *operand)
 
 static inline bfd_boolean
 operand_has_inserter (const aarch64_operand *operand)


@@ -210,6 +230,14 @@ get_operand_specific_data (const aarch64_operand *operand)
   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 }
 
   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 }
 

+/* Return the width of field number N of operand *OPERAND.  */
+static inline unsigned
+get_operand_field_width (const aarch64_operand *operand, unsigned n)
+{
+  assert (operand->fields[n] != FLD_NIL);
+  return fields[operand->fields[n]].width;
+}
+

 /* Return the total width of the operand *OPERAND.  */
 static inline unsigned
 get_operand_fields_width (const aarch64_operand *operand)
 /* Return the total width of the operand *OPERAND.  */
 static inline unsigned
 get_operand_fields_width (const aarch64_operand *operand)


@@ -320,6 +348,9 @@ extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 {
   return extract_field_2 (&fields[kind], code, mask);
 }
 {
   return extract_field_2 (&fields[kind], code, mask);
 }

+
+extern aarch64_insn
+extract_fields (aarch64_insn code, aarch64_insn mask, ...);

 \f
 /* Inline functions selecting operand to do the encoding/decoding for a
    certain instruction bit-field.  */
 \f
 /* Inline functions selecting operand to do the encoding/decoding for a
    certain instruction bit-field.  */