-/* Local insertion and extraction functions */
-
-static unsigned insert_rba PARAMS((unsigned, int, const char **));
-static unsigned insert_rca PARAMS((unsigned, int, const char **));
-static unsigned insert_za PARAMS((unsigned, int, const char **));
-static unsigned insert_zb PARAMS((unsigned, int, const char **));
-static unsigned insert_zc PARAMS((unsigned, int, const char **));
-static unsigned insert_bdisp PARAMS((unsigned, int, const char **));
-static unsigned insert_jhint PARAMS((unsigned, int, const char **));
-static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **));
-
-static int extract_rba PARAMS((unsigned, int *));
-static int extract_rca PARAMS((unsigned, int *));
-static int extract_za PARAMS((unsigned, int *));
-static int extract_zb PARAMS((unsigned, int *));
-static int extract_zc PARAMS((unsigned, int *));
-static int extract_bdisp PARAMS((unsigned, int *));
-static int extract_jhint PARAMS((unsigned, int *));
-static int extract_ev6hwjhint PARAMS((unsigned, int *));
-
-\f
-/* The operands table */
-
-const struct alpha_operand alpha_operands[] =
-{
- /* The fields are bits, shift, insert, extract, flags */
- /* The zero index is used to indicate end-of-list */
-#define UNUSED 0
- { 0, 0, 0, 0, 0 },
-
- /* The plain integer register fields */
-#define RA (UNUSED + 1)
- { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
-#define RB (RA + 1)
- { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
-#define RC (RB + 1)
- { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
-
- /* The plain fp register fields */
-#define FA (RC + 1)
- { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
-#define FB (FA + 1)
- { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
-#define FC (FB + 1)
- { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
-
- /* The integer registers when they are ZERO */
-#define ZA (FC + 1)
- { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
-#define ZB (ZA + 1)
- { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
-#define ZC (ZB + 1)
- { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
-
- /* The RB field when it needs parentheses */
-#define PRB (ZC + 1)
- { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
-
- /* The RB field when it needs parentheses _and_ a preceding comma */
-#define CPRB (PRB + 1)
- { 5, 16, 0,
- AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
-
- /* The RB field when it must be the same as the RA field */
-#define RBA (CPRB + 1)
- { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
-
- /* The RC field when it must be the same as the RB field */
-#define RCA (RBA + 1)
- { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
-
- /* The RC field when it can *default* to RA */
-#define DRC1 (RCA + 1)
- { 5, 0, 0,
- AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
-
- /* The RC field when it can *default* to RB */
-#define DRC2 (DRC1 + 1)
- { 5, 0, 0,
- AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
-
- /* The FC field when it can *default* to RA */
-#define DFC1 (DRC2 + 1)
- { 5, 0, 0,
- AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
-
- /* The FC field when it can *default* to RB */
-#define DFC2 (DFC1 + 1)
- { 5, 0, 0,
- AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
-
- /* The unsigned 8-bit literal of Operate format insns */
-#define LIT (DFC2 + 1)
- { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
-
- /* The signed 16-bit displacement of Memory format insns. From here
- we can't tell what relocation should be used, so don't use a default. */
-#define MDISP (LIT + 1)
- { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
-
- /* The signed "23-bit" aligned displacement of Branch format insns */
-#define BDISP (MDISP + 1)
- { 21, 0, BFD_RELOC_23_PCREL_S2,
- AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
-
- /* The 26-bit PALcode function */
-#define PALFN (BDISP + 1)
- { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
-
- /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
-#define JMPHINT (PALFN + 1)
- { 14, 0, BFD_RELOC_ALPHA_HINT,
- AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
- insert_jhint, extract_jhint },
-
- /* The optional hint to RET/JSR_COROUTINE */
-#define RETHINT (JMPHINT + 1)
- { 14, 0, -RETHINT,
- AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
-
- /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
-#define EV4HWDISP (RETHINT + 1)
-#define EV6HWDISP (EV4HWDISP)
- { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
-
- /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
-#define EV4HWINDEX (EV4HWDISP + 1)
- { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
-
- /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
- that occur in DEC PALcode. */
-#define EV4EXTHWINDEX (EV4HWINDEX + 1)
- { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
-
- /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
-#define EV5HWDISP (EV4EXTHWINDEX + 1)
- { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
-
- /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
-#define EV5HWINDEX (EV5HWDISP + 1)
- { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
-
- /* The 16-bit combined index/scoreboard mask for the ev6
- hw_m[ft]pr (pal19/pal1d) insns */
-#define EV6HWINDEX (EV5HWINDEX + 1)
- { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
-
- /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
-#define EV6HWJMPHINT (EV6HWINDEX+ 1)
- { 8, 0, -EV6HWJMPHINT,
- AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
- insert_ev6hwjhint, extract_ev6hwjhint }
-};
-
-const int alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
-