+
+void
+disassemble_init_for_target (struct disassemble_info * info)
+{
+ if (info == NULL)
+ return;
+
+ switch (info->arch)
+ {
+#ifdef ARCH_aarch64
+ case bfd_arch_aarch64:
+ info->symbol_is_valid = aarch64_symbol_is_valid;
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
+#ifdef ARCH_arm
+ case bfd_arch_arm:
+ info->symbol_is_valid = arm_symbol_is_valid;
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
+#ifdef ARCH_csky
+ case bfd_arch_csky:
+ info->symbol_is_valid = csky_symbol_is_valid;
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
+
+#ifdef ARCH_ia64
+ case bfd_arch_ia64:
+ info->skip_zeroes = 16;
+ break;
+#endif
+#ifdef ARCH_tic4x
+ case bfd_arch_tic4x:
+ info->skip_zeroes = 32;
+ break;
+#endif
+#ifdef ARCH_mep
+ case bfd_arch_mep:
+ info->skip_zeroes = 256;
+ info->skip_zeroes_at_end = 0;
+ break;
+#endif
+#ifdef ARCH_metag
+ case bfd_arch_metag:
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
+#ifdef ARCH_m32c
+ case bfd_arch_m32c:
+ /* This processor in fact is little endian. The value set here
+ reflects the way opcodes are written in the cgen description. */
+ info->endian = BFD_ENDIAN_BIG;
+ if (! info->insn_sets)
+ {
+ info->insn_sets = cgen_bitset_create (ISA_MAX);
+ if (info->mach == bfd_mach_m16c)
+ cgen_bitset_set (info->insn_sets, ISA_M16C);
+ else
+ cgen_bitset_set (info->insn_sets, ISA_M32C);
+ }
+ break;
+#endif
+#ifdef ARCH_pru
+ case bfd_arch_pru:
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
+#ifdef ARCH_powerpc
+ case bfd_arch_powerpc:
+#endif
+#ifdef ARCH_rs6000
+ case bfd_arch_rs6000:
+#endif
+#if defined (ARCH_powerpc) || defined (ARCH_rs6000)
+ disassemble_init_powerpc (info);
+ break;
+#endif
+#ifdef ARCH_riscv
+ case bfd_arch_riscv:
+ info->symbol_is_valid = riscv_symbol_is_valid;
+ break;
+#endif
+#ifdef ARCH_wasm32
+ case bfd_arch_wasm32:
+ disassemble_init_wasm32 (info);
+ break;
+#endif
+#ifdef ARCH_s390
+ case bfd_arch_s390:
+ disassemble_init_s390 (info);
+ break;
+#endif
+#ifdef ARCH_nds32
+ case bfd_arch_nds32:
+ disassemble_init_nds32 (info);
+ break;
+ #endif
+ default:
+ break;
+ }
+}
+
+/* Remove whitespace and consecutive commas from OPTIONS. */
+
+char *
+remove_whitespace_and_extra_commas (char *options)
+{
+ char *str;
+ size_t i, len;
+
+ if (options == NULL)
+ return NULL;
+
+ /* Strip off all trailing whitespace and commas. */
+ for (len = strlen (options); len > 0; len--)
+ {
+ if (!ISSPACE (options[len - 1]) && options[len - 1] != ',')
+ break;
+ options[len - 1] = '\0';
+ }
+
+ /* Convert all remaining whitespace to commas. */
+ for (i = 0; options[i] != '\0'; i++)
+ if (ISSPACE (options[i]))
+ options[i] = ',';
+
+ /* Remove consecutive commas. */
+ for (str = options; *str != '\0'; str++)
+ if (*str == ',' && (*(str + 1) == ',' || str == options))
+ {
+ char *next = str + 1;
+ while (*next == ',')
+ next++;
+ len = strlen (next);
+ if (str != options)
+ str++;
+ memmove (str, next, len);
+ next[len - (size_t)(next - str)] = '\0';
+ }
+ return (strlen (options) != 0) ? options : NULL;
+}
+
+/* Like STRCMP, but treat ',' the same as '\0' so that we match
+ strings like "foobar" against "foobar,xxyyzz,...". */
+
+int
+disassembler_options_cmp (const char *s1, const char *s2)
+{
+ unsigned char c1, c2;
+
+ do
+ {
+ c1 = (unsigned char) *s1++;
+ if (c1 == ',')
+ c1 = '\0';
+ c2 = (unsigned char) *s2++;
+ if (c2 == ',')
+ c2 = '\0';
+ if (c1 == '\0')
+ return c1 - c2;
+ }
+ while (c1 == c2);
+
+ return c1 - c2;
+}