+
+void
+disassemble_init_for_target (struct disassemble_info * info)
+{
+ if (info == NULL)
+ return;
+
+ switch (info->arch)
+ {
+#ifdef ARCH_aarch64
+ case bfd_arch_aarch64:
+ info->symbol_is_valid = aarch64_symbol_is_valid;
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
+#ifdef ARCH_arm
+ case bfd_arch_arm:
+ info->symbol_is_valid = arm_symbol_is_valid;
+ info->disassembler_needs_relocs = TRUE;
+ break;
+#endif
+#ifdef ARCH_ia64
+ case bfd_arch_ia64:
+ info->skip_zeroes = 16;
+ break;
+#endif
+#ifdef ARCH_tic4x
+ case bfd_arch_tic4x:
+ info->skip_zeroes = 32;
+ break;
+#endif
+#ifdef ARCH_mep
+ case bfd_arch_mep:
+ info->skip_zeroes = 256;
+ info->skip_zeroes_at_end = 0;
+ break;
+#endif
+#ifdef ARCH_m32c
+ case bfd_arch_m32c:
+ /* This processor in fact is little endian. The value set here
+ reflects the way opcodes are written in the cgen description. */
+ info->endian = BFD_ENDIAN_BIG;
+ if (! info->insn_sets)
+ {
+ info->insn_sets = cgen_bitset_create (ISA_MAX);
+ if (info->mach == bfd_mach_m16c)
+ cgen_bitset_set (info->insn_sets, ISA_M16C);
+ else
+ cgen_bitset_set (info->insn_sets, ISA_M32C);
+ }
+ break;
+#endif
+#ifdef ARCH_powerpc
+ case bfd_arch_powerpc:
+#endif
+#ifdef ARCH_rs6000
+ case bfd_arch_rs6000:
+#endif
+#if defined (ARCH_powerpc) || defined (ARCH_rs6000)
+ disassemble_init_powerpc (info);
+ break;
+#endif
+ default:
+ break;
+ }
+}