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Prevent address violation problem when disassembling corrupt aarch64 binary.
[deliverable/binutils-gdb.git]
/
opcodes
/
fr30-ibld.c
diff --git
a/opcodes/fr30-ibld.c
b/opcodes/fr30-ibld.c
index 0607331fece3ba555fc093838020e9f1d621b097..b6f1fa16ff44d029f762889771dee17d211ad70e 100644
(file)
--- a/
opcodes/fr30-ibld.c
+++ b/
opcodes/fr30-ibld.c
@@
-3,8
+3,7
@@
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
- 2008, 2010 Free Software Foundation, Inc.
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
This file is part of libopcodes.
This file is part of libopcodes.
@@
-33,6
+32,7
@@
#include "symcat.h"
#include "fr30-desc.h"
#include "fr30-opc.h"
#include "symcat.h"
#include "fr30-desc.h"
#include "fr30-opc.h"
+#include "cgen/basic-modes.h"
#include "opintl.h"
#include "safe-ctype.h"
#include "opintl.h"
#include "safe-ctype.h"
@@
-137,7
+137,7
@@
insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
if (length == 0)
return NULL;
- if (word_length >
32
)
+ if (word_length >
8 * sizeof (CGEN_INSN_INT)
)
abort ();
/* For architectures with insns smaller than the base-insn-bitsize,
abort ();
/* For architectures with insns smaller than the base-insn-bitsize,
@@
-154,7
+154,7
@@
insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
-
+
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@@
-192,7
+192,7
@@
insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
-
+
if (value < minval || value > maxval)
{
sprintf
if (value < minval || value > maxval)
{
sprintf
@@
-207,12
+207,19
@@
insert_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
{
#if CGEN_INT_INSN_P
{
- int shift;
+ int shift
_within_word, shift_to_word, shift
;
+ /* How to shift the value to BIT0 of the word. */
+ shift_to_word = total_length - (word_offset + word_length);
+
+ /* How to shift the value to the field within the word. */
if (CGEN_INSN_LSB0_P)
if (CGEN_INSN_LSB0_P)
- shift
= (word_offset + start + 1)
- length;
+ shift
_within_word = start + 1
- length;
else
else
- shift = total_length - (word_offset + start + length);
+ shift_within_word = word_length - start - length;
+
+ /* The total SHIFT, then mask in the value. */
+ shift = shift_to_word + shift_within_word;
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
}
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
}
@@
-441,7
+448,7
@@
extract_normal (CGEN_CPU_DESC cd,
return 1;
}
return 1;
}
- if (word_length >
32
)
+ if (word_length >
8 * sizeof (CGEN_INSN_INT)
)
abort ();
/* For architectures with insns smaller than the insn-base-bitsize,
abort ();
/* For architectures with insns smaller than the insn-base-bitsize,
@@
-468,7
+475,7
@@
extract_normal (CGEN_CPU_DESC cd,
{
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
{
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
- if (word_length >
32
)
+ if (word_length >
8 * sizeof (CGEN_INSN_INT)
)
abort ();
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
abort ();
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
@@
-604,7
+611,7
@@
fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
case FR30_OPERAND_DIR10 :
{
long value = fields->f_dir10;
case FR30_OPERAND_DIR10 :
{
long value = fields->f_dir10;
- value = ((
unsigned int
) (value) >> (2));
+ value = ((
USI
) (value) >> (2));
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
}
break;
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
}
break;
@@
-614,14
+621,14
@@
fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
case FR30_OPERAND_DIR9 :
{
long value = fields->f_dir9;
case FR30_OPERAND_DIR9 :
{
long value = fields->f_dir9;
- value = ((
unsigned int
) (value) >> (1));
+ value = ((
USI
) (value) >> (1));
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_DISP10 :
{
long value = fields->f_disp10;
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_DISP10 :
{
long value = fields->f_disp10;
- value = ((
int
) (value) >> (2));
+ value = ((
SI
) (value) >> (2));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
}
break;
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
}
break;
@@
-631,14
+638,14
@@
fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
case FR30_OPERAND_DISP9 :
{
long value = fields->f_disp9;
case FR30_OPERAND_DISP9 :
{
long value = fields->f_disp9;
- value = ((
int
) (value) >> (1));
+ value = ((
SI
) (value) >> (1));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_I20 :
{
{
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 4, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_I20 :
{
{
- FLD (f_i20_4) = ((
unsigned int
) (FLD (f_i20)) >> (16));
+ FLD (f_i20_4) = ((
UINT
) (FLD (f_i20)) >> (16));
FLD (f_i20_16) = ((FLD (f_i20)) & (65535));
}
errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer);
FLD (f_i20_16) = ((FLD (f_i20)) & (65535));
}
errmsg = insert_normal (cd, fields->f_i20_4, 0, 0, 8, 4, 16, total_length, buffer);
@@
-658,14
+665,14
@@
fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
case FR30_OPERAND_LABEL12 :
{
long value = fields->f_rel12;
case FR30_OPERAND_LABEL12 :
{
long value = fields->f_rel12;
- value = ((
int
) (((value) - (((pc) + (2))))) >> (1));
+ value = ((
SI
) (((value) - (((pc) + (2))))) >> (1));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer);
}
break;
case FR30_OPERAND_LABEL9 :
{
long value = fields->f_rel9;
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer);
}
break;
case FR30_OPERAND_LABEL9 :
{
long value = fields->f_rel9;
- value = ((
int
) (((value) - (((pc) + (2))))) >> (1));
+ value = ((
SI
) (((value) - (((pc) + (2))))) >> (1));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer);
}
break;
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer);
}
break;
@@
-693,14
+700,14
@@
fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
case FR30_OPERAND_S10 :
{
long value = fields->f_s10;
case FR30_OPERAND_S10 :
{
long value = fields->f_s10;
- value = ((
int
) (value) >> (2));
+ value = ((
SI
) (value) >> (2));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_U10 :
{
long value = fields->f_u10;
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_U10 :
{
long value = fields->f_u10;
- value = ((
unsigned int
) (value) >> (2));
+ value = ((
USI
) (value) >> (2));
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
}
break;
errmsg = insert_normal (cd, value, 0, 0, 8, 8, 16, total_length, buffer);
}
break;
@@
-716,7
+723,7
@@
fr30_cgen_insert_operand (CGEN_CPU_DESC cd,
case FR30_OPERAND_UDISP6 :
{
long value = fields->f_udisp6;
case FR30_OPERAND_UDISP6 :
{
long value = fields->f_udisp6;
- value = ((
unsigned int
) (value) >> (2));
+ value = ((
USI
) (value) >> (2));
errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
}
break;
errmsg = insert_normal (cd, value, 0, 0, 8, 4, 16, total_length, buffer);
}
break;
@@
-874,7
+881,7
@@
fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
{
long value;
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
{
long value;
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 16, total_length, pc, & value);
- value = ((value) | (
((-1) << (4))
));
+ value = ((value) | (
-16
));
fields->f_m4 = value;
}
break;
fields->f_m4 = value;
}
break;
@@
-936,12
+943,12
@@
fr30_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
return length;
}
-cgen_insert_fn * const fr30_cgen_insert_handlers[] =
+cgen_insert_fn * const fr30_cgen_insert_handlers[] =
{
insert_insn_normal,
};
{
insert_insn_normal,
};
-cgen_extract_fn * const fr30_cgen_extract_handlers[] =
+cgen_extract_fn * const fr30_cgen_extract_handlers[] =
{
extract_insn_normal,
};
{
extract_insn_normal,
};
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