-static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int asm_hash_insn PARAMS ((const char *));
-static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
-
-/* Look up instruction INSN_VALUE and extract its fields.
- INSN, if non-null, is the insn table entry.
- Otherwise INSN_VALUE is examined to compute it.
- LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
- 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
- If INSN != NULL, LENGTH must be valid.
- ALIAS_P is non-zero if alias insns are to be included in the search.
-
- The result is a pointer to the insn table entry, or NULL if the instruction
- wasn't recognized. */
-
-const CGEN_INSN *
-fr30_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
- CGEN_OPCODE_DESC od;
- const CGEN_INSN *insn;
- CGEN_INSN_BYTES insn_value;
- int length;
- CGEN_FIELDS *fields;
- int alias_p;
-{
- unsigned char buf[CGEN_MAX_INSN_SIZE];
- unsigned char *bufp;
- CGEN_INSN_INT base_insn;
-#if CGEN_INT_INSN_P
- CGEN_EXTRACT_INFO *info = NULL;
-#else
- CGEN_EXTRACT_INFO ex_info;
- CGEN_EXTRACT_INFO *info = &ex_info;
-#endif
-
-#if CGEN_INT_INSN_P
- cgen_put_insn_value (od, buf, length, insn_value);
- bufp = buf;
- base_insn = insn_value; /*???*/
-#else
- ex_info.dis_info = NULL;
- ex_info.insn_bytes = insn_value;
- ex_info.valid = -1;
- base_insn = cgen_get_insn_value (od, buf, length);
- bufp = insn_value;
-#endif
-
- if (!insn)
- {
- const CGEN_INSN_LIST *insn_list;
-
- /* The instructions are stored in hash lists.
- Pick the first one and keep trying until we find the right one. */
-
- insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
- while (insn_list != NULL)
- {
- insn = insn_list->insn;
-
- if (alias_p
- || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
- {
- /* Basic bit mask must be correct. */
- /* ??? May wish to allow target to defer this check until the
- extract handler. */
- if ((base_insn & CGEN_INSN_BASE_MASK (insn))
- == CGEN_INSN_BASE_VALUE (insn))
- {
- /* ??? 0 is passed for `pc' */
- int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
- base_insn, fields,
- (bfd_vma) 0);
- if (elength > 0)
- {
- /* sanity check */
- if (length != 0 && length != elength)
- abort ();
- return insn;
- }
- }
- }
-
- insn_list = CGEN_DIS_NEXT_INSN (insn_list);
- }
- }
- else
- {
- /* Sanity check: can't pass an alias insn if ! alias_p. */
- if (! alias_p
- && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
- abort ();
- /* Sanity check: length must be correct. */
- if (length != CGEN_INSN_BITSIZE (insn))
- abort ();
-
- /* ??? 0 is passed for `pc' */
- length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
- (bfd_vma) 0);
- /* Sanity check: must succeed.
- Could relax this later if it ever proves useful. */
- if (length == 0)
- abort ();
- return insn;
- }
-
- return NULL;
-}
-
-/* Fill in the operand instances used by INSN whose operands are FIELDS.
- INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
- in. */
-
-void
-fr30_cgen_get_insn_operands (od, insn, fields, indices)
- CGEN_OPCODE_DESC od;
- const CGEN_INSN * insn;
- const CGEN_FIELDS * fields;
- int *indices;
-{
- const CGEN_OPERAND_INSTANCE *opinst;
- int i;
-
- for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
- opinst != NULL
- && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
- ++i, ++opinst)
- {
- const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
- if (op == NULL)
- indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
- else
- indices[i] = fr30_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
- fields);
- }
-}
-
-/* Cover function to fr30_cgen_get_insn_operands when either INSN or FIELDS
- isn't known.
- The INSN, INSN_VALUE, and LENGTH arguments are passed to
- fr30_cgen_lookup_insn unchanged.
-
- The result is the insn table entry or NULL if the instruction wasn't
- recognized. */
-
-const CGEN_INSN *
-fr30_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
- CGEN_OPCODE_DESC od;
- const CGEN_INSN *insn;
- CGEN_INSN_BYTES insn_value;
- int length;
- int *indices;
-{
- CGEN_FIELDS fields;
-
- /* Pass non-zero for ALIAS_P only if INSN != NULL.
- If INSN == NULL, we want a real insn. */
- insn = fr30_cgen_lookup_insn (od, insn, insn_value, length, &fields,
- insn != NULL);
- if (! insn)
- return NULL;
-
- fr30_cgen_get_insn_operands (od, insn, &fields, indices);
- return insn;
-}
-/* Attributes. */
-
-static const CGEN_ATTR_ENTRY bool_attr[] =
-{
- { "#f", 0 },
- { "#t", 1 },
- { 0, 0 }
-};
-
-static const CGEN_ATTR_ENTRY MACH_attr[] =
-{
- { "base", MACH_BASE },
- { "fr30", MACH_FR30 },
- { "max", MACH_MAX },
- { 0, 0 }
-};
-
-const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
-{
- { "MACH", & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
- { "RESERVED", &bool_attr[0], &bool_attr[0] },
- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
-{
- { "MACH", & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
- { "SIGNED", &bool_attr[0], &bool_attr[0] },
- { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
- { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
- { "PC", &bool_attr[0], &bool_attr[0] },
- { "PROFILE", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
-{
- { "MACH", & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
- { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
- { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
- { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
- { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
- { "RELAX", &bool_attr[0], &bool_attr[0] },
- { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
- { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
-{
- { "MACH", & MACH_attr[0] },
- { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
- { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
- { "COND-CTI", &bool_attr[0], &bool_attr[0] },
- { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
- { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
- { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
- { "RELAX", &bool_attr[0], &bool_attr[0] },
- { "ALIAS", &bool_attr[0], &bool_attr[0] },
- { "NO-DIS", &bool_attr[0], &bool_attr[0] },
- { "PBB", &bool_attr[0], &bool_attr[0] },
- { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
- { 0, 0, 0 }
-};
-
-CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
-{
- { "r0", 0 },
- { "r1", 1 },
- { "r2", 2 },
- { "r3", 3 },
- { "r4", 4 },
- { "r5", 5 },
- { "r6", 6 },
- { "r7", 7 },
- { "r8", 8 },
- { "r9", 9 },
- { "r10", 10 },
- { "r11", 11 },
- { "r12", 12 },
- { "r13", 13 },
- { "r14", 14 },
- { "r15", 15 },
- { "ac", 13 },
- { "fp", 14 },
- { "sp", 15 }
-};
-
-CGEN_KEYWORD fr30_cgen_opval_h_gr =
-{
- & fr30_cgen_opval_h_gr_entries[0],
- 19
-};
-
-CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_cr_entries[] =
-{
- { "cr0", 0 },
- { "cr1", 1 },
- { "cr2", 2 },
- { "cr3", 3 },
- { "cr4", 4 },
- { "cr5", 5 },
- { "cr6", 6 },
- { "cr7", 7 },
- { "cr8", 8 },
- { "cr9", 9 },
- { "cr10", 10 },
- { "cr11", 11 },
- { "cr12", 12 },
- { "cr13", 13 },
- { "cr14", 14 },
- { "cr15", 15 }
-};
-
-CGEN_KEYWORD fr30_cgen_opval_h_cr =
-{
- & fr30_cgen_opval_h_cr_entries[0],
- 16
-};
-
-CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_dr_entries[] =
-{
- { "tbr", 0 },
- { "rp", 1 },
- { "ssp", 2 },
- { "usp", 3 },
- { "mdh", 4 },
- { "mdl", 5 }
-};
-
-CGEN_KEYWORD fr30_cgen_opval_h_dr =
-{
- & fr30_cgen_opval_h_dr_entries[0],
- 6
-};
-
-CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
-{
- { "ps", 0 }
-};
-
-CGEN_KEYWORD fr30_cgen_opval_h_ps =
-{
- & fr30_cgen_opval_h_ps_entries[0],
- 1
-};
-
-CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
-{
- { "r13", 0 }
-};
-
-CGEN_KEYWORD fr30_cgen_opval_h_r13 =
-{
- & fr30_cgen_opval_h_r13_entries[0],
- 1
-};
-
-CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
-{
- { "r14", 0 }
-};
-
-CGEN_KEYWORD fr30_cgen_opval_h_r14 =
-{
- & fr30_cgen_opval_h_r14_entries[0],
- 1
-};
-
-CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
-{
- { "r15", 0 }
-};
-
-CGEN_KEYWORD fr30_cgen_opval_h_r15 =
-{
- & fr30_cgen_opval_h_r15_entries[0],
- 1
-};
-
-
-/* The hardware table. */
-
-#define HW_ENT(n) fr30_cgen_hw_entries[n]
-static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
-{
- { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
- { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
- { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
- { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
- { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
- { HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
- { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
- { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
- { 0 }
-};
-
-/* The instruction field table. */
-
-static const CGEN_IFLD fr30_cgen_ifld_table[] =
-{
- { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_CC, "f-cc", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_U4, "f-u4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_I4, "f-i4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { FR30_F_M4, "f-m4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_U8, "f-u8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_I8, "f-i8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_I32, "f-i32", 16, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { FR30_F_S10, "f-s10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { FR30_F_U10, "f-u10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
- { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
- { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
- { 0 }
-};
-
-/* The operand table. */
-
-#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
-#define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
-
-const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
-{
-/* pc: program counter */
- { "pc", & HW_ENT (HW_H_PC), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* Ri: destination register */
- { "Ri", & HW_ENT (HW_H_GR), 12, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* Rj: source register */
- { "Rj", & HW_ENT (HW_H_GR), 8, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* Ric: target register coproc insn */
- { "Ric", & HW_ENT (HW_H_GR), 12, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* Rjc: source register coproc insn */
- { "Rjc", & HW_ENT (HW_H_GR), 8, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* CRi: coprocessor register */
- { "CRi", & HW_ENT (HW_H_CR), 12, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* CRj: coprocessor register */
- { "CRj", & HW_ENT (HW_H_CR), 8, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* Rs1: dedicated register */
- { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* Rs2: dedicated register */
- { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* R13: General Register 13 */
- { "R13", & HW_ENT (HW_H_R13), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
-/* R14: General Register 14 */
- { "R14", & HW_ENT (HW_H_R14), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
-/* R15: General Register 15 */
- { "R15", & HW_ENT (HW_H_R15), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
-/* ps: Program Status register */
- { "ps", & HW_ENT (HW_H_PS), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
-/* u4: 4 bit unsigned immediate */
- { "u4", & HW_ENT (HW_H_UINT), 8, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* u4c: 4 bit unsigned immediate */
- { "u4c", & HW_ENT (HW_H_UINT), 12, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* u8: 8 bit unsigned immediate */
- { "u8", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* i8: 8 bit unsigned immediate */
- { "i8", & HW_ENT (HW_H_UINT), 4, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* udisp6: 6 bit unsigned immediate */
- { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* disp8: 8 bit signed immediate */
- { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
-/* disp9: 9 bit signed immediate */
- { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
-/* disp10: 10 bit signed immediate */
- { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
-/* s10: 10 bit signed immediate */
- { "s10", & HW_ENT (HW_H_SINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
-/* u10: 10 bit unsigned immediate */
- { "u10", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* i32: 32 bit immediate */
- { "i32", & HW_ENT (HW_H_UINT), 0, 32,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* m4: 4 bit negative immediate */
- { "m4", & HW_ENT (HW_H_SINT), 8, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* i20: 20 bit immediate */
- { "i20", & HW_ENT (HW_H_UINT), 0, 20,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { (1<<MACH_BASE) } } },
-/* dir8: 8 bit direct address */
- { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* dir9: 9 bit direct address */
- { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* dir10: 10 bit direct address */
- { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* label9: 9 bit pc relative address */
- { "label9", & HW_ENT (HW_H_IADDR), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
-/* label12: 12 bit pc relative address */
- { "label12", & HW_ENT (HW_H_IADDR), 5, 11,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
-/* reglist_low_ld: 8 bit register mask for ldm */
- { "reglist_low_ld", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* reglist_hi_ld: 8 bit register mask for ldm */
- { "reglist_hi_ld", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* reglist_low_st: 8 bit register mask for ldm */
- { "reglist_low_st", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* reglist_hi_st: 8 bit register mask for ldm */
- { "reglist_hi_st", & HW_ENT (HW_H_UINT), 8, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* cc: condition codes */
- { "cc", & HW_ENT (HW_H_UINT), 4, 4,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* ccc: coprocessor calc */
- { "ccc", & HW_ENT (HW_H_UINT), 0, 8,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
-/* nbit: negative bit */
- { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* vbit: overflow bit */
- { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* zbit: zero bit */
- { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* cbit: carry bit */
- { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* ibit: interrupt bit */
- { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* sbit: stack bit */
- { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* tbit: trace trap bit */
- { "tbit", & HW_ENT (HW_H_TBIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* d0bit: division 0 bit */
- { "d0bit", & HW_ENT (HW_H_D0BIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* d1bit: division 1 bit */
- { "d1bit", & HW_ENT (HW_H_D1BIT), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* ccr: condition code bits */
- { "ccr", & HW_ENT (HW_H_CCR), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* scr: system condition bits */
- { "scr", & HW_ENT (HW_H_SCR), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-/* ilm: interrupt level mask */
- { "ilm", & HW_ENT (HW_H_ILM), 0, 0,
- { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
-};