-
-/* The hardware table. */
-
-#define HW_ENT(n) fr30_cgen_hw_entries[n]
-static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
-{
- { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
- { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
- { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0, { 0 } } },
- { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
- { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
- { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
- { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { 0 }
-};
-
-/* The operand table. */
-
-#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
-#define OP_ENT(op) fr30_cgen_operand_table[OPERAND (op)]
-
-const CGEN_OPERAND fr30_cgen_operand_table[MAX_OPERANDS] =
-{
-/* pc: program counter */
- { "pc", & HW_ENT (HW_H_PC), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-/* Ri: destination register */
- { "Ri", & HW_ENT (HW_H_GR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* Rj: source register */
- { "Rj", & HW_ENT (HW_H_GR), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* Rs1: dedicated register */
- { "Rs1", & HW_ENT (HW_H_DR), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* Rs2: dedicated register */
- { "Rs2", & HW_ENT (HW_H_DR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* R13: General Register 13 */
- { "R13", & HW_ENT (HW_H_R13), 0, 0,
- { 0, 0, { 0 } } },
-/* R14: General Register 14 */
- { "R14", & HW_ENT (HW_H_R14), 0, 0,
- { 0, 0, { 0 } } },
-/* R15: General Register 15 */
- { "R15", & HW_ENT (HW_H_R15), 0, 0,
- { 0, 0, { 0 } } },
-/* ps: Program Status register */
- { "ps", & HW_ENT (HW_H_PS), 0, 0,
- { 0, 0, { 0 } } },
-/* u4: 4 bit unsigned immediate */
- { "u4", & HW_ENT (HW_H_UINT), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* m4: 4 bit negative immediate */
- { "m4", & HW_ENT (HW_H_UINT), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* u8: 8 bit unsigned immediate */
- { "u8", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* i8: 8 bit unsigned immediate */
- { "i8", & HW_ENT (HW_H_UINT), 4, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* udisp6: 6 bit unsigned immediate */
- { "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* disp8: 8 bit signed immediate */
- { "disp8", & HW_ENT (HW_H_SINT), 4, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
-/* disp9: 9 bit signed immediate */
- { "disp9", & HW_ENT (HW_H_SINT), 4, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
-/* disp10: 10 bit signed immediate */
- { "disp10", & HW_ENT (HW_H_SINT), 4, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
-/* s10: 10 bit signed immediate */
- { "s10", & HW_ENT (HW_H_SINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
-/* u10: 10 bit unsigned immediate */
- { "u10", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* i32: 32 bit immediate */
- { "i32", & HW_ENT (HW_H_UINT), 16, 32,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* dir8: 8 bit direct address */
- { "dir8", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* dir9: 9 bit direct address */
- { "dir9", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* dir10: 10 bit direct address */
- { "dir10", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* label9: 9 bit pc relative address */
- { "label9", & HW_ENT (HW_H_SINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
-/* label12: 12 bit pc relative address */
- { "label12", & HW_ENT (HW_H_SINT), 5, 11,
- { 0, 0|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
-/* cc: condition codes */
- { "cc", & HW_ENT (HW_H_UINT), 4, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* nbit: negative bit */
- { "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-/* vbit: overflow bit */
- { "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-/* zbit: zero bit */
- { "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-/* cbit: carry bit */
- { "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-/* ibit: interrupt bit */
- { "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-/* sbit: stack bit */
- { "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-};
-
-/* Operand references. */
-
-#define INPUT CGEN_OPERAND_INSTANCE_INPUT
-#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
-#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
-
-static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "u4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (U4), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_add2_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "m4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (M4), 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addc_ops[] = {
- { INPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { INPUT, "Rj", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RJ), 0, 0 },
- { INPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "vbit", & HW_ENT (HW_H_VBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "cbit", & HW_ENT (HW_H_CBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "Ri", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (RI), 0, 0 },
- { OUTPUT, "zbit", & HW_ENT (HW_H_ZBIT), CGEN_MODE_BI, 0, 0, 0 },
- { OUTPUT, "nbit", & HW_ENT (HW_H_NBIT), CGEN_MODE_BI, 0, 0, 0 },
- { 0 }