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x86: correct abort check
[deliverable/binutils-gdb.git]
/
opcodes
/
frv-ibld.c
diff --git
a/opcodes/frv-ibld.c
b/opcodes/frv-ibld.c
index 7b7efab4b49184791067895e494f2bb5fe61953c..98f2f3459b8f969af9ef77372d39a6502186ddc2 100644
(file)
--- a/
opcodes/frv-ibld.c
+++ b/
opcodes/frv-ibld.c
@@
-1,10
+1,10
@@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Instruction building/extraction support for frv. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
/* Instruction building/extraction support for frv. -*- C -*-
THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
- the resultant file is machine generated, cgen-ibld.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007
- Free Software Foundation, Inc.
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
This file is part of libopcodes.
This file is part of libopcodes.
@@
-33,6
+33,7
@@
#include "symcat.h"
#include "frv-desc.h"
#include "frv-opc.h"
#include "symcat.h"
#include "frv-desc.h"
#include "frv-opc.h"
+#include "cgen/basic-modes.h"
#include "opintl.h"
#include "safe-ctype.h"
#include "opintl.h"
#include "safe-ctype.h"
@@
-137,7
+138,7
@@
insert_normal (CGEN_CPU_DESC cd,
if (length == 0)
return NULL;
if (length == 0)
return NULL;
- if (word_length >
32
)
+ if (word_length >
8 * sizeof (CGEN_INSN_INT)
)
abort ();
/* For architectures with insns smaller than the base-insn-bitsize,
abort ();
/* For architectures with insns smaller than the base-insn-bitsize,
@@
-154,7
+155,7
@@
insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
{
long minval = - (1L << (length - 1));
unsigned long maxval = mask;
-
+
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
if ((value > 0 && (unsigned long) value > maxval)
|| value < minval)
{
@@
-192,7
+193,7
@@
insert_normal (CGEN_CPU_DESC cd,
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
{
long minval = - (1L << (length - 1));
long maxval = (1L << (length - 1)) - 1;
-
+
if (value < minval || value > maxval)
{
sprintf
if (value < minval || value > maxval)
{
sprintf
@@
-207,12
+208,19
@@
insert_normal (CGEN_CPU_DESC cd,
#if CGEN_INT_INSN_P
{
#if CGEN_INT_INSN_P
{
- int shift;
+ int shift
_within_word, shift_to_word, shift
;
+ /* How to shift the value to BIT0 of the word. */
+ shift_to_word = total_length - (word_offset + word_length);
+
+ /* How to shift the value to the field within the word. */
if (CGEN_INSN_LSB0_P)
if (CGEN_INSN_LSB0_P)
- shift
= (word_offset + start + 1)
- length;
+ shift
_within_word = start + 1
- length;
else
else
- shift = total_length - (word_offset + start + length);
+ shift_within_word = word_length - start - length;
+
+ /* The total SHIFT, then mask in the value. */
+ shift = shift_to_word + shift_within_word;
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
}
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
}
@@
-441,7
+449,7
@@
extract_normal (CGEN_CPU_DESC cd,
return 1;
}
return 1;
}
- if (word_length >
32
)
+ if (word_length >
8 * sizeof (CGEN_INSN_INT)
)
abort ();
/* For architectures with insns smaller than the insn-base-bitsize,
abort ();
/* For architectures with insns smaller than the insn-base-bitsize,
@@
-468,7
+476,7
@@
extract_normal (CGEN_CPU_DESC cd,
{
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
{
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
- if (word_length >
32
)
+ if (word_length >
8 * sizeof (CGEN_INSN_INT)
)
abort ();
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
abort ();
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
@@
-755,15
+763,15
@@
frv_cgen_insert_operand (CGEN_CPU_DESC cd,
case FRV_OPERAND_LABEL16 :
{
long value = fields->f_label16;
case FRV_OPERAND_LABEL16 :
{
long value = fields->f_label16;
- value = ((
int
) (((value) - (pc))) >> (2));
+ value = ((
SI
) (((value) - (pc))) >> (2));
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, buffer);
}
break;
case FRV_OPERAND_LABEL24 :
{
{
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, buffer);
}
break;
case FRV_OPERAND_LABEL24 :
{
{
- FLD (f_labelH6) = ((
int
) (((FLD (f_label24)) - (pc))) >> (20));
- FLD (f_labelL18) = ((((
unsigned int
) (((FLD (f_label24)) - (pc))) >> (2))) & (262143));
+ FLD (f_labelH6) = ((
SI
) (((FLD (f_label24)) - (pc))) >> (20));
+ FLD (f_labelL18) = ((((
UINT
) (((FLD (f_label24)) - (pc))) >> (2))) & (262143));
}
errmsg = insert_normal (cd, fields->f_labelH6, 0|(1<<CGEN_IFLD_SIGNED), 0, 30, 6, 32, total_length, buffer);
if (errmsg)
}
errmsg = insert_normal (cd, fields->f_labelH6, 0|(1<<CGEN_IFLD_SIGNED), 0, 30, 6, 32, total_length, buffer);
if (errmsg)
@@
-809,7
+817,7
@@
frv_cgen_insert_operand (CGEN_CPU_DESC cd,
case FRV_OPERAND_SPR :
{
{
case FRV_OPERAND_SPR :
{
{
- FLD (f_spr_h) = ((
unsigned int
) (FLD (f_spr)) >> (6));
+ FLD (f_spr_h) = ((
UINT
) (FLD (f_spr)) >> (6));
FLD (f_spr_l) = ((FLD (f_spr)) & (63));
}
errmsg = insert_normal (cd, fields->f_spr_h, 0, 0, 30, 6, 32, total_length, buffer);
FLD (f_spr_l) = ((FLD (f_spr)) & (63));
}
errmsg = insert_normal (cd, fields->f_spr_h, 0, 0, 30, 6, 32, total_length, buffer);
@@
-823,7
+831,7
@@
frv_cgen_insert_operand (CGEN_CPU_DESC cd,
case FRV_OPERAND_U12 :
{
{
case FRV_OPERAND_U12 :
{
{
- FLD (f_u12_h) = ((
int
) (FLD (f_u12)) >> (6));
+ FLD (f_u12_h) = ((
SI
) (FLD (f_u12)) >> (6));
FLD (f_u12_l) = ((FLD (f_u12)) & (63));
}
errmsg = insert_normal (cd, fields->f_u12_h, 0|(1<<CGEN_IFLD_SIGNED), 0, 17, 6, 32, total_length, buffer);
FLD (f_u12_l) = ((FLD (f_u12)) & (63));
}
errmsg = insert_normal (cd, fields->f_u12_h, 0|(1<<CGEN_IFLD_SIGNED), 0, 17, 6, 32, total_length, buffer);
@@
-1174,12
+1182,12
@@
frv_cgen_extract_operand (CGEN_CPU_DESC cd,
return length;
}
return length;
}
-cgen_insert_fn * const frv_cgen_insert_handlers[] =
+cgen_insert_fn * const frv_cgen_insert_handlers[] =
{
insert_insn_normal,
};
{
insert_insn_normal,
};
-cgen_extract_fn * const frv_cgen_extract_handlers[] =
+cgen_extract_fn * const frv_cgen_extract_handlers[] =
{
extract_insn_normal,
};
{
extract_insn_normal,
};
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