+ if (!((thisnib & 0x4) == 0))
+ goto fail;
+
+ looking_for = (op_type) ((int) looking_for & ~(int) B20);
+ }
+ if ((int) looking_for & (int) B11)
+ {
+ if (!((thisnib & 0x2) != 0))
+ goto fail;
+
+ looking_for = (op_type) ((int) looking_for & ~(int) B11);
+ thisnib &= 0xd;
+ }
+ else if ((int) looking_for & (int) B10)
+ {
+ if (!((thisnib & 0x2) == 0))
+ goto fail;
+
+ looking_for = (op_type) ((int) looking_for & ~(int) B10);
+ }
+
+ if ((int) looking_for & (int) B01)
+ {
+ if (!((thisnib & 0x1) != 0))
+ goto fail;
+
+ looking_for = (op_type) ((int) looking_for & ~(int) B01);
+ thisnib &= 0xe;
+ }
+ else if ((int) looking_for & (int) B00)
+ {
+ if (!((thisnib & 0x1) == 0))
+ goto fail;
+
+ looking_for = (op_type) ((int) looking_for & ~(int) B00);
+ }
+
+ if (looking_for & IGNORE)
+ {
+ /* Hitachi has declared that IGNORE must be zero. */
+ if (thisnib != 0)
+ goto fail;
+ }
+ else if ((looking_for & MODE) == DATA)
+ {
+ ; /* Skip embedded data. */
+ }
+ else if ((looking_for & MODE) == DBIT)
+ {
+ /* Exclude adds/subs by looking at bit 0 and 2, and
+ make sure the operand size, either w or l,
+ matches by looking at bit 1. */
+ if ((looking_for & 7) != (thisnib & 7))
+ goto fail;
+
+ cst[opnr] = (thisnib & 0x8) ? 2 : 1;
+ }
+ else if ((looking_for & MODE) == DISP
+ || (looking_for & MODE) == ABS
+ || (looking_for & MODE) == PCREL
+ || (looking_for & MODE) == INDEXB
+ || (looking_for & MODE) == INDEXW
+ || (looking_for & MODE) == INDEXL)
+ {
+ extract_immediate (stream, looking_for, thisnib,
+ data + len / 2, cst + opnr,
+ cstlen + opnr, q);
+ /* Even address == bra, odd == bra/s. */
+ if (q->how == O (O_BRAS, SB))
+ cst[opnr] -= 1;
+ }
+ else if ((looking_for & MODE) == REG
+ || (looking_for & MODE) == LOWREG
+ || (looking_for & MODE) == IND
+ || (looking_for & MODE) == PREINC
+ || (looking_for & MODE) == POSTINC
+ || (looking_for & MODE) == PREDEC
+ || (looking_for & MODE) == POSTDEC)
+ {
+ regno[opnr] = thisnib;
+ }
+ else if (looking_for & CTRL) /* Control Register. */
+ {
+ thisnib &= 7;
+ if (((looking_for & MODE) == CCR && (thisnib != C_CCR))
+ || ((looking_for & MODE) == EXR && (thisnib != C_EXR))
+ || ((looking_for & MODE) == MACH && (thisnib != C_MACH))
+ || ((looking_for & MODE) == MACL && (thisnib != C_MACL))
+ || ((looking_for & MODE) == VBR && (thisnib != C_VBR))
+ || ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
+ goto fail;
+ if (((looking_for & MODE) == CCR_EXR
+ && (thisnib != C_CCR && thisnib != C_EXR))
+ || ((looking_for & MODE) == VBR_SBR
+ && (thisnib != C_VBR && thisnib != C_SBR))
+ || ((looking_for & MODE) == MACREG
+ && (thisnib != C_MACH && thisnib != C_MACL)))
+ goto fail;
+ if (((looking_for & MODE) == CC_EX_VB_SB
+ && (thisnib != C_CCR && thisnib != C_EXR
+ && thisnib != C_VBR && thisnib != C_SBR)))
+ goto fail;
+
+ regno[opnr] = thisnib;
+ }
+ else if ((looking_for & SIZE) == L_5)
+ {
+ cst[opnr] = data[len / 2] & 31;
+ cstlen[opnr] = 5;
+ }
+ else if ((looking_for & SIZE) == L_4)
+ {
+ cst[opnr] = thisnib;
+ cstlen[opnr] = 4;