- "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7",
- "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"
- }
- ;
-
- int rs = 0;
- int rd = 0;
- int rdisp = 0;
- int abs = 0;
- int bit = 0;
- int plen = 0;
- static boolean init = 0;
- struct h8_opcode *q = h8_opcodes;
- char CONST **pregnames = mode != 0 ? lregnames : wregnames;
+ if ((x & SIZE) == L_16 ||
+ (x & SIZE) == L_16U)
+ {
+ outfn (stream, ".%s%d (0x%lx)",
+ (short) cst > 0 ? "+" : "",
+ (short) cst,
+ (long)(addr + (short) cst + len));
+ }
+ else
+ {
+ outfn (stream, ".%s%d (0x%lx)",
+ (char) cst > 0 ? "+" : "",
+ (char) cst,
+ (long)(addr + (char) cst + len));
+ }
+ }
+ else if ((x & MODE) == DISP)
+ outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, pregnames[rdisp_n]);
+
+ else if ((x & MODE) == INDEXB)
+ /* Always take low half of reg. */
+ outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
+ regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
+
+ else if ((x & MODE) == INDEXW)
+ /* Always take low half of reg. */
+ outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
+ wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
+
+ else if ((x & MODE) == INDEXL)
+ outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]);
+
+ else if (x & CTRL)
+ outfn (stream, "%s", cregnames[rn]);
+
+ else if ((x & MODE) == CCR)
+ outfn (stream, "ccr");
+
+ else if ((x & MODE) == EXR)
+ outfn (stream, "exr");
+
+ else if ((x & MODE) == MACREG)
+ outfn (stream, "mac%c", cst ? 'l' : 'h');
+
+ else
+ /* xgettext:c-format */
+ outfn (stream, _("Hmmmm 0x%x"), x);
+}
+
+static unsigned int
+bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
+{
+ /* Find the first entry in the table for this opcode. */
+ int regno[3] = { 0, 0, 0 };
+ int dispregno[3] = { 0, 0, 0 };
+ int cst[3] = { 0, 0, 0 };
+ int cstlen[3] = { 0, 0, 0 };
+ static bfd_boolean init = 0;
+ const struct h8_instruction *qi;
+ char const **pregnames = mach != 0 ? lregnames : wregnames;