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Remove the remaining SSE5 support
[deliverable/binutils-gdb.git]
/
opcodes
/
i386-dis.c
diff --git
a/opcodes/i386-dis.c
b/opcodes/i386-dis.c
index de0534c24e7dea107281d61e4eea4007181a44a7..cd1321f40050bf635b7dd4e77608622cabacc4d9 100644
(file)
--- a/
opcodes/i386-dis.c
+++ b/
opcodes/i386-dis.c
@@
-258,7
+258,7
@@
fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define Edw { OP_E, dw_mode }
#define Edqd { OP_E, dqd_mode }
#define Eq { OP_E, q_mode }
#define Edw { OP_E, dw_mode }
#define Edqd { OP_E, dqd_mode }
#define Eq { OP_E, q_mode }
-#define indirEv { OP_indirE,
stack
_v_mode }
+#define indirEv { OP_indirE,
indir
_v_mode }
#define indirEp { OP_indirE, f_mode }
#define stackEv { OP_E, stack_v_mode }
#define Em { OP_E, m_mode }
#define indirEp { OP_indirE, f_mode }
#define stackEv { OP_E, stack_v_mode }
#define Em { OP_E, m_mode }
@@
-561,6
+561,8
@@
enum
/* 4- or 6-byte pointer operand */
f_mode,
const_1_mode,
/* 4- or 6-byte pointer operand */
f_mode,
const_1_mode,
+ /* v_mode for indirect branch opcodes. */
+ indir_v_mode,
/* v_mode for stack-related opcodes. */
stack_v_mode,
/* non-quad operand size depends on prefixes */
/* v_mode for stack-related opcodes. */
stack_v_mode,
/* non-quad operand size depends on prefixes */
@@
-982,6
+984,8
@@
enum
PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2,
PREFIX_0FAE_REG_3,
PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2,
PREFIX_0FAE_REG_3,
+ PREFIX_MOD_0_0FAE_REG_4,
+ PREFIX_MOD_3_0FAE_REG_4,
PREFIX_0FAE_REG_6,
PREFIX_0FAE_REG_7,
PREFIX_RM_0_0FAE_REG_7,
PREFIX_0FAE_REG_6,
PREFIX_0FAE_REG_7,
PREFIX_RM_0_0FAE_REG_7,
@@
-2483,6
+2487,9
@@
struct dis386 {
suffix_always is true (lcall/ljmp).
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
suffix_always is true (lcall/ljmp).
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
+ '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
+ has no operand size prefix for AMD64 ISA, behave as 'P'
+ otherwise
2 upper case letter macros:
"XY" => print 'x' or 'y' if suffix_always is true or no register
2 upper case letter macros:
"XY" => print 'x' or 'y' if suffix_always is true or no register
@@
-3531,9
+3538,9
@@
static const struct dis386 reg_table[][8] = {
{
{ "incQ", { Evh1 }, 0 },
{ "decQ", { Evh1 }, 0 },
{
{ "incQ", { Evh1 }, 0 },
{ "decQ", { Evh1 }, 0 },
- { "call{
T
|}", { indirEv, BND }, 0 },
+ { "call{
&
|}", { indirEv, BND }, 0 },
{ MOD_TABLE (MOD_FF_REG_3) },
{ MOD_TABLE (MOD_FF_REG_3) },
- { "jmp{
T
|}", { indirEv, BND }, 0 },
+ { "jmp{
&
|}", { indirEv, BND }, 0 },
{ MOD_TABLE (MOD_FF_REG_5) },
{ "pushU", { stackEv }, 0 },
{ Bad_Opcode },
{ MOD_TABLE (MOD_FF_REG_5) },
{ "pushU", { stackEv }, 0 },
{ Bad_Opcode },
@@
-4061,6
+4068,18
@@
static const struct dis386 prefix_table[][4] = {
{ "wrgsbase", { Ev }, 0 },
},
{ "wrgsbase", { Ev }, 0 },
},
+ /* PREFIX_MOD_0_0FAE_REG_4 */
+ {
+ { "xsave", { FXSAVE }, 0 },
+ { "ptwrite%LQ", { Edq }, 0 },
+ },
+
+ /* PREFIX_MOD_3_0FAE_REG_4 */
+ {
+ { Bad_Opcode },
+ { "ptwrite%LQ", { Edq }, 0 },
+ },
+
/* PREFIX_0FAE_REG_6 */
{
{ "xsaveopt", { FXSAVE }, 0 },
/* PREFIX_0FAE_REG_6 */
{
{ "xsaveopt", { FXSAVE }, 0 },
@@
-4132,7
+4151,7
@@
static const struct dis386 prefix_table[][4] = {
/* PREFIX_MOD_3_0FC7_REG_7 */
{
{ "rdseed", { Ev }, 0 },
/* PREFIX_MOD_3_0FC7_REG_7 */
{
{ "rdseed", { Ev }, 0 },
- {
Bad_Opcode
},
+ {
"rdpid", { Em }, 0
},
{ "rdseed", { Ev }, 0 },
},
{ "rdseed", { Ev }, 0 },
},
@@
-7572,7
+7591,7
@@
static const struct dis386 three_byte_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
- {
"ptest", { XX }, PREFIX_OPCODE
},
+ {
Bad_Opcode
},
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
@@
-11864,7
+11883,8
@@
static const struct dis386 mod_table[][2] = {
},
{
/* MOD_0FAE_REG_4 */
},
{
/* MOD_0FAE_REG_4 */
- { "xsave", { FXSAVE }, 0 },
+ { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
},
{
/* MOD_0FAE_REG_5 */
},
{
/* MOD_0FAE_REG_5 */
@@
-13327,6
+13347,13
@@
print_insn (bfd_vma pc, disassemble_info *info)
p++;
}
p++;
}
+ if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
+ {
+ (*info->fprintf_func) (info->stream,
+ _("64-bit address is disabled"));
+ return -1;
+ }
+
if (intel_syntax)
{
names64 = intel_names64;
if (intel_syntax)
{
names64 = intel_names64;
@@
-14068,7
+14095,6
@@
putop (const char *in_template, int sizeflag)
cond = 0;
break;
case '{':
cond = 0;
break;
case '{':
- alt = 0;
if (intel_syntax)
{
while (*++p != '|')
if (intel_syntax)
{
while (*++p != '|')
@@
-14289,6
+14315,15
@@
case_L:
if (!(rex & REX_W))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
if (!(rex & REX_W))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
+ case '&':
+ if (!intel_syntax
+ && address_mode == mode_64bit
+ && isa64 == intel64)
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
case 'T':
if (!intel_syntax
&& address_mode == mode_64bit
case 'T':
if (!intel_syntax
&& address_mode == mode_64bit
@@
-14809,13
+14844,20
@@
intel_operand_size (int bytemode, int sizeflag)
case dqw_swap_mode:
oappend ("WORD PTR ");
break;
case dqw_swap_mode:
oappend ("WORD PTR ");
break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ oappend ("QWORD PTR ");
+ break;
+ }
+ /* Fall through. */
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
oappend ("QWORD PTR ");
break;
}
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
oappend ("QWORD PTR ");
break;
}
- /* F
ALLTHRU
*/
+ /* F
all through.
*/
case v_mode:
case v_swap_mode:
case dq_mode:
case v_mode:
case v_swap_mode:
case dq_mode:
@@
-15186,6
+15228,13
@@
OP_E_register (int bytemode, int sizeflag)
case bnd_mode:
names = names_bnd;
break;
case bnd_mode:
names = names_bnd;
break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ names = names64;
+ break;
+ }
+ /* Fall through. */
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
@@
-15193,7
+15242,7
@@
OP_E_register (int bytemode, int sizeflag)
break;
}
bytemode = v_mode;
break;
}
bytemode = v_mode;
- /* F
ALLTHRU
*/
+ /* F
all through.
*/
case v_mode:
case v_swap_mode:
case dq_mode:
case v_mode:
case v_swap_mode:
case dq_mode:
@@
-15274,7
+15323,7
@@
OP_E_memory (int bytemode, int sizeflag)
shift = vex.w ? 3 : 2;
break;
}
shift = vex.w ? 3 : 2;
break;
}
- /* Fall through
if vex.b == 0
. */
+ /* Fall through. */
case xmmqd_mode:
case xmmdw_mode:
case ymmq_mode:
case xmmqd_mode:
case xmmdw_mode:
case ymmq_mode:
@@
-17254,6
+17303,7
@@
get_vex_imm8 (int sizeflag, int opnum)
if (base != 5)
/* No displacement. */
break;
if (base != 5)
/* No displacement. */
break;
+ /* Fall through. */
case 2:
/* 4 byte displacement. */
bytes_before_imm += 4;
case 2:
/* 4 byte displacement. */
bytes_before_imm += 4;
@@
-17280,6
+17330,7
@@
get_vex_imm8 (int sizeflag, int opnum)
if (modrm.rm != 6)
/* No displacement. */
break;
if (modrm.rm != 6)
/* No displacement. */
break;
+ /* Fall through. */
case 2:
/* 2 byte displacement. */
bytes_before_imm += 2;
case 2:
/* 2 byte displacement. */
bytes_before_imm += 2;
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