+ /* PREFIX_VEX_0F92 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
+ },
+
+ /* PREFIX_VEX_0F93 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
+ },
+
+ /* PREFIX_VEX_0F98 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
+ },
+
+ /* PREFIX_VEX_0F99 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
+ },
+
+ /* PREFIX_VEX_0FC2 */
+ {
+ { VEX_W_TABLE (VEX_W_0FC2_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
+ { VEX_W_TABLE (VEX_W_0FC2_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
+ },
+
+ /* PREFIX_VEX_0FC4 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
+ },
+
+ /* PREFIX_VEX_0FC5 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
+ },
+
+ /* PREFIX_VEX_0FD0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD0_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD0_P_3) },
+ },
+
+ /* PREFIX_VEX_0FD1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD1_P_2) },
+ },
+
+ /* PREFIX_VEX_0FD2 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD2_P_2) },
+ },
+
+ /* PREFIX_VEX_0FD3 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD3_P_2) },
+ },
+
+ /* PREFIX_VEX_0FD4 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD4_P_2) },
+ },
+
+ /* PREFIX_VEX_0FD5 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD5_P_2) },
+ },
+
+ /* PREFIX_VEX_0FD6 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
+ },
+
+ /* PREFIX_VEX_0FD7 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0FD8 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD8_P_2) },
+ },
+
+ /* PREFIX_VEX_0FD9 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD9_P_2) },
+ },
+
+ /* PREFIX_VEX_0FDA */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FDA_P_2) },
+ },
+
+ /* PREFIX_VEX_0FDB */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FDB_P_2) },
+ },
+
+ /* PREFIX_VEX_0FDC */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FDC_P_2) },
+ },
+
+ /* PREFIX_VEX_0FDD */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FDD_P_2) },
+ },
+
+ /* PREFIX_VEX_0FDE */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FDE_P_2) },
+ },
+
+ /* PREFIX_VEX_0FDF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FDF_P_2) },
+ },
+
+ /* PREFIX_VEX_0FE0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE0_P_2) },
+ },
+
+ /* PREFIX_VEX_0FE1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE1_P_2) },
+ },
+
+ /* PREFIX_VEX_0FE2 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE2_P_2) },
+ },
+
+ /* PREFIX_VEX_0FE3 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE3_P_2) },
+ },
+
+ /* PREFIX_VEX_0FE4 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE4_P_2) },
+ },
+
+ /* PREFIX_VEX_0FE5 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE5_P_2) },
+ },
+
+ /* PREFIX_VEX_0FE6 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE6_P_1) },
+ { VEX_W_TABLE (VEX_W_0FE6_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE6_P_3) },
+ },
+
+ /* PREFIX_VEX_0FE7 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0FE8 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE8_P_2) },
+ },
+
+ /* PREFIX_VEX_0FE9 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FE9_P_2) },
+ },
+
+ /* PREFIX_VEX_0FEA */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FEA_P_2) },
+ },
+
+ /* PREFIX_VEX_0FEB */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FEB_P_2) },
+ },
+
+ /* PREFIX_VEX_0FEC */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FEC_P_2) },
+ },
+
+ /* PREFIX_VEX_0FED */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FED_P_2) },
+ },
+
+ /* PREFIX_VEX_0FEE */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FEE_P_2) },
+ },
+
+ /* PREFIX_VEX_0FEF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FEF_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
+ },
+
+ /* PREFIX_VEX_0FF1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FF1_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF2 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FF2_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF3 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FF3_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF4 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FF4_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF5 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FF5_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF6 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FF6_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF7 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF8 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FF8_P_2) },
+ },
+
+ /* PREFIX_VEX_0FF9 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FF9_P_2) },
+ },
+
+ /* PREFIX_VEX_0FFA */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FFA_P_2) },
+ },
+
+ /* PREFIX_VEX_0FFB */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FFB_P_2) },
+ },
+
+ /* PREFIX_VEX_0FFC */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FFC_P_2) },
+ },
+
+ /* PREFIX_VEX_0FFD */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FFD_P_2) },
+ },
+
+ /* PREFIX_VEX_0FFE */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FFE_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3800 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3800_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3801 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3801_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3802 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3802_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3803 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3803_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3804 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3804_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3805 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3805_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3806 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3806_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3807 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3807_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3808 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3808_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3809 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3809_P_2) },
+ },
+
+ /* PREFIX_VEX_0F380A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F380A_P_2) },
+ },
+
+ /* PREFIX_VEX_0F380B */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F380B_P_2) },
+ },
+
+ /* PREFIX_VEX_0F380C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F380C_P_2) },
+ },
+
+ /* PREFIX_VEX_0F380D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F380D_P_2) },
+ },
+
+ /* PREFIX_VEX_0F380E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F380E_P_2) },
+ },
+
+ /* PREFIX_VEX_0F380F */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F380F_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3813 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vcvtph2ps", { XM, EXxmmq }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3816 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3817 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3817_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3818 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3818_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3819 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
+ },
+
+ /* PREFIX_VEX_0F381A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F381C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F381C_P_2) },
+ },
+
+ /* PREFIX_VEX_0F381D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F381D_P_2) },
+ },
+
+ /* PREFIX_VEX_0F381E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F381E_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3820 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3820_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3821 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3821_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3822 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3822_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3823 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3823_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3824 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3824_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3825 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3825_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3828 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3828_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3829 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3829_P_2) },
+ },
+
+ /* PREFIX_VEX_0F382A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F382B */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F382B_P_2) },
+ },
+
+ /* PREFIX_VEX_0F382C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F382D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F382E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F382F */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F3830 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3830_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3831 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3831_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3832 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3832_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3833 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3833_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3834 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3834_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3835 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3835_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3836 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3837 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3837_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3838 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3838_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3839 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3839_P_2) },
+ },
+
+ /* PREFIX_VEX_0F383A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F383A_P_2) },
+ },
+
+ /* PREFIX_VEX_0F383B */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F383B_P_2) },
+ },
+
+ /* PREFIX_VEX_0F383C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F383C_P_2) },
+ },
+
+ /* PREFIX_VEX_0F383D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F383D_P_2) },
+ },
+
+ /* PREFIX_VEX_0F383E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F383E_P_2) },
+ },
+
+ /* PREFIX_VEX_0F383F */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F383F_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3840 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3840_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3841 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3845 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3846 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3846_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3847 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpsllv%LW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3858 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3858_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3859 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3859_P_2) },
+ },
+
+ /* PREFIX_VEX_0F385A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F3878 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3878_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3879 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3879_P_2) },
+ },
+
+ /* PREFIX_VEX_0F388C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F388E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F3890 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3891 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3892 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3893 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3896 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3897 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3898 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3899 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F389A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F389B */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F389C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F389D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F389E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F389F */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38A6 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
+ { Bad_Opcode },
+ },
+
+ /* PREFIX_VEX_0F38A7 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38A8 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38A9 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38AA */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38AB */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38AC */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38AD */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38AE */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38AF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38B6 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38B7 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38B8 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38B9 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38BA */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38BB */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38BC */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38BD */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38BE */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38BF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ },
+
+ /* PREFIX_VEX_0F38DB */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
+ },
+
+ /* PREFIX_VEX_0F38DC */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
+ },
+
+ /* PREFIX_VEX_0F38DD */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
+ },
+
+ /* PREFIX_VEX_0F38DE */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
+ },
+
+ /* PREFIX_VEX_0F38DF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
+ },
+
+ /* PREFIX_VEX_0F38F2 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_1 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_2 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_3 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F5 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
+ },
+
+ /* PREFIX_VEX_0F38F6 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
+ },
+
+ /* PREFIX_VEX_0F38F7 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
+ },
+
+ /* PREFIX_VEX_0F3A00 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A01 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A02 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A04 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A05 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A06 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A08 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A09 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A0A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A0B */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A0C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A0D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A0E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A0F */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A14 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A15 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A16 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A17 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A18 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A19 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A1D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A20 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A21 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A22 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A30 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A31 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A32 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A33 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A38 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A39 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A40 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A41 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A42 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A44 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A46 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A48 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A49 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A4A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A4B */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A4C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A5C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A5D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A5E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A5F */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A60 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
+ { Bad_Opcode },
+ },
+
+ /* PREFIX_VEX_0F3A61 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A62 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A63 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A68 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A69 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A6A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A6B */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A6C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A6D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A6E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A6F */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A78 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A79 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A7A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A7B */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A7C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { Bad_Opcode },
+ },
+
+ /* PREFIX_VEX_0F3A7D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3A7E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A7F */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3ADF */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3AF0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
+ },
+
+#define NEED_PREFIX_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_PREFIX_TABLE
+};
+
+static const struct dis386 x86_64_table[][2] = {
+ /* X86_64_06 */
+ {
+ { "pushP", { es }, 0 },
+ },
+
+ /* X86_64_07 */
+ {
+ { "popP", { es }, 0 },
+ },
+
+ /* X86_64_0D */
+ {
+ { "pushP", { cs }, 0 },
+ },
+
+ /* X86_64_16 */
+ {
+ { "pushP", { ss }, 0 },
+ },
+
+ /* X86_64_17 */
+ {
+ { "popP", { ss }, 0 },
+ },
+
+ /* X86_64_1E */
+ {
+ { "pushP", { ds }, 0 },
+ },
+
+ /* X86_64_1F */
+ {
+ { "popP", { ds }, 0 },
+ },
+
+ /* X86_64_27 */
+ {
+ { "daa", { XX }, 0 },
+ },
+
+ /* X86_64_2F */
+ {
+ { "das", { XX }, 0 },
+ },
+
+ /* X86_64_37 */
+ {
+ { "aaa", { XX }, 0 },
+ },
+
+ /* X86_64_3F */
+ {
+ { "aas", { XX }, 0 },
+ },
+
+ /* X86_64_60 */
+ {
+ { "pushaP", { XX }, 0 },
+ },
+
+ /* X86_64_61 */
+ {
+ { "popaP", { XX }, 0 },
+ },
+
+ /* X86_64_62 */
+ {
+ { MOD_TABLE (MOD_62_32BIT) },
+ { EVEX_TABLE (EVEX_0F) },
+ },
+
+ /* X86_64_63 */
+ {
+ { "arpl", { Ew, Gw }, 0 },
+ { "movs{lq|xd}", { Gv, Ed }, 0 },
+ },
+
+ /* X86_64_6D */
+ {
+ { "ins{R|}", { Yzr, indirDX }, 0 },
+ { "ins{G|}", { Yzr, indirDX }, 0 },
+ },
+
+ /* X86_64_6F */
+ {
+ { "outs{R|}", { indirDXr, Xz }, 0 },
+ { "outs{G|}", { indirDXr, Xz }, 0 },
+ },
+
+ /* X86_64_82 */
+ {
+ /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */
+ { REG_TABLE (REG_80) },
+ },
+
+ /* X86_64_9A */
+ {
+ { "Jcall{T|}", { Ap }, 0 },
+ },
+
+ /* X86_64_C4 */
+ {
+ { MOD_TABLE (MOD_C4_32BIT) },
+ { VEX_C4_TABLE (VEX_0F) },
+ },
+
+ /* X86_64_C5 */
+ {
+ { MOD_TABLE (MOD_C5_32BIT) },
+ { VEX_C5_TABLE (VEX_0F) },
+ },
+
+ /* X86_64_CE */
+ {
+ { "into", { XX }, 0 },
+ },
+
+ /* X86_64_D4 */
+ {
+ { "aam", { Ib }, 0 },
+ },
+
+ /* X86_64_D5 */
+ {
+ { "aad", { Ib }, 0 },
+ },
+
+ /* X86_64_E8 */
+ {
+ { "callP", { Jv, BND }, 0 },
+ { "call@", { Jv, BND }, 0 }
+ },
+
+ /* X86_64_E9 */
+ {
+ { "jmpP", { Jv, BND }, 0 },
+ { "jmp@", { Jv, BND }, 0 }
+ },
+
+ /* X86_64_EA */
+ {
+ { "Jjmp{T|}", { Ap }, 0 },
+ },
+
+ /* X86_64_0F01_REG_0 */
+ {
+ { "sgdt{Q|IQ}", { M }, 0 },
+ { "sgdt", { M }, 0 },
+ },
+
+ /* X86_64_0F01_REG_1 */
+ {
+ { "sidt{Q|IQ}", { M }, 0 },
+ { "sidt", { M }, 0 },
+ },
+
+ /* X86_64_0F01_REG_2 */
+ {
+ { "lgdt{Q|Q}", { M }, 0 },
+ { "lgdt", { M }, 0 },
+ },
+
+ /* X86_64_0F01_REG_3 */
+ {
+ { "lidt{Q|Q}", { M }, 0 },
+ { "lidt", { M }, 0 },
+ },
+};
+
+static const struct dis386 three_byte_table[][256] = {
+
+ /* THREE_BYTE_0F38 */
+ {
+ /* 00 */
+ { "pshufb", { MX, EM }, PREFIX_OPCODE },
+ { "phaddw", { MX, EM }, PREFIX_OPCODE },
+ { "phaddd", { MX, EM }, PREFIX_OPCODE },
+ { "phaddsw", { MX, EM }, PREFIX_OPCODE },
+ { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
+ { "phsubw", { MX, EM }, PREFIX_OPCODE },
+ { "phsubd", { MX, EM }, PREFIX_OPCODE },
+ { "phsubsw", { MX, EM }, PREFIX_OPCODE },
+ /* 08 */
+ { "psignb", { MX, EM }, PREFIX_OPCODE },
+ { "psignw", { MX, EM }, PREFIX_OPCODE },
+ { "psignd", { MX, EM }, PREFIX_OPCODE },
+ { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 10 */
+ { PREFIX_TABLE (PREFIX_0F3810) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3814) },
+ { PREFIX_TABLE (PREFIX_0F3815) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3817) },
+ /* 18 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "pabsb", { MX, EM }, PREFIX_OPCODE },
+ { "pabsw", { MX, EM }, PREFIX_OPCODE },
+ { "pabsd", { MX, EM }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ /* 20 */
+ { PREFIX_TABLE (PREFIX_0F3820) },
+ { PREFIX_TABLE (PREFIX_0F3821) },
+ { PREFIX_TABLE (PREFIX_0F3822) },
+ { PREFIX_TABLE (PREFIX_0F3823) },
+ { PREFIX_TABLE (PREFIX_0F3824) },
+ { PREFIX_TABLE (PREFIX_0F3825) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { PREFIX_TABLE (PREFIX_0F3828) },
+ { PREFIX_TABLE (PREFIX_0F3829) },
+ { PREFIX_TABLE (PREFIX_0F382A) },
+ { PREFIX_TABLE (PREFIX_0F382B) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 30 */
+ { PREFIX_TABLE (PREFIX_0F3830) },
+ { PREFIX_TABLE (PREFIX_0F3831) },
+ { PREFIX_TABLE (PREFIX_0F3832) },
+ { PREFIX_TABLE (PREFIX_0F3833) },
+ { PREFIX_TABLE (PREFIX_0F3834) },
+ { PREFIX_TABLE (PREFIX_0F3835) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3837) },
+ /* 38 */
+ { PREFIX_TABLE (PREFIX_0F3838) },
+ { PREFIX_TABLE (PREFIX_0F3839) },
+ { PREFIX_TABLE (PREFIX_0F383A) },
+ { PREFIX_TABLE (PREFIX_0F383B) },
+ { PREFIX_TABLE (PREFIX_0F383C) },
+ { PREFIX_TABLE (PREFIX_0F383D) },
+ { PREFIX_TABLE (PREFIX_0F383E) },
+ { PREFIX_TABLE (PREFIX_0F383F) },
+ /* 40 */
+ { PREFIX_TABLE (PREFIX_0F3840) },
+ { PREFIX_TABLE (PREFIX_0F3841) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 48 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 58 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 60 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 68 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 70 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 78 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 80 */
+ { PREFIX_TABLE (PREFIX_0F3880) },
+ { PREFIX_TABLE (PREFIX_0F3881) },
+ { PREFIX_TABLE (PREFIX_0F3882) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 90 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 98 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c8 */
+ { PREFIX_TABLE (PREFIX_0F38C8) },
+ { PREFIX_TABLE (PREFIX_0F38C9) },
+ { PREFIX_TABLE (PREFIX_0F38CA) },
+ { PREFIX_TABLE (PREFIX_0F38CB) },
+ { PREFIX_TABLE (PREFIX_0F38CC) },
+ { PREFIX_TABLE (PREFIX_0F38CD) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38DB) },
+ { PREFIX_TABLE (PREFIX_0F38DC) },
+ { PREFIX_TABLE (PREFIX_0F38DD) },
+ { PREFIX_TABLE (PREFIX_0F38DE) },
+ { PREFIX_TABLE (PREFIX_0F38DF) },
+ /* e0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f0 */
+ { PREFIX_TABLE (PREFIX_0F38F0) },
+ { PREFIX_TABLE (PREFIX_0F38F1) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38F6) },
+ { Bad_Opcode },
+ /* f8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* THREE_BYTE_0F3A */
+ {
+ /* 00 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 08 */
+ { PREFIX_TABLE (PREFIX_0F3A08) },
+ { PREFIX_TABLE (PREFIX_0F3A09) },
+ { PREFIX_TABLE (PREFIX_0F3A0A) },
+ { PREFIX_TABLE (PREFIX_0F3A0B) },
+ { PREFIX_TABLE (PREFIX_0F3A0C) },
+ { PREFIX_TABLE (PREFIX_0F3A0D) },
+ { PREFIX_TABLE (PREFIX_0F3A0E) },
+ { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
+ /* 10 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3A14) },
+ { PREFIX_TABLE (PREFIX_0F3A15) },
+ { PREFIX_TABLE (PREFIX_0F3A16) },
+ { PREFIX_TABLE (PREFIX_0F3A17) },
+ /* 18 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 20 */
+ { PREFIX_TABLE (PREFIX_0F3A20) },
+ { PREFIX_TABLE (PREFIX_0F3A21) },
+ { PREFIX_TABLE (PREFIX_0F3A22) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 30 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 38 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 40 */
+ { PREFIX_TABLE (PREFIX_0F3A40) },
+ { PREFIX_TABLE (PREFIX_0F3A41) },
+ { PREFIX_TABLE (PREFIX_0F3A42) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3A44) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 48 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 58 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 60 */
+ { PREFIX_TABLE (PREFIX_0F3A60) },
+ { PREFIX_TABLE (PREFIX_0F3A61) },
+ { PREFIX_TABLE (PREFIX_0F3A62) },
+ { PREFIX_TABLE (PREFIX_0F3A63) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 68 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 70 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 78 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 80 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 90 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 98 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3ACC) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3ADF) },
+ /* e0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+
+ /* THREE_BYTE_0F7A */
+ {
+ /* 00 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 08 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 10 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 18 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 20 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 30 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 38 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 40 */
+ { Bad_Opcode },
+ { "phaddbw", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddbd", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddbq", { XM, EXq }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "phaddwd", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddwq", { XM, EXq }, PREFIX_OPCODE },
+ /* 48 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "phadddq", { XM, EXq }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { Bad_Opcode },
+ { "phaddubw", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddubd", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddubq", { XM, EXq }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "phadduwd", { XM, EXq }, PREFIX_OPCODE },
+ { "phadduwq", { XM, EXq }, PREFIX_OPCODE },
+ /* 58 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "phaddudq", { XM, EXq }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 60 */
+ { Bad_Opcode },
+ { "phsubbw", { XM, EXq }, PREFIX_OPCODE },
+ { "phsubbd", { XM, EXq }, PREFIX_OPCODE },
+ { "phsubbq", { XM, EXq }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 68 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 70 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 78 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 80 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 90 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 98 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+};
+
+static const struct dis386 xop_table[][256] = {
+ /* XOP_08 */
+ {
+ /* 00 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 08 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 10 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 18 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 20 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 30 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 38 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 40 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 48 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 58 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 60 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 68 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 70 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 78 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 80 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ /* 90 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ /* 98 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { Bad_Opcode },
+ /* a8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { Bad_Opcode },
+ /* b8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c0 */
+ { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
+ /* d0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
+ /* f0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* XOP_09 */
+ {
+ /* 00 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_XOP_TBM_01) },
+ { REG_TABLE (REG_XOP_TBM_02) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 08 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 10 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { REG_TABLE (REG_XOP_LWPCB) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 18 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 20 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 30 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 38 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 40 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 48 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 58 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 60 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 68 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 70 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 78 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 80 */
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
+ { "vfrczss", { XM, EXd }, 0 },
+ { "vfrczsd", { XM, EXq }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 90 */
+ { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ /* 98 */
+ { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c0 */
+ { Bad_Opcode },
+ { "vphaddbw", { XM, EXxmm }, 0 },
+ { "vphaddbd", { XM, EXxmm }, 0 },
+ { "vphaddbq", { XM, EXxmm }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vphaddwd", { XM, EXxmm }, 0 },
+ { "vphaddwq", { XM, EXxmm }, 0 },
+ /* c8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vphadddq", { XM, EXxmm }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d0 */
+ { Bad_Opcode },
+ { "vphaddubw", { XM, EXxmm }, 0 },
+ { "vphaddubd", { XM, EXxmm }, 0 },
+ { "vphaddubq", { XM, EXxmm }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vphadduwd", { XM, EXxmm }, 0 },
+ { "vphadduwq", { XM, EXxmm }, 0 },
+ /* d8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vphaddudq", { XM, EXxmm }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e0 */
+ { Bad_Opcode },
+ { "vphsubbw", { XM, EXxmm }, 0 },
+ { "vphsubwd", { XM, EXxmm }, 0 },
+ { "vphsubdq", { XM, EXxmm }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* XOP_0A */
+ {
+ /* 00 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 08 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 10 */
+ { "bextr", { Gv, Ev, Iq }, 0 },
+ { Bad_Opcode },
+ { REG_TABLE (REG_XOP_LWP) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 18 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 20 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 30 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 38 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 40 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 48 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 58 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 60 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 68 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 70 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 78 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 80 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 90 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 98 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+};
+
+static const struct dis386 vex_table[][256] = {
+ /* VEX_0F */
+ {
+ /* 00 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 08 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 10 */
+ { PREFIX_TABLE (PREFIX_VEX_0F10) },
+ { PREFIX_TABLE (PREFIX_VEX_0F11) },
+ { PREFIX_TABLE (PREFIX_VEX_0F12) },
+ { MOD_TABLE (MOD_VEX_0F13) },
+ { VEX_W_TABLE (VEX_W_0F14) },
+ { VEX_W_TABLE (VEX_W_0F15) },
+ { PREFIX_TABLE (PREFIX_VEX_0F16) },
+ { MOD_TABLE (MOD_VEX_0F17) },
+ /* 18 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 20 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { VEX_W_TABLE (VEX_W_0F28) },
+ { VEX_W_TABLE (VEX_W_0F29) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2A) },
+ { MOD_TABLE (MOD_VEX_0F2B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2F) },
+ /* 30 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 38 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 40 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F41) },
+ { PREFIX_TABLE (PREFIX_VEX_0F42) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F44) },
+ { PREFIX_TABLE (PREFIX_VEX_0F45) },
+ { PREFIX_TABLE (PREFIX_VEX_0F46) },
+ { PREFIX_TABLE (PREFIX_VEX_0F47) },
+ /* 48 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F4A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F4B) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { MOD_TABLE (MOD_VEX_0F50) },
+ { PREFIX_TABLE (PREFIX_VEX_0F51) },
+ { PREFIX_TABLE (PREFIX_VEX_0F52) },
+ { PREFIX_TABLE (PREFIX_VEX_0F53) },
+ { "vandpX", { XM, Vex, EXx }, 0 },
+ { "vandnpX", { XM, Vex, EXx }, 0 },
+ { "vorpX", { XM, Vex, EXx }, 0 },
+ { "vxorpX", { XM, Vex, EXx }, 0 },
+ /* 58 */
+ { PREFIX_TABLE (PREFIX_VEX_0F58) },
+ { PREFIX_TABLE (PREFIX_VEX_0F59) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5F) },
+ /* 60 */
+ { PREFIX_TABLE (PREFIX_VEX_0F60) },
+ { PREFIX_TABLE (PREFIX_VEX_0F61) },
+ { PREFIX_TABLE (PREFIX_VEX_0F62) },
+ { PREFIX_TABLE (PREFIX_VEX_0F63) },
+ { PREFIX_TABLE (PREFIX_VEX_0F64) },
+ { PREFIX_TABLE (PREFIX_VEX_0F65) },
+ { PREFIX_TABLE (PREFIX_VEX_0F66) },
+ { PREFIX_TABLE (PREFIX_VEX_0F67) },
+ /* 68 */
+ { PREFIX_TABLE (PREFIX_VEX_0F68) },
+ { PREFIX_TABLE (PREFIX_VEX_0F69) },
+ { PREFIX_TABLE (PREFIX_VEX_0F6A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F6B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F6C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F6D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F6E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F6F) },
+ /* 70 */
+ { PREFIX_TABLE (PREFIX_VEX_0F70) },
+ { REG_TABLE (REG_VEX_0F71) },
+ { REG_TABLE (REG_VEX_0F72) },
+ { REG_TABLE (REG_VEX_0F73) },
+ { PREFIX_TABLE (PREFIX_VEX_0F74) },
+ { PREFIX_TABLE (PREFIX_VEX_0F75) },
+ { PREFIX_TABLE (PREFIX_VEX_0F76) },
+ { PREFIX_TABLE (PREFIX_VEX_0F77) },
+ /* 78 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F7C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F7D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F7E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F7F) },
+ /* 80 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 90 */
+ { PREFIX_TABLE (PREFIX_VEX_0F90) },
+ { PREFIX_TABLE (PREFIX_VEX_0F91) },
+ { PREFIX_TABLE (PREFIX_VEX_0F92) },
+ { PREFIX_TABLE (PREFIX_VEX_0F93) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 98 */
+ { PREFIX_TABLE (PREFIX_VEX_0F98) },
+ { PREFIX_TABLE (PREFIX_VEX_0F99) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { REG_TABLE (REG_VEX_0FAE) },
+ { Bad_Opcode },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0FC2) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0FC4) },
+ { PREFIX_TABLE (PREFIX_VEX_0FC5) },
+ { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
+ { Bad_Opcode },
+ /* c8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d0 */
+ { PREFIX_TABLE (PREFIX_VEX_0FD0) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD1) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD2) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD3) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD4) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD5) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD6) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD7) },
+ /* d8 */
+ { PREFIX_TABLE (PREFIX_VEX_0FD8) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD9) },
+ { PREFIX_TABLE (PREFIX_VEX_0FDA) },
+ { PREFIX_TABLE (PREFIX_VEX_0FDB) },
+ { PREFIX_TABLE (PREFIX_VEX_0FDC) },
+ { PREFIX_TABLE (PREFIX_VEX_0FDD) },
+ { PREFIX_TABLE (PREFIX_VEX_0FDE) },
+ { PREFIX_TABLE (PREFIX_VEX_0FDF) },
+ /* e0 */
+ { PREFIX_TABLE (PREFIX_VEX_0FE0) },
+ { PREFIX_TABLE (PREFIX_VEX_0FE1) },
+ { PREFIX_TABLE (PREFIX_VEX_0FE2) },
+ { PREFIX_TABLE (PREFIX_VEX_0FE3) },
+ { PREFIX_TABLE (PREFIX_VEX_0FE4) },
+ { PREFIX_TABLE (PREFIX_VEX_0FE5) },
+ { PREFIX_TABLE (PREFIX_VEX_0FE6) },
+ { PREFIX_TABLE (PREFIX_VEX_0FE7) },
+ /* e8 */
+ { PREFIX_TABLE (PREFIX_VEX_0FE8) },
+ { PREFIX_TABLE (PREFIX_VEX_0FE9) },
+ { PREFIX_TABLE (PREFIX_VEX_0FEA) },
+ { PREFIX_TABLE (PREFIX_VEX_0FEB) },
+ { PREFIX_TABLE (PREFIX_VEX_0FEC) },
+ { PREFIX_TABLE (PREFIX_VEX_0FED) },
+ { PREFIX_TABLE (PREFIX_VEX_0FEE) },
+ { PREFIX_TABLE (PREFIX_VEX_0FEF) },
+ /* f0 */
+ { PREFIX_TABLE (PREFIX_VEX_0FF0) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF1) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF2) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF3) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF4) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF5) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF6) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF7) },
+ /* f8 */
+ { PREFIX_TABLE (PREFIX_VEX_0FF8) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF9) },
+ { PREFIX_TABLE (PREFIX_VEX_0FFA) },
+ { PREFIX_TABLE (PREFIX_VEX_0FFB) },
+ { PREFIX_TABLE (PREFIX_VEX_0FFC) },
+ { PREFIX_TABLE (PREFIX_VEX_0FFD) },
+ { PREFIX_TABLE (PREFIX_VEX_0FFE) },
+ { Bad_Opcode },
+ },
+ /* VEX_0F38 */
+ {
+ /* 00 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3800) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3801) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3802) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3803) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3804) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3805) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3806) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3807) },
+ /* 08 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3808) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3809) },
+ { PREFIX_TABLE (PREFIX_VEX_0F380A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F380B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F380C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F380D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F380E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F380F) },
+ /* 10 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3813) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3816) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3817) },
+ /* 18 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3818) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3819) },
+ { PREFIX_TABLE (PREFIX_VEX_0F381A) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F381C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F381D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F381E) },
+ { Bad_Opcode },
+ /* 20 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3820) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3821) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3822) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3823) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3824) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3825) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3828) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3829) },
+ { PREFIX_TABLE (PREFIX_VEX_0F382A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F382B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F382C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F382D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F382E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F382F) },
+ /* 30 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3830) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3831) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3832) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3833) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3834) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3835) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3836) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3837) },
+ /* 38 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3838) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3839) },
+ { PREFIX_TABLE (PREFIX_VEX_0F383A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F383B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F383C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F383D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F383E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F383F) },
+ /* 40 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3840) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3841) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3845) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3846) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3847) },
+ /* 48 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 58 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3858) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3859) },
+ { PREFIX_TABLE (PREFIX_VEX_0F385A) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 60 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 68 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 70 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 78 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3878) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3879) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 80 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F388C) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F388E) },
+ { Bad_Opcode },
+ /* 90 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3890) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3891) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3892) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3893) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3896) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3897) },
+ /* 98 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3898) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3899) },
+ { PREFIX_TABLE (PREFIX_VEX_0F389A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F389B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F389C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F389D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F389E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F389F) },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
+ /* a8 */
+ { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
+ /* b8 */
+ { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
+ /* c0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
+ /* e0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
+ { REG_TABLE (REG_VEX_0F38F3) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
+ /* f8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* VEX_0F3A */
+ {
+ /* 00 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
+ { Bad_Opcode },
+ /* 08 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
+ /* 10 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
+ /* 18 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 20 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 28 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 30 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 38 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 40 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
+ { Bad_Opcode },
+ /* 48 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 50 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 58 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
+ /* 60 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 68 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
+ /* 70 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 78 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
+ /* 80 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 88 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 90 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* 98 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* a8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* b8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* c8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* d8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
+ /* e0 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* e8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f0 */
+ { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ /* f8 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+};
+
+#define NEED_OPCODE_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_OPCODE_TABLE
+static const struct dis386 vex_len_table[][2] = {
+ /* VEX_LEN_0F10_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F10_P_1) },
+ { VEX_W_TABLE (VEX_W_0F10_P_1) },
+ },
+
+ /* VEX_LEN_0F10_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F10_P_3) },
+ { VEX_W_TABLE (VEX_W_0F10_P_3) },
+ },
+
+ /* VEX_LEN_0F11_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F11_P_1) },
+ { VEX_W_TABLE (VEX_W_0F11_P_1) },
+ },
+
+ /* VEX_LEN_0F11_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F11_P_3) },
+ { VEX_W_TABLE (VEX_W_0F11_P_3) },
+ },
+
+ /* VEX_LEN_0F12_P_0_M_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
+ },
+
+ /* VEX_LEN_0F12_P_0_M_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
+ },
+
+ /* VEX_LEN_0F12_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F12_P_2) },
+ },
+
+ /* VEX_LEN_0F13_M_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F13_M_0) },
+ },
+
+ /* VEX_LEN_0F16_P_0_M_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
+ },
+
+ /* VEX_LEN_0F16_P_0_M_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
+ },
+
+ /* VEX_LEN_0F16_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F16_P_2) },
+ },
+
+ /* VEX_LEN_0F17_M_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F17_M_0) },
+ },
+
+ /* VEX_LEN_0F2A_P_1 */
+ {
+ { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
+ { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
+ },
+
+ /* VEX_LEN_0F2A_P_3 */
+ {
+ { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
+ { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
+ },
+
+ /* VEX_LEN_0F2C_P_1 */
+ {
+ { "vcvttss2siY", { Gv, EXdScalar }, 0 },
+ { "vcvttss2siY", { Gv, EXdScalar }, 0 },
+ },
+
+ /* VEX_LEN_0F2C_P_3 */
+ {
+ { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
+ { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
+ },
+
+ /* VEX_LEN_0F2D_P_1 */
+ {
+ { "vcvtss2siY", { Gv, EXdScalar }, 0 },
+ { "vcvtss2siY", { Gv, EXdScalar }, 0 },
+ },
+
+ /* VEX_LEN_0F2D_P_3 */
+ {
+ { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
+ { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
+ },
+
+ /* VEX_LEN_0F2E_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F2E_P_0) },
+ { VEX_W_TABLE (VEX_W_0F2E_P_0) },
+ },
+
+ /* VEX_LEN_0F2E_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F2E_P_2) },
+ { VEX_W_TABLE (VEX_W_0F2E_P_2) },
+ },
+
+ /* VEX_LEN_0F2F_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F2F_P_0) },
+ { VEX_W_TABLE (VEX_W_0F2F_P_0) },
+ },
+
+ /* VEX_LEN_0F2F_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F2F_P_2) },
+ { VEX_W_TABLE (VEX_W_0F2F_P_2) },
+ },
+
+ /* VEX_LEN_0F41_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F41_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F42_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F42_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F44_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
+ },
+ /* VEX_LEN_0F44_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
+ },
+ /* VEX_LEN_0F45_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F45_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F46_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F46_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F47_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F47_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F4A_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F4A_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F4B_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F4B_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
+ },
+
+ /* VEX_LEN_0F51_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F51_P_1) },
+ { VEX_W_TABLE (VEX_W_0F51_P_1) },
+ },
+
+ /* VEX_LEN_0F51_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F51_P_3) },
+ { VEX_W_TABLE (VEX_W_0F51_P_3) },
+ },
+
+ /* VEX_LEN_0F52_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F52_P_1) },
+ { VEX_W_TABLE (VEX_W_0F52_P_1) },
+ },
+
+ /* VEX_LEN_0F53_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F53_P_1) },
+ { VEX_W_TABLE (VEX_W_0F53_P_1) },
+ },
+
+ /* VEX_LEN_0F58_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F58_P_1) },
+ { VEX_W_TABLE (VEX_W_0F58_P_1) },
+ },
+
+ /* VEX_LEN_0F58_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F58_P_3) },
+ { VEX_W_TABLE (VEX_W_0F58_P_3) },
+ },
+
+ /* VEX_LEN_0F59_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F59_P_1) },
+ { VEX_W_TABLE (VEX_W_0F59_P_1) },
+ },
+
+ /* VEX_LEN_0F59_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F59_P_3) },
+ { VEX_W_TABLE (VEX_W_0F59_P_3) },
+ },
+
+ /* VEX_LEN_0F5A_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5A_P_1) },
+ { VEX_W_TABLE (VEX_W_0F5A_P_1) },
+ },
+
+ /* VEX_LEN_0F5A_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5A_P_3) },
+ { VEX_W_TABLE (VEX_W_0F5A_P_3) },
+ },
+
+ /* VEX_LEN_0F5C_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5C_P_1) },
+ { VEX_W_TABLE (VEX_W_0F5C_P_1) },
+ },
+
+ /* VEX_LEN_0F5C_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5C_P_3) },
+ { VEX_W_TABLE (VEX_W_0F5C_P_3) },
+ },
+
+ /* VEX_LEN_0F5D_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5D_P_1) },
+ { VEX_W_TABLE (VEX_W_0F5D_P_1) },
+ },
+
+ /* VEX_LEN_0F5D_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5D_P_3) },
+ { VEX_W_TABLE (VEX_W_0F5D_P_3) },
+ },
+
+ /* VEX_LEN_0F5E_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5E_P_1) },
+ { VEX_W_TABLE (VEX_W_0F5E_P_1) },
+ },
+
+ /* VEX_LEN_0F5E_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5E_P_3) },
+ { VEX_W_TABLE (VEX_W_0F5E_P_3) },
+ },
+
+ /* VEX_LEN_0F5F_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5F_P_1) },
+ { VEX_W_TABLE (VEX_W_0F5F_P_1) },
+ },
+
+ /* VEX_LEN_0F5F_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F5F_P_3) },
+ { VEX_W_TABLE (VEX_W_0F5F_P_3) },
+ },
+
+ /* VEX_LEN_0F6E_P_2 */
+ {
+ { "vmovK", { XMScalar, Edq }, 0 },
+ { "vmovK", { XMScalar, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F7E_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0F7E_P_1) },
+ { VEX_W_TABLE (VEX_W_0F7E_P_1) },
+ },
+
+ /* VEX_LEN_0F7E_P_2 */
+ {
+ { "vmovK", { Edq, XMScalar }, 0 },
+ { "vmovK", { Edq, XMScalar }, 0 },
+ },
+
+ /* VEX_LEN_0F90_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
+ },
+
+ /* VEX_LEN_0F90_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F91_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
+ },
+
+ /* VEX_LEN_0F91_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F92_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
+ },
+
+ /* VEX_LEN_0F92_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F92_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
+ },
+
+ /* VEX_LEN_0F93_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
+ },
+
+ /* VEX_LEN_0F93_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F93_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
+ },
+
+ /* VEX_LEN_0F98_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
+ },
+
+ /* VEX_LEN_0F98_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F99_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
+ },
+
+ /* VEX_LEN_0F99_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0FAE_R_2_M_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
+ },
+
+ /* VEX_LEN_0FAE_R_3_M_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
+ },
+
+ /* VEX_LEN_0FC2_P_1 */
+ {
+ { VEX_W_TABLE (VEX_W_0FC2_P_1) },
+ { VEX_W_TABLE (VEX_W_0FC2_P_1) },
+ },
+
+ /* VEX_LEN_0FC2_P_3 */
+ {
+ { VEX_W_TABLE (VEX_W_0FC2_P_3) },
+ { VEX_W_TABLE (VEX_W_0FC2_P_3) },
+ },
+
+ /* VEX_LEN_0FC4_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0FC4_P_2) },
+ },
+
+ /* VEX_LEN_0FC5_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0FC5_P_2) },
+ },
+
+ /* VEX_LEN_0FD6_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0FD6_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD6_P_2) },
+ },
+
+ /* VEX_LEN_0FF7_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0FF7_P_2) },
+ },
+
+ /* VEX_LEN_0F3816_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3816_P_2) },
+ },
+
+ /* VEX_LEN_0F3819_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3819_P_2) },
+ },
+
+ /* VEX_LEN_0F381A_P_2_M_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
+ },
+
+ /* VEX_LEN_0F3836_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3836_P_2) },
+ },
+
+ /* VEX_LEN_0F3841_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3841_P_2) },
+ },
+
+ /* VEX_LEN_0F385A_P_2_M_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
+ },
+
+ /* VEX_LEN_0F38DB_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
+ },
+
+ /* VEX_LEN_0F38DC_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
+ },
+
+ /* VEX_LEN_0F38DD_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
+ },
+
+ /* VEX_LEN_0F38DE_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
+ },
+
+ /* VEX_LEN_0F38DF_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
+ },
+
+ /* VEX_LEN_0F38F2_P_0 */
+ {
+ { "andnS", { Gdq, VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F3_R_1_P_0 */
+ {
+ { "blsrS", { VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F3_R_2_P_0 */
+ {
+ { "blsmskS", { VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F3_R_3_P_0 */
+ {
+ { "blsiS", { VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F5_P_0 */
+ {
+ { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F5_P_1 */
+ {
+ { "pextS", { Gdq, VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F5_P_3 */
+ {
+ { "pdepS", { Gdq, VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F6_P_3 */
+ {
+ { "mulxS", { Gdq, VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F7_P_0 */
+ {
+ { "bextrS", { Gdq, Edq, VexGdq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F7_P_1 */
+ {
+ { "sarxS", { Gdq, Edq, VexGdq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F7_P_2 */
+ {
+ { "shlxS", { Gdq, Edq, VexGdq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F7_P_3 */
+ {
+ { "shrxS", { Gdq, Edq, VexGdq }, 0 },
+ },
+
+ /* VEX_LEN_0F3A00_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
+ },
+
+ /* VEX_LEN_0F3A01_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
+ },
+
+ /* VEX_LEN_0F3A06_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
+ },
+
+ /* VEX_LEN_0F3A0A_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
+ },
+
+ /* VEX_LEN_0F3A0B_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
+ },
+
+ /* VEX_LEN_0F3A14_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
+ },
+
+ /* VEX_LEN_0F3A15_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
+ },
+
+ /* VEX_LEN_0F3A16_P_2 */
+ {
+ { "vpextrK", { Edq, XM, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0F3A17_P_2 */
+ {
+ { "vextractps", { Edqd, XM, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0F3A18_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
+ },
+
+ /* VEX_LEN_0F3A19_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
+ },
+
+ /* VEX_LEN_0F3A20_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
+ },
+
+ /* VEX_LEN_0F3A21_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
+ },
+
+ /* VEX_LEN_0F3A22_P_2 */
+ {
+ { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0F3A30_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F3A31_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F3A32_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F3A33_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
+ },
+
+ /* VEX_LEN_0F3A38_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
+ },
+
+ /* VEX_LEN_0F3A39_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
+ },
+
+ /* VEX_LEN_0F3A41_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
+ },
+
+ /* VEX_LEN_0F3A44_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
+ },
+
+ /* VEX_LEN_0F3A46_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
+ },
+
+ /* VEX_LEN_0F3A60_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
+ },
+
+ /* VEX_LEN_0F3A61_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
+ },
+
+ /* VEX_LEN_0F3A62_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
+ },
+
+ /* VEX_LEN_0F3A63_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
+ },
+
+ /* VEX_LEN_0F3A6A_P_2 */
+ {
+ { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0F3A6B_P_2 */
+ {
+ { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0F3A6E_P_2 */
+ {
+ { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0F3A6F_P_2 */
+ {
+ { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0F3A7A_P_2 */
+ {
+ { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0F3A7B_P_2 */
+ {
+ { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0F3A7E_P_2 */
+ {
+ { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0F3A7F_P_2 */
+ {
+ { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
+ },
+
+ /* VEX_LEN_0F3ADF_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
+ },
+
+ /* VEX_LEN_0F3AF0_P_3 */
+ {
+ { "rorxS", { Gdq, Edq, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_CC */
+ {
+ { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_CD */
+ {
+ { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_CE */
+ {
+ { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_CF */
+ {
+ { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_EC */
+ {
+ { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_ED */
+ {
+ { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_EE */
+ {
+ { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_08_EF */
+ {
+ { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_09_80 */
+ {
+ { "vfrczps", { XM, EXxmm }, 0 },
+ { "vfrczps", { XM, EXymmq }, 0 },
+ },
+
+ /* VEX_LEN_0FXOP_09_81 */
+ {
+ { "vfrczpd", { XM, EXxmm }, 0 },
+ { "vfrczpd", { XM, EXymmq }, 0 },
+ },
+};
+
+static const struct dis386 vex_w_table[][2] = {
+ {
+ /* VEX_W_0F10_P_0 */
+ { "vmovups", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F10_P_1 */
+ { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F10_P_2 */
+ { "vmovupd", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F10_P_3 */
+ { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F11_P_0 */
+ { "vmovups", { EXxS, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F11_P_1 */
+ { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F11_P_2 */
+ { "vmovupd", { EXxS, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F11_P_3 */
+ { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F12_P_0_M_0 */
+ { "vmovlps", { XM, Vex128, EXq }, 0 },
+ },
+ {
+ /* VEX_W_0F12_P_0_M_1 */
+ { "vmovhlps", { XM, Vex128, EXq }, 0 },
+ },
+ {
+ /* VEX_W_0F12_P_1 */
+ { "vmovsldup", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F12_P_2 */
+ { "vmovlpd", { XM, Vex128, EXq }, 0 },
+ },
+ {
+ /* VEX_W_0F12_P_3 */
+ { "vmovddup", { XM, EXymmq }, 0 },
+ },
+ {
+ /* VEX_W_0F13_M_0 */
+ { "vmovlpX", { EXq, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F14 */
+ { "vunpcklpX", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F15 */
+ { "vunpckhpX", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F16_P_0_M_0 */
+ { "vmovhps", { XM, Vex128, EXq }, 0 },
+ },
+ {
+ /* VEX_W_0F16_P_0_M_1 */
+ { "vmovlhps", { XM, Vex128, EXq }, 0 },
+ },
+ {
+ /* VEX_W_0F16_P_1 */
+ { "vmovshdup", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F16_P_2 */
+ { "vmovhpd", { XM, Vex128, EXq }, 0 },
+ },
+ {
+ /* VEX_W_0F17_M_0 */
+ { "vmovhpX", { EXq, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F28 */
+ { "vmovapX", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F29 */
+ { "vmovapX", { EXxS, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F2B_M_0 */
+ { "vmovntpX", { Mx, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F2E_P_0 */
+ { "vucomiss", { XMScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F2E_P_2 */
+ { "vucomisd", { XMScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F2F_P_0 */
+ { "vcomiss", { XMScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F2F_P_2 */
+ { "vcomisd", { XMScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F41_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F41_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
+ },
+ {
+ /* VEX_W_0F42_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F42_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F44_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F44_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F45_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F45_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F46_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F46_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F47_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F47_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F4A_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F4A_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F4B_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F4B_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F50_M_0 */
+ { "vmovmskpX", { Gdq, XS }, 0 },
+ },
+ {
+ /* VEX_W_0F51_P_0 */
+ { "vsqrtps", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F51_P_1 */
+ { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F51_P_2 */
+ { "vsqrtpd", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F51_P_3 */
+ { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F52_P_0 */
+ { "vrsqrtps", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F52_P_1 */
+ { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F53_P_0 */
+ { "vrcpps", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F53_P_1 */
+ { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F58_P_0 */
+ { "vaddps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F58_P_1 */
+ { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F58_P_2 */
+ { "vaddpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F58_P_3 */
+ { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F59_P_0 */
+ { "vmulps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F59_P_1 */
+ { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F59_P_2 */
+ { "vmulpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F59_P_3 */
+ { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5A_P_0 */
+ { "vcvtps2pd", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0F5A_P_1 */
+ { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5A_P_3 */
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5B_P_0 */
+ { "vcvtdq2ps", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5B_P_1 */
+ { "vcvttps2dq", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5B_P_2 */
+ { "vcvtps2dq", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5C_P_0 */
+ { "vsubps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5C_P_1 */
+ { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5C_P_2 */
+ { "vsubpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5C_P_3 */
+ { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5D_P_0 */
+ { "vminps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5D_P_1 */
+ { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5D_P_2 */
+ { "vminpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5D_P_3 */
+ { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5E_P_0 */
+ { "vdivps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5E_P_1 */
+ { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5E_P_2 */
+ { "vdivpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5E_P_3 */
+ { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5F_P_0 */
+ { "vmaxps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5F_P_1 */
+ { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F5F_P_2 */
+ { "vmaxpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F5F_P_3 */
+ { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F60_P_2 */
+ { "vpunpcklbw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F61_P_2 */
+ { "vpunpcklwd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F62_P_2 */
+ { "vpunpckldq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F63_P_2 */
+ { "vpacksswb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F64_P_2 */
+ { "vpcmpgtb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F65_P_2 */
+ { "vpcmpgtw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F66_P_2 */
+ { "vpcmpgtd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F67_P_2 */
+ { "vpackuswb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F68_P_2 */
+ { "vpunpckhbw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F69_P_2 */
+ { "vpunpckhwd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F6A_P_2 */
+ { "vpunpckhdq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F6B_P_2 */
+ { "vpackssdw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F6C_P_2 */
+ { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F6D_P_2 */
+ { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F6F_P_1 */
+ { "vmovdqu", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F6F_P_2 */
+ { "vmovdqa", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F70_P_1 */
+ { "vpshufhw", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F70_P_2 */
+ { "vpshufd", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F70_P_3 */
+ { "vpshuflw", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F71_R_2_P_2 */
+ { "vpsrlw", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F71_R_4_P_2 */
+ { "vpsraw", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F71_R_6_P_2 */
+ { "vpsllw", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F72_R_2_P_2 */
+ { "vpsrld", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F72_R_4_P_2 */
+ { "vpsrad", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F72_R_6_P_2 */
+ { "vpslld", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F73_R_2_P_2 */
+ { "vpsrlq", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F73_R_3_P_2 */
+ { "vpsrldq", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F73_R_6_P_2 */
+ { "vpsllq", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F73_R_7_P_2 */
+ { "vpslldq", { Vex, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F74_P_2 */
+ { "vpcmpeqb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F75_P_2 */
+ { "vpcmpeqw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F76_P_2 */
+ { "vpcmpeqd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F77_P_0 */
+ { "", { VZERO }, 0 },
+ },
+ {
+ /* VEX_W_0F7C_P_2 */
+ { "vhaddpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F7C_P_3 */
+ { "vhaddps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F7D_P_2 */
+ { "vhsubpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F7D_P_3 */
+ { "vhsubps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F7E_P_1 */
+ { "vmovq", { XMScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F7F_P_1 */
+ { "vmovdqu", { EXxS, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F7F_P_2 */
+ { "vmovdqa", { EXxS, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F90_P_0_LEN_0 */
+ { "kmovw", { MaskG, MaskE }, 0 },
+ { "kmovq", { MaskG, MaskE }, 0 },
+ },
+ {
+ /* VEX_W_0F90_P_2_LEN_0 */
+ { "kmovb", { MaskG, MaskBDE }, 0 },
+ { "kmovd", { MaskG, MaskBDE }, 0 },
+ },
+ {
+ /* VEX_W_0F91_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F91_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F92_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F92_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F92_P_3_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
+ },
+ {
+ /* VEX_W_0F93_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F93_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F93_P_3_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
+ },
+ {
+ /* VEX_W_0F98_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F98_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F99_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F99_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0FAE_R_2_M_0 */
+ { "vldmxcsr", { Md }, 0 },
+ },
+ {
+ /* VEX_W_0FAE_R_3_M_0 */
+ { "vstmxcsr", { Md }, 0 },
+ },
+ {
+ /* VEX_W_0FC2_P_0 */
+ { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
+ },
+ {
+ /* VEX_W_0FC2_P_1 */
+ { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
+ },
+ {
+ /* VEX_W_0FC2_P_2 */
+ { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
+ },
+ {
+ /* VEX_W_0FC2_P_3 */
+ { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
+ },
+ {
+ /* VEX_W_0FC4_P_2 */
+ { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0FC5_P_2 */
+ { "vpextrw", { Gdq, XS, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0FD0_P_2 */
+ { "vaddsubpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FD0_P_3 */
+ { "vaddsubps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FD1_P_2 */
+ { "vpsrlw", { XM, Vex, EXxmm }, 0 },
+ },
+ {
+ /* VEX_W_0FD2_P_2 */
+ { "vpsrld", { XM, Vex, EXxmm }, 0 },
+ },
+ {
+ /* VEX_W_0FD3_P_2 */
+ { "vpsrlq", { XM, Vex, EXxmm }, 0 },
+ },
+ {
+ /* VEX_W_0FD4_P_2 */
+ { "vpaddq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FD5_P_2 */
+ { "vpmullw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FD6_P_2 */
+ { "vmovq", { EXqScalarS, XMScalar }, 0 },
+ },
+ {
+ /* VEX_W_0FD7_P_2_M_1 */
+ { "vpmovmskb", { Gdq, XS }, 0 },
+ },
+ {
+ /* VEX_W_0FD8_P_2 */
+ { "vpsubusb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FD9_P_2 */
+ { "vpsubusw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FDA_P_2 */
+ { "vpminub", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FDB_P_2 */
+ { "vpand", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FDC_P_2 */
+ { "vpaddusb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FDD_P_2 */
+ { "vpaddusw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FDE_P_2 */
+ { "vpmaxub", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FDF_P_2 */
+ { "vpandn", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FE0_P_2 */
+ { "vpavgb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FE1_P_2 */
+ { "vpsraw", { XM, Vex, EXxmm }, 0 },
+ },
+ {
+ /* VEX_W_0FE2_P_2 */
+ { "vpsrad", { XM, Vex, EXxmm }, 0 },
+ },
+ {
+ /* VEX_W_0FE3_P_2 */
+ { "vpavgw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FE4_P_2 */
+ { "vpmulhuw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FE5_P_2 */
+ { "vpmulhw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FE6_P_1 */
+ { "vcvtdq2pd", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0FE6_P_2 */
+ { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FE6_P_3 */
+ { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FE7_P_2_M_0 */
+ { "vmovntdq", { Mx, XM }, 0 },
+ },
+ {
+ /* VEX_W_0FE8_P_2 */
+ { "vpsubsb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FE9_P_2 */
+ { "vpsubsw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FEA_P_2 */
+ { "vpminsw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FEB_P_2 */
+ { "vpor", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FEC_P_2 */
+ { "vpaddsb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FED_P_2 */
+ { "vpaddsw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FEE_P_2 */
+ { "vpmaxsw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FEF_P_2 */
+ { "vpxor", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FF0_P_3_M_0 */
+ { "vlddqu", { XM, M }, 0 },
+ },
+ {
+ /* VEX_W_0FF1_P_2 */
+ { "vpsllw", { XM, Vex, EXxmm }, 0 },
+ },
+ {
+ /* VEX_W_0FF2_P_2 */
+ { "vpslld", { XM, Vex, EXxmm }, 0 },
+ },
+ {
+ /* VEX_W_0FF3_P_2 */
+ { "vpsllq", { XM, Vex, EXxmm }, 0 },
+ },
+ {
+ /* VEX_W_0FF4_P_2 */
+ { "vpmuludq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FF5_P_2 */
+ { "vpmaddwd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FF6_P_2 */
+ { "vpsadbw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FF7_P_2 */
+ { "vmaskmovdqu", { XM, XS }, 0 },
+ },
+ {
+ /* VEX_W_0FF8_P_2 */
+ { "vpsubb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FF9_P_2 */
+ { "vpsubw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FFA_P_2 */
+ { "vpsubd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FFB_P_2 */
+ { "vpsubq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FFC_P_2 */
+ { "vpaddb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FFD_P_2 */
+ { "vpaddw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0FFE_P_2 */
+ { "vpaddd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3800_P_2 */
+ { "vpshufb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3801_P_2 */
+ { "vphaddw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3802_P_2 */
+ { "vphaddd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3803_P_2 */
+ { "vphaddsw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3804_P_2 */
+ { "vpmaddubsw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3805_P_2 */
+ { "vphsubw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3806_P_2 */
+ { "vphsubd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3807_P_2 */
+ { "vphsubsw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3808_P_2 */
+ { "vpsignb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3809_P_2 */
+ { "vpsignw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F380A_P_2 */
+ { "vpsignd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F380B_P_2 */
+ { "vpmulhrsw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F380C_P_2 */
+ { "vpermilps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F380D_P_2 */
+ { "vpermilpd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F380E_P_2 */
+ { "vtestps", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F380F_P_2 */
+ { "vtestpd", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3816_P_2 */
+ { "vpermps", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3817_P_2 */
+ { "vptest", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3818_P_2 */
+ { "vbroadcastss", { XM, EXxmm_md }, 0 },
+ },
+ {
+ /* VEX_W_0F3819_P_2 */
+ { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
+ },
+ {
+ /* VEX_W_0F381A_P_2_M_0 */
+ { "vbroadcastf128", { XM, Mxmm }, 0 },
+ },
+ {
+ /* VEX_W_0F381C_P_2 */
+ { "vpabsb", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F381D_P_2 */
+ { "vpabsw", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F381E_P_2 */
+ { "vpabsd", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3820_P_2 */
+ { "vpmovsxbw", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0F3821_P_2 */
+ { "vpmovsxbd", { XM, EXxmmqd }, 0 },
+ },
+ {
+ /* VEX_W_0F3822_P_2 */
+ { "vpmovsxbq", { XM, EXxmmdw }, 0 },
+ },
+ {
+ /* VEX_W_0F3823_P_2 */
+ { "vpmovsxwd", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0F3824_P_2 */
+ { "vpmovsxwq", { XM, EXxmmqd }, 0 },
+ },
+ {
+ /* VEX_W_0F3825_P_2 */
+ { "vpmovsxdq", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0F3828_P_2 */
+ { "vpmuldq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3829_P_2 */
+ { "vpcmpeqq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F382A_P_2_M_0 */
+ { "vmovntdqa", { XM, Mx }, 0 },
+ },
+ {
+ /* VEX_W_0F382B_P_2 */
+ { "vpackusdw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F382C_P_2_M_0 */
+ { "vmaskmovps", { XM, Vex, Mx }, 0 },
+ },
+ {
+ /* VEX_W_0F382D_P_2_M_0 */
+ { "vmaskmovpd", { XM, Vex, Mx }, 0 },
+ },
+ {
+ /* VEX_W_0F382E_P_2_M_0 */
+ { "vmaskmovps", { Mx, Vex, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F382F_P_2_M_0 */
+ { "vmaskmovpd", { Mx, Vex, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F3830_P_2 */
+ { "vpmovzxbw", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0F3831_P_2 */
+ { "vpmovzxbd", { XM, EXxmmqd }, 0 },
+ },
+ {
+ /* VEX_W_0F3832_P_2 */
+ { "vpmovzxbq", { XM, EXxmmdw }, 0 },
+ },
+ {
+ /* VEX_W_0F3833_P_2 */
+ { "vpmovzxwd", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0F3834_P_2 */
+ { "vpmovzxwq", { XM, EXxmmqd }, 0 },
+ },
+ {
+ /* VEX_W_0F3835_P_2 */
+ { "vpmovzxdq", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0F3836_P_2 */
+ { "vpermd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3837_P_2 */
+ { "vpcmpgtq", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3838_P_2 */
+ { "vpminsb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3839_P_2 */
+ { "vpminsd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F383A_P_2 */
+ { "vpminuw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F383B_P_2 */
+ { "vpminud", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F383C_P_2 */
+ { "vpmaxsb", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F383D_P_2 */
+ { "vpmaxsd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F383E_P_2 */
+ { "vpmaxuw", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F383F_P_2 */
+ { "vpmaxud", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3840_P_2 */
+ { "vpmulld", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3841_P_2 */
+ { "vphminposuw", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3846_P_2 */
+ { "vpsravd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3858_P_2 */
+ { "vpbroadcastd", { XM, EXxmm_md }, 0 },
+ },
+ {
+ /* VEX_W_0F3859_P_2 */
+ { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
+ },
+ {
+ /* VEX_W_0F385A_P_2_M_0 */
+ { "vbroadcasti128", { XM, Mxmm }, 0 },
+ },
+ {
+ /* VEX_W_0F3878_P_2 */
+ { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
+ },
+ {
+ /* VEX_W_0F3879_P_2 */
+ { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
+ },
+ {
+ /* VEX_W_0F38DB_P_2 */
+ { "vaesimc", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F38DC_P_2 */
+ { "vaesenc", { XM, Vex128, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F38DD_P_2 */
+ { "vaesenclast", { XM, Vex128, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F38DE_P_2 */
+ { "vaesdec", { XM, Vex128, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F38DF_P_2 */
+ { "vaesdeclast", { XM, Vex128, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3A00_P_2 */
+ { Bad_Opcode },
+ { "vpermq", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A01_P_2 */
+ { Bad_Opcode },
+ { "vpermpd", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A02_P_2 */
+ { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A04_P_2 */
+ { "vpermilps", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A05_P_2 */
+ { "vpermilpd", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A06_P_2 */
+ { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A08_P_2 */
+ { "vroundps", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A09_P_2 */
+ { "vroundpd", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A0A_P_2 */
+ { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A0B_P_2 */
+ { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A0C_P_2 */
+ { "vblendps", { XM, Vex, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A0D_P_2 */
+ { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A0E_P_2 */
+ { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A0F_P_2 */
+ { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A14_P_2 */
+ { "vpextrb", { Edqb, XM, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A15_P_2 */
+ { "vpextrw", { Edqw, XM, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A18_P_2 */
+ { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A19_P_2 */
+ { "vextractf128", { EXxmm, XM, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A20_P_2 */
+ { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A21_P_2 */
+ { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A30_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F3A31_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F3A32_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F3A33_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F3A38_P_2 */
+ { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A39_P_2 */
+ { "vextracti128", { EXxmm, XM, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A40_P_2 */
+ { "vdpps", { XM, Vex, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A41_P_2 */
+ { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A42_P_2 */
+ { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A44_P_2 */
+ { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
+ },
+ {
+ /* VEX_W_0F3A46_P_2 */
+ { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A48_P_2 */
+ { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ },
+ {
+ /* VEX_W_0F3A49_P_2 */
+ { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ },
+ {
+ /* VEX_W_0F3A4A_P_2 */
+ { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ {
+ /* VEX_W_0F3A4B_P_2 */
+ { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ {
+ /* VEX_W_0F3A4C_P_2 */
+ { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ {
+ /* VEX_W_0F3A60_P_2 */
+ { "vpcmpestrm", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A61_P_2 */
+ { "vpcmpestri", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A62_P_2 */
+ { "vpcmpistrm", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A63_P_2 */
+ { "vpcmpistri", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3ADF_P_2 */
+ { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
+ },
+#define NEED_VEX_W_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_VEX_W_TABLE
+};
+
+static const struct dis386 mod_table[][2] = {
+ {
+ /* MOD_8D */
+ { "leaS", { Gv, M }, 0 },
+ },
+ {
+ /* MOD_C6_REG_7 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_C6_REG_7) },
+ },
+ {
+ /* MOD_C7_REG_7 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_C7_REG_7) },
+ },
+ {
+ /* MOD_FF_REG_3 */
+ { "Jcall^", { indirEp }, 0 },
+ },
+ {
+ /* MOD_FF_REG_5 */
+ { "Jjmp^", { indirEp }, 0 },
+ },
+ {
+ /* MOD_0F01_REG_0 */
+ { X86_64_TABLE (X86_64_0F01_REG_0) },
+ { RM_TABLE (RM_0F01_REG_0) },
+ },
+ {
+ /* MOD_0F01_REG_1 */
+ { X86_64_TABLE (X86_64_0F01_REG_1) },
+ { RM_TABLE (RM_0F01_REG_1) },
+ },
+ {
+ /* MOD_0F01_REG_2 */
+ { X86_64_TABLE (X86_64_0F01_REG_2) },
+ { RM_TABLE (RM_0F01_REG_2) },
+ },
+ {
+ /* MOD_0F01_REG_3 */
+ { X86_64_TABLE (X86_64_0F01_REG_3) },
+ { RM_TABLE (RM_0F01_REG_3) },
+ },
+ {
+ /* MOD_0F01_REG_5 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_0F01_REG_5) },
+ },
+ {
+ /* MOD_0F01_REG_7 */
+ { "invlpg", { Mb }, 0 },
+ { RM_TABLE (RM_0F01_REG_7) },
+ },
+ {
+ /* MOD_0F12_PREFIX_0 */
+ { "movlps", { XM, EXq }, PREFIX_OPCODE },
+ { "movhlps", { XM, EXq }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F13 */
+ { "movlpX", { EXq, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F16_PREFIX_0 */
+ { "movhps", { XM, EXq }, 0 },
+ { "movlhps", { XM, EXq }, 0 },
+ },
+ {
+ /* MOD_0F17 */
+ { "movhpX", { EXq, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F18_REG_0 */
+ { "prefetchnta", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_1 */
+ { "prefetcht0", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_2 */
+ { "prefetcht1", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_3 */
+ { "prefetcht2", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_4 */
+ { "nop/reserved", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_5 */
+ { "nop/reserved", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_6 */
+ { "nop/reserved", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_7 */
+ { "nop/reserved", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F1A_PREFIX_0 */
+ { "bndldx", { Gbnd, Ev_bnd }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F1B_PREFIX_0 */
+ { "bndstx", { Ev_bnd, Gbnd }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F1B_PREFIX_1 */
+ { "bndmk", { Gbnd, Ev_bnd }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F24 */
+ { Bad_Opcode },
+ { "movL", { Rd, Td }, 0 },
+ },
+ {
+ /* MOD_0F26 */
+ { Bad_Opcode },
+ { "movL", { Td, Rd }, 0 },
+ },
+ {
+ /* MOD_0F2B_PREFIX_0 */
+ {"movntps", { Mx, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F2B_PREFIX_1 */
+ {"movntss", { Md, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F2B_PREFIX_2 */
+ {"movntpd", { Mx, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F2B_PREFIX_3 */
+ {"movntsd", { Mq, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F51 */
+ { Bad_Opcode },
+ { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F71_REG_2 */
+ { Bad_Opcode },
+ { "psrlw", { MS, Ib }, 0 },
+ },
+ {
+ /* MOD_0F71_REG_4 */
+ { Bad_Opcode },
+ { "psraw", { MS, Ib }, 0 },
+ },
+ {
+ /* MOD_0F71_REG_6 */
+ { Bad_Opcode },
+ { "psllw", { MS, Ib }, 0 },
+ },
+ {
+ /* MOD_0F72_REG_2 */
+ { Bad_Opcode },
+ { "psrld", { MS, Ib }, 0 },
+ },
+ {
+ /* MOD_0F72_REG_4 */
+ { Bad_Opcode },
+ { "psrad", { MS, Ib }, 0 },
+ },
+ {
+ /* MOD_0F72_REG_6 */
+ { Bad_Opcode },
+ { "pslld", { MS, Ib }, 0 },
+ },
+ {
+ /* MOD_0F73_REG_2 */
+ { Bad_Opcode },
+ { "psrlq", { MS, Ib }, 0 },
+ },
+ {
+ /* MOD_0F73_REG_3 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F73_REG_3) },
+ },
+ {
+ /* MOD_0F73_REG_6 */
+ { Bad_Opcode },
+ { "psllq", { MS, Ib }, 0 },
+ },
+ {
+ /* MOD_0F73_REG_7 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F73_REG_7) },
+ },
+ {
+ /* MOD_0FAE_REG_0 */
+ { "fxsave", { FXSAVE }, 0 },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
+ },
+ {
+ /* MOD_0FAE_REG_1 */
+ { "fxrstor", { FXSAVE }, 0 },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
+ },
+ {
+ /* MOD_0FAE_REG_2 */
+ { "ldmxcsr", { Md }, 0 },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
+ },
+ {
+ /* MOD_0FAE_REG_3 */
+ { "stmxcsr", { Md }, 0 },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
+ },
+ {
+ /* MOD_0FAE_REG_4 */
+ { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
+ },
+ {
+ /* MOD_0FAE_REG_5 */
+ { "xrstor", { FXSAVE }, 0 },
+ { RM_TABLE (RM_0FAE_REG_5) },
+ },
+ {
+ /* MOD_0FAE_REG_6 */
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
+ { RM_TABLE (RM_0FAE_REG_6) },
+ },
+ {
+ /* MOD_0FAE_REG_7 */
+ { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
+ { RM_TABLE (RM_0FAE_REG_7) },
+ },
+ {
+ /* MOD_0FB2 */
+ { "lssS", { Gv, Mp }, 0 },
+ },
+ {
+ /* MOD_0FB4 */
+ { "lfsS", { Gv, Mp }, 0 },
+ },
+ {
+ /* MOD_0FB5 */
+ { "lgsS", { Gv, Mp }, 0 },
+ },
+ {
+ /* MOD_0FC3 */
+ { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
+ },
+ {
+ /* MOD_0FC7_REG_3 */
+ { "xrstors", { FXSAVE }, 0 },
+ },
+ {
+ /* MOD_0FC7_REG_4 */
+ { "xsavec", { FXSAVE }, 0 },
+ },
+ {
+ /* MOD_0FC7_REG_5 */
+ { "xsaves", { FXSAVE }, 0 },
+ },
+ {
+ /* MOD_0FC7_REG_6 */
+ { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
+ },
+ {
+ /* MOD_0FC7_REG_7 */
+ { "vmptrst", { Mq }, 0 },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
+ },
+ {
+ /* MOD_0FD7 */
+ { Bad_Opcode },
+ { "pmovmskb", { Gdq, MS }, 0 },
+ },
+ {
+ /* MOD_0FE7_PREFIX_2 */
+ { "movntdq", { Mx, XM }, 0 },
+ },
+ {
+ /* MOD_0FF0_PREFIX_3 */
+ { "lddqu", { XM, M }, 0 },
+ },
+ {
+ /* MOD_0F382A_PREFIX_2 */
+ { "movntdqa", { XM, Mx }, 0 },
+ },
+ {
+ /* MOD_62_32BIT */
+ { "bound{S|}", { Gv, Ma }, 0 },
+ { EVEX_TABLE (EVEX_0F) },
+ },
+ {
+ /* MOD_C4_32BIT */
+ { "lesS", { Gv, Mp }, 0 },
+ { VEX_C4_TABLE (VEX_0F) },
+ },
+ {
+ /* MOD_C5_32BIT */
+ { "ldsS", { Gv, Mp }, 0 },
+ { VEX_C5_TABLE (VEX_0F) },
+ },
+ {
+ /* MOD_VEX_0F12_PREFIX_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0F13 */
+ { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
+ },
+ {
+ /* MOD_VEX_0F16_PREFIX_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0F17 */
+ { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
+ },
+ {
+ /* MOD_VEX_0F2B */
+ { VEX_W_TABLE (VEX_W_0F2B_M_0) },
+ },
+ {
+ /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "knotw", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "knotq", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "knotb", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "knotd", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "korw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "korq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "korb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_0F50 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F50_M_0) },
+ },
+ {
+ /* MOD_VEX_0F71_REG_2 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
+ },
+ {
+ /* MOD_VEX_0F71_REG_4 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
+ },
+ {
+ /* MOD_VEX_0F71_REG_6 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
+ },
+ {
+ /* MOD_VEX_0F72_REG_2 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
+ },
+ {
+ /* MOD_VEX_0F72_REG_4 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
+ },
+ {
+ /* MOD_VEX_0F72_REG_6 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
+ },
+ {
+ /* MOD_VEX_0F73_REG_2 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
+ },
+ {
+ /* MOD_VEX_0F73_REG_3 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
+ },
+ {
+ /* MOD_VEX_0F73_REG_6 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
+ },
+ {
+ /* MOD_VEX_0F73_REG_7 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+ { "kmovw", { Ew, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+ { "kmovq", { Eq, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+ { "kmovb", { Eb, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+ { "kmovd", { Ed, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kmovw", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kmovb", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovd", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovq", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kmovw", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kmovb", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovd", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovq", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kortestw", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kortestq", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kortestb", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kortestd", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "ktestw", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "ktestq", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "ktestb", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "ktestd", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_0FAE_REG_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0FAE_REG_3 */
+ { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
+ },
+ {
+ /* MOD_VEX_0FD7_PREFIX_2 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
+ },
+ {
+ /* MOD_VEX_0FE7_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0FF0_PREFIX_3 */
+ { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
+ },
+ {
+ /* MOD_VEX_0F381A_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382A_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382C_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382D_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382E_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382F_PREFIX_2 */
+ { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F385A_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F388C_PREFIX_2 */
+ { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
+ },
+ {
+ /* MOD_VEX_0F388E_PREFIX_2 */
+ { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftld", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
+ },
+#define NEED_MOD_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_MOD_TABLE
+};
+
+static const struct dis386 rm_table[][8] = {
+ {
+ /* RM_C6_REG_7 */
+ { "xabort", { Skip_MODRM, Ib }, 0 },
+ },
+ {
+ /* RM_C7_REG_7 */
+ { "xbeginT", { Skip_MODRM, Jv }, 0 },
+ },
+ {
+ /* RM_0F01_REG_0 */
+ { Bad_Opcode },
+ { "vmcall", { Skip_MODRM }, 0 },
+ { "vmlaunch", { Skip_MODRM }, 0 },
+ { "vmresume", { Skip_MODRM }, 0 },
+ { "vmxoff", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0F01_REG_1 */
+ { "monitor", { { OP_Monitor, 0 } }, 0 },
+ { "mwait", { { OP_Mwait, 0 } }, 0 },
+ { "clac", { Skip_MODRM }, 0 },
+ { "stac", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "encls", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0F01_REG_2 */
+ { "xgetbv", { Skip_MODRM }, 0 },
+ { "xsetbv", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vmfunc", { Skip_MODRM }, 0 },
+ { "xend", { Skip_MODRM }, 0 },
+ { "xtest", { Skip_MODRM }, 0 },
+ { "enclu", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0F01_REG_3 */
+ { "vmrun", { Skip_MODRM }, 0 },
+ { "vmmcall", { Skip_MODRM }, 0 },
+ { "vmload", { Skip_MODRM }, 0 },
+ { "vmsave", { Skip_MODRM }, 0 },
+ { "stgi", { Skip_MODRM }, 0 },
+ { "clgi", { Skip_MODRM }, 0 },
+ { "skinit", { Skip_MODRM }, 0 },
+ { "invlpga", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0F01_REG_5 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "rdpkru", { Skip_MODRM }, 0 },
+ { "wrpkru", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0F01_REG_7 */
+ { "swapgs", { Skip_MODRM }, 0 },
+ { "rdtscp", { Skip_MODRM }, 0 },
+ { "monitorx", { { OP_Monitor, 0 } }, 0 },
+ { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
+ { "clzero", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0FAE_REG_5 */
+ { "lfence", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0FAE_REG_6 */
+ { "mfence", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0FAE_REG_7 */
+ { "sfence", { Skip_MODRM }, 0 },
+
+ },
+};
+
+#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
+
+/* We use the high bit to indicate different name for the same
+ prefix. */
+#define REP_PREFIX (0xf3 | 0x100)
+#define XACQUIRE_PREFIX (0xf2 | 0x200)
+#define XRELEASE_PREFIX (0xf3 | 0x400)
+#define BND_PREFIX (0xf2 | 0x400)
+
+static int
+ckprefix (void)
+{
+ int newrex, i, length;
+ rex = 0;
+ rex_ignored = 0;
+ prefixes = 0;
+ used_prefixes = 0;
+ rex_used = 0;
+ last_lock_prefix = -1;
+ last_repz_prefix = -1;
+ last_repnz_prefix = -1;
+ last_data_prefix = -1;
+ last_addr_prefix = -1;
+ last_rex_prefix = -1;
+ last_seg_prefix = -1;
+ fwait_prefix = -1;
+ active_seg_prefix = 0;
+ for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
+ all_prefixes[i] = 0;
+ i = 0;
+ length = 0;
+ /* The maximum instruction length is 15bytes. */
+ while (length < MAX_CODE_LENGTH - 1)
+ {
+ FETCH_DATA (the_info, codep + 1);
+ newrex = 0;
+ switch (*codep)
+ {
+ /* REX prefixes family. */
+ case 0x40:
+ case 0x41:
+ case 0x42:
+ case 0x43:
+ case 0x44:
+ case 0x45:
+ case 0x46:
+ case 0x47:
+ case 0x48:
+ case 0x49:
+ case 0x4a:
+ case 0x4b:
+ case 0x4c:
+ case 0x4d:
+ case 0x4e:
+ case 0x4f:
+ if (address_mode == mode_64bit)
+ newrex = *codep;
+ else
+ return 1;
+ last_rex_prefix = i;
+ break;
+ case 0xf3:
+ prefixes |= PREFIX_REPZ;
+ last_repz_prefix = i;
+ break;
+ case 0xf2:
+ prefixes |= PREFIX_REPNZ;
+ last_repnz_prefix = i;
+ break;
+ case 0xf0:
+ prefixes |= PREFIX_LOCK;
+ last_lock_prefix = i;
+ break;
+ case 0x2e:
+ prefixes |= PREFIX_CS;
+ last_seg_prefix = i;
+ active_seg_prefix = PREFIX_CS;
+ break;
+ case 0x36:
+ prefixes |= PREFIX_SS;
+ last_seg_prefix = i;
+ active_seg_prefix = PREFIX_SS;
+ break;
+ case 0x3e:
+ prefixes |= PREFIX_DS;
+ last_seg_prefix = i;
+ active_seg_prefix = PREFIX_DS;
+ break;
+ case 0x26:
+ prefixes |= PREFIX_ES;
+ last_seg_prefix = i;
+ active_seg_prefix = PREFIX_ES;
+ break;
+ case 0x64:
+ prefixes |= PREFIX_FS;
+ last_seg_prefix = i;
+ active_seg_prefix = PREFIX_FS;
+ break;
+ case 0x65:
+ prefixes |= PREFIX_GS;
+ last_seg_prefix = i;
+ active_seg_prefix = PREFIX_GS;
+ break;
+ case 0x66:
+ prefixes |= PREFIX_DATA;
+ last_data_prefix = i;
+ break;
+ case 0x67:
+ prefixes |= PREFIX_ADDR;
+ last_addr_prefix = i;
+ break;
+ case FWAIT_OPCODE:
+ /* fwait is really an instruction. If there are prefixes
+ before the fwait, they belong to the fwait, *not* to the
+ following instruction. */
+ fwait_prefix = i;
+ if (prefixes || rex)
+ {
+ prefixes |= PREFIX_FWAIT;
+ codep++;
+ /* This ensures that the previous REX prefixes are noticed
+ as unused prefixes, as in the return case below. */
+ rex_used = rex;
+ return 1;
+ }
+ prefixes = PREFIX_FWAIT;
+ break;
+ default:
+ return 1;
+ }
+ /* Rex is ignored when followed by another prefix. */
+ if (rex)
+ {
+ rex_used = rex;
+ return 1;
+ }
+ if (*codep != FWAIT_OPCODE)
+ all_prefixes[i++] = *codep;
+ rex = newrex;
+ codep++;
+ length++;
+ }
+ return 0;
+}
+
+/* Return the name of the prefix byte PREF, or NULL if PREF is not a
+ prefix byte. */
+
+static const char *
+prefix_name (int pref, int sizeflag)
+{
+ static const char *rexes [16] =
+ {
+ "rex", /* 0x40 */
+ "rex.B", /* 0x41 */
+ "rex.X", /* 0x42 */
+ "rex.XB", /* 0x43 */
+ "rex.R", /* 0x44 */
+ "rex.RB", /* 0x45 */
+ "rex.RX", /* 0x46 */
+ "rex.RXB", /* 0x47 */
+ "rex.W", /* 0x48 */
+ "rex.WB", /* 0x49 */
+ "rex.WX", /* 0x4a */
+ "rex.WXB", /* 0x4b */
+ "rex.WR", /* 0x4c */
+ "rex.WRB", /* 0x4d */
+ "rex.WRX", /* 0x4e */
+ "rex.WRXB", /* 0x4f */
+ };
+
+ switch (pref)
+ {
+ /* REX prefixes family. */
+ case 0x40:
+ case 0x41:
+ case 0x42:
+ case 0x43:
+ case 0x44:
+ case 0x45:
+ case 0x46:
+ case 0x47:
+ case 0x48:
+ case 0x49:
+ case 0x4a:
+ case 0x4b:
+ case 0x4c:
+ case 0x4d:
+ case 0x4e:
+ case 0x4f:
+ return rexes [pref - 0x40];
+ case 0xf3:
+ return "repz";
+ case 0xf2:
+ return "repnz";
+ case 0xf0:
+ return "lock";
+ case 0x2e:
+ return "cs";
+ case 0x36:
+ return "ss";
+ case 0x3e:
+ return "ds";
+ case 0x26:
+ return "es";
+ case 0x64:
+ return "fs";
+ case 0x65:
+ return "gs";
+ case 0x66:
+ return (sizeflag & DFLAG) ? "data16" : "data32";
+ case 0x67:
+ if (address_mode == mode_64bit)
+ return (sizeflag & AFLAG) ? "addr32" : "addr64";
+ else
+ return (sizeflag & AFLAG) ? "addr16" : "addr32";
+ case FWAIT_OPCODE:
+ return "fwait";
+ case REP_PREFIX:
+ return "rep";
+ case XACQUIRE_PREFIX:
+ return "xacquire";
+ case XRELEASE_PREFIX:
+ return "xrelease";
+ case BND_PREFIX:
+ return "bnd";
+ default:
+ return NULL;
+ }
+}
+
+static char op_out[MAX_OPERANDS][100];
+static int op_ad, op_index[MAX_OPERANDS];
+static int two_source_ops;
+static bfd_vma op_address[MAX_OPERANDS];
+static bfd_vma op_riprel[MAX_OPERANDS];
+static bfd_vma start_pc;
+
+/*
+ * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
+ * (see topic "Redundant prefixes" in the "Differences from 8086"
+ * section of the "Virtual 8086 Mode" chapter.)
+ * 'pc' should be the address of this instruction, it will
+ * be used to print the target address if this is a relative jump or call
+ * The function returns the length of this instruction in bytes.
+ */
+
+static char intel_syntax;
+static char intel_mnemonic = !SYSV386_COMPAT;
+static char open_char;
+static char close_char;
+static char separator_char;
+static char scale_char;
+
+enum x86_64_isa
+{
+ amd64 = 0,
+ intel64
+};
+
+static enum x86_64_isa isa64;
+
+/* Here for backwards compatibility. When gdb stops using
+ print_insn_i386_att and print_insn_i386_intel these functions can
+ disappear, and print_insn_i386 be merged into print_insn. */
+int
+print_insn_i386_att (bfd_vma pc, disassemble_info *info)
+{
+ intel_syntax = 0;
+
+ return print_insn (pc, info);
+}
+
+int
+print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
+{
+ intel_syntax = 1;
+
+ return print_insn (pc, info);
+}
+
+int
+print_insn_i386 (bfd_vma pc, disassemble_info *info)
+{
+ intel_syntax = -1;
+
+ return print_insn (pc, info);
+}
+
+void
+print_i386_disassembler_options (FILE *stream)
+{
+ fprintf (stream, _("\n\
+The following i386/x86-64 specific disassembler options are supported for use\n\
+with the -M switch (multiple options should be separated by commas):\n"));
+
+ fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
+ fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
+ fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
+ fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
+ fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
+ fprintf (stream, _(" att-mnemonic\n"
+ " Display instruction in AT&T mnemonic\n"));
+ fprintf (stream, _(" intel-mnemonic\n"
+ " Display instruction in Intel mnemonic\n"));
+ fprintf (stream, _(" addr64 Assume 64bit address size\n"));
+ fprintf (stream, _(" addr32 Assume 32bit address size\n"));
+ fprintf (stream, _(" addr16 Assume 16bit address size\n"));
+ fprintf (stream, _(" data32 Assume 32bit data size\n"));
+ fprintf (stream, _(" data16 Assume 16bit data size\n"));
+ fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
+ fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
+ fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
+}
+
+/* Bad opcode. */
+static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
+
+/* Get a pointer to struct dis386 with a valid name. */
+
+static const struct dis386 *
+get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
+{
+ int vindex, vex_table_index;
+
+ if (dp->name != NULL)
+ return dp;
+
+ switch (dp->op[0].bytemode)
+ {
+ case USE_REG_TABLE:
+ dp = ®_table[dp->op[1].bytemode][modrm.reg];
+ break;
+
+ case USE_MOD_TABLE:
+ vindex = modrm.mod == 0x3 ? 1 : 0;
+ dp = &mod_table[dp->op[1].bytemode][vindex];
+ break;
+
+ case USE_RM_TABLE:
+ dp = &rm_table[dp->op[1].bytemode][modrm.rm];
+ break;
+
+ case USE_PREFIX_TABLE:
+ if (need_vex)
+ {
+ /* The prefix in VEX is implicit. */
+ switch (vex.prefix)
+ {
+ case 0:
+ vindex = 0;
+ break;
+ case REPE_PREFIX_OPCODE:
+ vindex = 1;
+ break;
+ case DATA_PREFIX_OPCODE:
+ vindex = 2;
+ break;
+ case REPNE_PREFIX_OPCODE:
+ vindex = 3;
+ break;
+ default:
+ abort ();
+ break;
+ }
+ }
+ else
+ {
+ int last_prefix = -1;
+ int prefix = 0;
+ vindex = 0;
+ /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
+ When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
+ last one wins. */
+ if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
+ {
+ if (last_repz_prefix > last_repnz_prefix)
+ {
+ vindex = 1;
+ prefix = PREFIX_REPZ;
+ last_prefix = last_repz_prefix;
+ }
+ else
+ {
+ vindex = 3;
+ prefix = PREFIX_REPNZ;
+ last_prefix = last_repnz_prefix;
+ }
+
+ /* Check if prefix should be ignored. */
+ if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
+ & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
+ & prefix) != 0)
+ vindex = 0;
+ }
+
+ if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
+ {
+ vindex = 2;
+ prefix = PREFIX_DATA;
+ last_prefix = last_data_prefix;
+ }
+
+ if (vindex != 0)
+ {
+ used_prefixes |= prefix;
+ all_prefixes[last_prefix] = 0;
+ }
+ }
+ dp = &prefix_table[dp->op[1].bytemode][vindex];
+ break;
+
+ case USE_X86_64_TABLE:
+ vindex = address_mode == mode_64bit ? 1 : 0;
+ dp = &x86_64_table[dp->op[1].bytemode][vindex];
+ break;
+
+ case USE_3BYTE_TABLE:
+ FETCH_DATA (info, codep + 2);
+ vindex = *codep++;
+ dp = &three_byte_table[dp->op[1].bytemode][vindex];
+ end_codep = codep;
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ break;
+
+ case USE_VEX_LEN_TABLE:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ vindex = 0;
+ break;
+ case 256:
+ vindex = 1;
+ break;
+ default:
+ abort ();
+ break;
+ }
+
+ dp = &vex_len_table[dp->op[1].bytemode][vindex];
+ break;
+
+ case USE_XOP_8F_TABLE:
+ FETCH_DATA (info, codep + 3);
+ /* All bits in the REX prefix are ignored. */
+ rex_ignored = rex;
+ rex = ~(*codep >> 5) & 0x7;
+
+ /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
+ switch ((*codep & 0x1f))
+ {
+ default:
+ dp = &bad_opcode;
+ return dp;
+ case 0x8:
+ vex_table_index = XOP_08;
+ break;
+ case 0x9:
+ vex_table_index = XOP_09;
+ break;
+ case 0xa:
+ vex_table_index = XOP_0A;
+ break;
+ }
+ codep++;
+ vex.w = *codep & 0x80;
+ if (vex.w && address_mode == mode_64bit)
+ rex |= REX_W;
+
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
+ if (address_mode != mode_64bit
+ && vex.register_specifier > 0x7)
+ {
+ dp = &bad_opcode;
+ return dp;
+ }
+
+ vex.length = (*codep & 0x4) ? 256 : 128;
+ switch ((*codep & 0x3))
+ {
+ case 0:
+ vex.prefix = 0;
+ break;
+ case 1:
+ vex.prefix = DATA_PREFIX_OPCODE;
+ break;
+ case 2:
+ vex.prefix = REPE_PREFIX_OPCODE;
+ break;
+ case 3:
+ vex.prefix = REPNE_PREFIX_OPCODE;
+ break;
+ }
+ need_vex = 1;
+ need_vex_reg = 1;
+ codep++;
+ vindex = *codep++;
+ dp = &xop_table[vex_table_index][vindex];
+
+ end_codep = codep;
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ break;
+
+ case USE_VEX_C4_TABLE:
+ /* VEX prefix. */
+ FETCH_DATA (info, codep + 3);
+ /* All bits in the REX prefix are ignored. */
+ rex_ignored = rex;
+ rex = ~(*codep >> 5) & 0x7;
+ switch ((*codep & 0x1f))
+ {
+ default:
+ dp = &bad_opcode;
+ return dp;
+ case 0x1:
+ vex_table_index = VEX_0F;
+ break;
+ case 0x2:
+ vex_table_index = VEX_0F38;
+ break;
+ case 0x3:
+ vex_table_index = VEX_0F3A;
+ break;
+ }
+ codep++;
+ vex.w = *codep & 0x80;
+ if (address_mode == mode_64bit)
+ {
+ if (vex.w)
+ rex |= REX_W;
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
+ }
+ else
+ {
+ /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
+ is ignored, other REX bits are 0 and the highest bit in
+ VEX.vvvv is also ignored. */
+ rex = 0;
+ vex.register_specifier = (~(*codep >> 3)) & 0x7;
+ }
+ vex.length = (*codep & 0x4) ? 256 : 128;
+ switch ((*codep & 0x3))
+ {
+ case 0:
+ vex.prefix = 0;
+ break;
+ case 1:
+ vex.prefix = DATA_PREFIX_OPCODE;
+ break;
+ case 2:
+ vex.prefix = REPE_PREFIX_OPCODE;
+ break;
+ case 3:
+ vex.prefix = REPNE_PREFIX_OPCODE;
+ break;
+ }
+ need_vex = 1;
+ need_vex_reg = 1;
+ codep++;
+ vindex = *codep++;
+ dp = &vex_table[vex_table_index][vindex];
+ end_codep = codep;
+ /* There is no MODRM byte for VEX [82|77]. */
+ if (vindex != 0x77 && vindex != 0x82)
+ {
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ }
+ break;
+
+ case USE_VEX_C5_TABLE:
+ /* VEX prefix. */
+ FETCH_DATA (info, codep + 2);
+ /* All bits in the REX prefix are ignored. */
+ rex_ignored = rex;
+ rex = (*codep & 0x80) ? 0 : REX_R;
+
+ /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
+ VEX.vvvv is 1. */
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
+ vex.w = 0;
+ vex.length = (*codep & 0x4) ? 256 : 128;
+ switch ((*codep & 0x3))
+ {
+ case 0:
+ vex.prefix = 0;
+ break;
+ case 1:
+ vex.prefix = DATA_PREFIX_OPCODE;
+ break;
+ case 2:
+ vex.prefix = REPE_PREFIX_OPCODE;
+ break;
+ case 3:
+ vex.prefix = REPNE_PREFIX_OPCODE;
+ break;
+ }
+ need_vex = 1;
+ need_vex_reg = 1;
+ codep++;
+ vindex = *codep++;
+ dp = &vex_table[dp->op[1].bytemode][vindex];
+ end_codep = codep;
+ /* There is no MODRM byte for VEX [82|77]. */
+ if (vindex != 0x77 && vindex != 0x82)
+ {
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ }
+ break;
+
+ case USE_VEX_W_TABLE:
+ if (!need_vex)
+ abort ();
+
+ dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
+ break;
+
+ case USE_EVEX_TABLE:
+ two_source_ops = 0;
+ /* EVEX prefix. */
+ vex.evex = 1;
+ FETCH_DATA (info, codep + 4);
+ /* All bits in the REX prefix are ignored. */
+ rex_ignored = rex;
+ /* The first byte after 0x62. */
+ rex = ~(*codep >> 5) & 0x7;
+ vex.r = *codep & 0x10;
+ switch ((*codep & 0xf))
+ {
+ default:
+ return &bad_opcode;
+ case 0x1:
+ vex_table_index = EVEX_0F;
+ break;
+ case 0x2:
+ vex_table_index = EVEX_0F38;
+ break;
+ case 0x3:
+ vex_table_index = EVEX_0F3A;
+ break;
+ }
+
+ /* The second byte after 0x62. */
+ codep++;
+ vex.w = *codep & 0x80;
+ if (vex.w && address_mode == mode_64bit)
+ rex |= REX_W;
+
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
+ if (address_mode != mode_64bit)
+ {
+ /* In 16/32-bit mode silently ignore following bits. */
+ rex &= ~REX_B;
+ vex.r = 1;
+ vex.v = 1;
+ vex.register_specifier &= 0x7;
+ }
+
+ /* The U bit. */
+ if (!(*codep & 0x4))
+ return &bad_opcode;
+
+ switch ((*codep & 0x3))
+ {
+ case 0:
+ vex.prefix = 0;
+ break;
+ case 1:
+ vex.prefix = DATA_PREFIX_OPCODE;
+ break;
+ case 2:
+ vex.prefix = REPE_PREFIX_OPCODE;
+ break;
+ case 3:
+ vex.prefix = REPNE_PREFIX_OPCODE;
+ break;
+ }
+
+ /* The third byte after 0x62. */
+ codep++;
+
+ /* Remember the static rounding bits. */
+ vex.ll = (*codep >> 5) & 3;
+ vex.b = (*codep & 0x10) != 0;
+
+ vex.v = *codep & 0x8;
+ vex.mask_register_specifier = *codep & 0x7;
+ vex.zeroing = *codep & 0x80;
+
+ need_vex = 1;
+ need_vex_reg = 1;
+ codep++;
+ vindex = *codep++;
+ dp = &evex_table[vex_table_index][vindex];
+ end_codep = codep;
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+
+ /* Set vector length. */
+ if (modrm.mod == 3 && vex.b)
+ vex.length = 512;
+ else
+ {
+ switch (vex.ll)
+ {
+ case 0x0:
+ vex.length = 128;
+ break;
+ case 0x1:
+ vex.length = 256;
+ break;
+ case 0x2:
+ vex.length = 512;
+ break;
+ default:
+ return &bad_opcode;
+ }
+ }
+ break;
+
+ case 0:
+ dp = &bad_opcode;
+ break;
+
+ default:
+ abort ();
+ }
+
+ if (dp->name != NULL)
+ return dp;
+ else
+ return get_valid_dis386 (dp, info);
+}
+
+static void
+get_sib (disassemble_info *info, int sizeflag)
+{
+ /* If modrm.mod == 3, operand must be register. */
+ if (need_modrm
+ && ((sizeflag & AFLAG) || address_mode == mode_64bit)
+ && modrm.mod != 3
+ && modrm.rm == 4)
+ {
+ FETCH_DATA (info, codep + 2);
+ sib.index = (codep [1] >> 3) & 7;
+ sib.scale = (codep [1] >> 6) & 3;
+ sib.base = codep [1] & 7;
+ }
+}
+
+static int
+print_insn (bfd_vma pc, disassemble_info *info)
+{
+ const struct dis386 *dp;
+ int i;
+ char *op_txt[MAX_OPERANDS];
+ int needcomma;
+ int sizeflag, orig_sizeflag;
+ const char *p;
+ struct dis_private priv;
+ int prefix_length;
+
+ priv.orig_sizeflag = AFLAG | DFLAG;
+ if ((info->mach & bfd_mach_i386_i386) != 0)
+ address_mode = mode_32bit;
+ else if (info->mach == bfd_mach_i386_i8086)
+ {
+ address_mode = mode_16bit;
+ priv.orig_sizeflag = 0;
+ }
+ else
+ address_mode = mode_64bit;
+
+ if (intel_syntax == (char) -1)
+ intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
+
+ for (p = info->disassembler_options; p != NULL; )
+ {
+ if (CONST_STRNEQ (p, "amd64"))
+ isa64 = amd64;
+ else if (CONST_STRNEQ (p, "intel64"))
+ isa64 = intel64;
+ else if (CONST_STRNEQ (p, "x86-64"))
+ {
+ address_mode = mode_64bit;
+ priv.orig_sizeflag = AFLAG | DFLAG;
+ }
+ else if (CONST_STRNEQ (p, "i386"))
+ {
+ address_mode = mode_32bit;
+ priv.orig_sizeflag = AFLAG | DFLAG;
+ }
+ else if (CONST_STRNEQ (p, "i8086"))
+ {
+ address_mode = mode_16bit;
+ priv.orig_sizeflag = 0;
+ }
+ else if (CONST_STRNEQ (p, "intel"))
+ {
+ intel_syntax = 1;
+ if (CONST_STRNEQ (p + 5, "-mnemonic"))
+ intel_mnemonic = 1;
+ }
+ else if (CONST_STRNEQ (p, "att"))
+ {
+ intel_syntax = 0;
+ if (CONST_STRNEQ (p + 3, "-mnemonic"))
+ intel_mnemonic = 0;
+ }
+ else if (CONST_STRNEQ (p, "addr"))
+ {
+ if (address_mode == mode_64bit)
+ {
+ if (p[4] == '3' && p[5] == '2')
+ priv.orig_sizeflag &= ~AFLAG;
+ else if (p[4] == '6' && p[5] == '4')
+ priv.orig_sizeflag |= AFLAG;
+ }
+ else
+ {
+ if (p[4] == '1' && p[5] == '6')
+ priv.orig_sizeflag &= ~AFLAG;
+ else if (p[4] == '3' && p[5] == '2')
+ priv.orig_sizeflag |= AFLAG;
+ }
+ }
+ else if (CONST_STRNEQ (p, "data"))
+ {
+ if (p[4] == '1' && p[5] == '6')
+ priv.orig_sizeflag &= ~DFLAG;
+ else if (p[4] == '3' && p[5] == '2')
+ priv.orig_sizeflag |= DFLAG;
+ }
+ else if (CONST_STRNEQ (p, "suffix"))
+ priv.orig_sizeflag |= SUFFIX_ALWAYS;
+
+ p = strchr (p, ',');
+ if (p != NULL)
+ p++;
+ }
+
+ if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
+ {
+ (*info->fprintf_func) (info->stream,
+ _("64-bit address is disabled"));
+ return -1;
+ }
+
+ if (intel_syntax)
+ {
+ names64 = intel_names64;
+ names32 = intel_names32;
+ names16 = intel_names16;
+ names8 = intel_names8;
+ names8rex = intel_names8rex;
+ names_seg = intel_names_seg;
+ names_mm = intel_names_mm;
+ names_bnd = intel_names_bnd;
+ names_xmm = intel_names_xmm;
+ names_ymm = intel_names_ymm;
+ names_zmm = intel_names_zmm;
+ index64 = intel_index64;
+ index32 = intel_index32;
+ names_mask = intel_names_mask;
+ index16 = intel_index16;
+ open_char = '[';
+ close_char = ']';
+ separator_char = '+';
+ scale_char = '*';
+ }
+ else
+ {
+ names64 = att_names64;
+ names32 = att_names32;
+ names16 = att_names16;
+ names8 = att_names8;
+ names8rex = att_names8rex;
+ names_seg = att_names_seg;
+ names_mm = att_names_mm;
+ names_bnd = att_names_bnd;
+ names_xmm = att_names_xmm;
+ names_ymm = att_names_ymm;
+ names_zmm = att_names_zmm;
+ index64 = att_index64;
+ index32 = att_index32;
+ names_mask = att_names_mask;
+ index16 = att_index16;
+ open_char = '(';
+ close_char = ')';
+ separator_char = ',';
+ scale_char = ',';
+ }
+
+ /* The output looks better if we put 7 bytes on a line, since that
+ puts most long word instructions on a single line. Use 8 bytes
+ for Intel L1OM. */
+ if ((info->mach & bfd_mach_l1om) != 0)
+ info->bytes_per_line = 8;
+ else
+ info->bytes_per_line = 7;
+
+ info->private_data = &priv;
+ priv.max_fetched = priv.the_buffer;
+ priv.insn_start = pc;
+
+ obuf[0] = 0;
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ {
+ op_out[i][0] = 0;
+ op_index[i] = -1;
+ }
+
+ the_info = info;
+ start_pc = pc;
+ start_codep = priv.the_buffer;
+ codep = priv.the_buffer;
+
+ if (OPCODES_SIGSETJMP (priv.bailout) != 0)
+ {
+ const char *name;
+
+ /* Getting here means we tried for data but didn't get it. That
+ means we have an incomplete instruction of some sort. Just
+ print the first byte as a prefix or a .byte pseudo-op. */
+ if (codep > priv.the_buffer)
+ {
+ name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
+ if (name != NULL)
+ (*info->fprintf_func) (info->stream, "%s", name);
+ else
+ {
+ /* Just print the first byte as a .byte instruction. */
+ (*info->fprintf_func) (info->stream, ".byte 0x%x",
+ (unsigned int) priv.the_buffer[0]);
+ }
+
+ return 1;
+ }
+
+ return -1;
+ }
+
+ obufp = obuf;
+ sizeflag = priv.orig_sizeflag;
+
+ if (!ckprefix () || rex_used)
+ {
+ /* Too many prefixes or unused REX prefixes. */
+ for (i = 0;
+ i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
+ i++)
+ (*info->fprintf_func) (info->stream, "%s%s",
+ i == 0 ? "" : " ",
+ prefix_name (all_prefixes[i], sizeflag));
+ return i;
+ }
+
+ insn_codep = codep;
+
+ FETCH_DATA (info, codep + 1);
+ two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
+
+ if (((prefixes & PREFIX_FWAIT)
+ && ((*codep < 0xd8) || (*codep > 0xdf))))
+ {
+ /* Handle prefixes before fwait. */
+ for (i = 0; i < fwait_prefix && all_prefixes[i];
+ i++)
+ (*info->fprintf_func) (info->stream, "%s ",
+ prefix_name (all_prefixes[i], sizeflag));
+ (*info->fprintf_func) (info->stream, "fwait");
+ return i + 1;
+ }
+
+ if (*codep == 0x0f)
+ {
+ unsigned char threebyte;
+
+ codep++;
+ FETCH_DATA (info, codep + 1);
+ threebyte = *codep;
+ dp = &dis386_twobyte[threebyte];
+ need_modrm = twobyte_has_modrm[*codep];
+ codep++;
+ }
+ else
+ {
+ dp = &dis386[*codep];
+ need_modrm = onebyte_has_modrm[*codep];
+ codep++;
+ }
+
+ /* Save sizeflag for printing the extra prefixes later before updating
+ it for mnemonic and operand processing. The prefix names depend
+ only on the address mode. */
+ orig_sizeflag = sizeflag;
+ if (prefixes & PREFIX_ADDR)
+ sizeflag ^= AFLAG;
+ if ((prefixes & PREFIX_DATA))
+ sizeflag ^= DFLAG;
+
+ end_codep = codep;
+ if (need_modrm)
+ {
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+ }
+
+ need_vex = 0;
+ need_vex_reg = 0;
+ vex_w_done = 0;
+ vex.evex = 0;
+
+ if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
+ {
+ get_sib (info, sizeflag);
+ dofloat (sizeflag);
+ }
+ else
+ {
+ dp = get_valid_dis386 (dp, info);
+ if (dp != NULL && putop (dp->name, sizeflag) == 0)
+ {
+ get_sib (info, sizeflag);
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ {
+ obufp = op_out[i];
+ op_ad = MAX_OPERANDS - 1 - i;
+ if (dp->op[i].rtn)
+ (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
+ /* For EVEX instruction after the last operand masking
+ should be printed. */
+ if (i == 0 && vex.evex)
+ {
+ /* Don't print {%k0}. */
+ if (vex.mask_register_specifier)
+ {
+ oappend ("{");
+ oappend (names_mask[vex.mask_register_specifier]);
+ oappend ("}");
+ }
+ if (vex.zeroing)
+ oappend ("{z}");
+ }
+ }
+ }
+ }
+
+ /* Check if the REX prefix is used. */
+ if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
+ all_prefixes[last_rex_prefix] = 0;
+
+ /* Check if the SEG prefix is used. */
+ if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
+ | PREFIX_FS | PREFIX_GS)) != 0
+ && (used_prefixes & active_seg_prefix) != 0)
+ all_prefixes[last_seg_prefix] = 0;
+
+ /* Check if the ADDR prefix is used. */
+ if ((prefixes & PREFIX_ADDR) != 0
+ && (used_prefixes & PREFIX_ADDR) != 0)
+ all_prefixes[last_addr_prefix] = 0;
+
+ /* Check if the DATA prefix is used. */
+ if ((prefixes & PREFIX_DATA) != 0
+ && (used_prefixes & PREFIX_DATA) != 0)
+ all_prefixes[last_data_prefix] = 0;
+
+ /* Print the extra prefixes. */
+ prefix_length = 0;
+ for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
+ if (all_prefixes[i])
+ {
+ const char *name;
+ name = prefix_name (all_prefixes[i], orig_sizeflag);
+ if (name == NULL)
+ abort ();
+ prefix_length += strlen (name) + 1;
+ (*info->fprintf_func) (info->stream, "%s ", name);
+ }
+
+ /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
+ unused, opcode is invalid. Since the PREFIX_DATA prefix may be
+ used by putop and MMX/SSE operand and may be overriden by the
+ PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
+ separately. */
+ if (dp->prefix_requirement == PREFIX_OPCODE
+ && dp != &bad_opcode
+ && (((prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
+ && (used_prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
+ || ((((prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
+ == PREFIX_DATA)
+ && (used_prefixes & PREFIX_DATA) == 0))))
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
+
+ /* Check maximum code length. */
+ if ((codep - start_codep) > MAX_CODE_LENGTH)
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return MAX_CODE_LENGTH;
+ }
+
+ obufp = mnemonicendp;
+ for (i = strlen (obuf) + prefix_length; i < 6; i++)
+ oappend (" ");
+ oappend (" ");
+ (*info->fprintf_func) (info->stream, "%s", obuf);
+
+ /* The enter and bound instructions are printed with operands in the same
+ order as the intel book; everything else is printed in reverse order. */
+ if (intel_syntax || two_source_ops)
+ {
+ bfd_vma riprel;
+
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ op_txt[i] = op_out[i];
+
+ if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
+ && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
+ {
+ op_txt[2] = op_out[3];
+ op_txt[3] = op_out[2];
+ }
+
+ for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
+ {
+ op_ad = op_index[i];
+ op_index[i] = op_index[MAX_OPERANDS - 1 - i];
+ op_index[MAX_OPERANDS - 1 - i] = op_ad;
+ riprel = op_riprel[i];
+ op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
+ op_riprel[MAX_OPERANDS - 1 - i] = riprel;
+ }
+ }
+ else
+ {
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
+ }
+
+ needcomma = 0;
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ if (*op_txt[i])
+ {
+ if (needcomma)
+ (*info->fprintf_func) (info->stream, ",");
+ if (op_index[i] != -1 && !op_riprel[i])
+ (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
+ else
+ (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
+ needcomma = 1;
+ }
+
+ for (i = 0; i < MAX_OPERANDS; i++)
+ if (op_index[i] != -1 && op_riprel[i])
+ {
+ (*info->fprintf_func) (info->stream, " # ");
+ (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
+ + op_address[op_index[i]]), info);
+ break;
+ }
+ return codep - priv.the_buffer;
+}
+
+static const char *float_mem[] = {
+ /* d8 */
+ "fadd{s|}",
+ "fmul{s|}",
+ "fcom{s|}",
+ "fcomp{s|}",
+ "fsub{s|}",
+ "fsubr{s|}",
+ "fdiv{s|}",
+ "fdivr{s|}",
+ /* d9 */
+ "fld{s|}",
+ "(bad)",
+ "fst{s|}",
+ "fstp{s|}",
+ "fldenvIC",
+ "fldcw",
+ "fNstenvIC",
+ "fNstcw",
+ /* da */
+ "fiadd{l|}",
+ "fimul{l|}",
+ "ficom{l|}",
+ "ficomp{l|}",
+ "fisub{l|}",
+ "fisubr{l|}",
+ "fidiv{l|}",
+ "fidivr{l|}",
+ /* db */
+ "fild{l|}",
+ "fisttp{l|}",
+ "fist{l|}",
+ "fistp{l|}",
+ "(bad)",
+ "fld{t||t|}",
+ "(bad)",
+ "fstp{t||t|}",
+ /* dc */
+ "fadd{l|}",
+ "fmul{l|}",
+ "fcom{l|}",
+ "fcomp{l|}",
+ "fsub{l|}",
+ "fsubr{l|}",
+ "fdiv{l|}",
+ "fdivr{l|}",
+ /* dd */
+ "fld{l|}",
+ "fisttp{ll|}",
+ "fst{l||}",
+ "fstp{l|}",
+ "frstorIC",
+ "(bad)",
+ "fNsaveIC",
+ "fNstsw",
+ /* de */
+ "fiadd",
+ "fimul",
+ "ficom",
+ "ficomp",
+ "fisub",
+ "fisubr",
+ "fidiv",
+ "fidivr",
+ /* df */
+ "fild",
+ "fisttp",
+ "fist",
+ "fistp",
+ "fbld",
+ "fild{ll|}",
+ "fbstp",
+ "fistp{ll|}",
+};
+
+static const unsigned char float_mem_mode[] = {
+ /* d8 */
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ /* d9 */
+ d_mode,
+ 0,
+ d_mode,
+ d_mode,
+ 0,
+ w_mode,
+ 0,
+ w_mode,
+ /* da */
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ /* db */
+ d_mode,
+ d_mode,
+ d_mode,
+ d_mode,
+ 0,
+ t_mode,
+ 0,
+ t_mode,
+ /* dc */
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ /* dd */
+ q_mode,
+ q_mode,
+ q_mode,
+ q_mode,
+ 0,
+ 0,
+ 0,
+ w_mode,
+ /* de */
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ /* df */
+ w_mode,
+ w_mode,
+ w_mode,
+ w_mode,
+ t_mode,
+ q_mode,
+ t_mode,
+ q_mode
+};
+
+#define ST { OP_ST, 0 }
+#define STi { OP_STi, 0 }
+
+#define FGRPd9_2 NULL, { { NULL, 1 } }, 0
+#define FGRPd9_4 NULL, { { NULL, 2 } }, 0
+#define FGRPd9_5 NULL, { { NULL, 3 } }, 0
+#define FGRPd9_6 NULL, { { NULL, 4 } }, 0
+#define FGRPd9_7 NULL, { { NULL, 5 } }, 0
+#define FGRPda_5 NULL, { { NULL, 6 } }, 0
+#define FGRPdb_4 NULL, { { NULL, 7 } }, 0
+#define FGRPde_3 NULL, { { NULL, 8 } }, 0
+#define FGRPdf_4 NULL, { { NULL, 9 } }, 0
+
+static const struct dis386 float_reg[][8] = {
+ /* d8 */
+ {
+ { "fadd", { ST, STi }, 0 },
+ { "fmul", { ST, STi }, 0 },
+ { "fcom", { STi }, 0 },
+ { "fcomp", { STi }, 0 },
+ { "fsub", { ST, STi }, 0 },
+ { "fsubr", { ST, STi }, 0 },
+ { "fdiv", { ST, STi }, 0 },
+ { "fdivr", { ST, STi }, 0 },
+ },
+ /* d9 */
+ {
+ { "fld", { STi }, 0 },
+ { "fxch", { STi }, 0 },
+ { FGRPd9_2 },
+ { Bad_Opcode },
+ { FGRPd9_4 },
+ { FGRPd9_5 },
+ { FGRPd9_6 },
+ { FGRPd9_7 },
+ },
+ /* da */
+ {
+ { "fcmovb", { ST, STi }, 0 },
+ { "fcmove", { ST, STi }, 0 },
+ { "fcmovbe",{ ST, STi }, 0 },
+ { "fcmovu", { ST, STi }, 0 },
+ { Bad_Opcode },
+ { FGRPda_5 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* db */
+ {
+ { "fcmovnb",{ ST, STi }, 0 },
+ { "fcmovne",{ ST, STi }, 0 },
+ { "fcmovnbe",{ ST, STi }, 0 },
+ { "fcmovnu",{ ST, STi }, 0 },
+ { FGRPdb_4 },
+ { "fucomi", { ST, STi }, 0 },
+ { "fcomi", { ST, STi }, 0 },
+ { Bad_Opcode },
+ },
+ /* dc */
+ {
+ { "fadd", { STi, ST }, 0 },
+ { "fmul", { STi, ST }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "fsub!M", { STi, ST }, 0 },
+ { "fsubM", { STi, ST }, 0 },
+ { "fdiv!M", { STi, ST }, 0 },
+ { "fdivM", { STi, ST }, 0 },
+ },
+ /* dd */
+ {
+ { "ffree", { STi }, 0 },
+ { Bad_Opcode },
+ { "fst", { STi }, 0 },
+ { "fstp", { STi }, 0 },
+ { "fucom", { STi }, 0 },
+ { "fucomp", { STi }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+ /* de */
+ {
+ { "faddp", { STi, ST }, 0 },
+ { "fmulp", { STi, ST }, 0 },
+ { Bad_Opcode },
+ { FGRPde_3 },
+ { "fsub!Mp", { STi, ST }, 0 },
+ { "fsubMp", { STi, ST }, 0 },
+ { "fdiv!Mp", { STi, ST }, 0 },
+ { "fdivMp", { STi, ST }, 0 },
+ },
+ /* df */
+ {
+ { "ffreep", { STi }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { FGRPdf_4 },
+ { "fucomip", { ST, STi }, 0 },
+ { "fcomip", { ST, STi }, 0 },
+ { Bad_Opcode },
+ },
+};
+
+static char *fgrps[][8] = {
+ /* Bad opcode 0 */
+ {
+ "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+
+ /* d9_2 1 */
+ {
+ "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+
+ /* d9_4 2 */
+ {
+ "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
+ },
+
+ /* d9_5 3 */
+ {
+ "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
+ },
+
+ /* d9_6 4 */
+ {
+ "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
+ },
+
+ /* d9_7 5 */
+ {
+ "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
+ },
+
+ /* da_5 6 */
+ {
+ "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+
+ /* db_4 7 */
+ {
+ "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
+ "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
+ },
+
+ /* de_3 8 */
+ {
+ "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+
+ /* df_4 9 */
+ {
+ "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
+ },
+};
+
+static void
+swap_operand (void)
+{
+ mnemonicendp[0] = '.';
+ mnemonicendp[1] = 's';
+ mnemonicendp += 2;
+}
+
+static void
+OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+}
+
+static void
+dofloat (int sizeflag)
+{
+ const struct dis386 *dp;
+ unsigned char floatop;
+
+ floatop = codep[-1];
+
+ if (modrm.mod != 3)
+ {
+ int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
+
+ putop (float_mem[fp_indx], sizeflag);
+ obufp = op_out[0];
+ op_ad = 2;
+ OP_E (float_mem_mode[fp_indx], sizeflag);
+ return;
+ }
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+
+ dp = &float_reg[floatop - 0xd8][modrm.reg];
+ if (dp->name == NULL)
+ {
+ putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
+
+ /* Instruction fnstsw is only one with strange arg. */
+ if (floatop == 0xdf && codep[-1] == 0xe0)
+ strcpy (op_out[0], names16[0]);
+ }
+ else
+ {
+ putop (dp->name, sizeflag);
+
+ obufp = op_out[0];
+ op_ad = 2;
+ if (dp->op[0].rtn)
+ (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
+
+ obufp = op_out[1];
+ op_ad = 1;
+ if (dp->op[1].rtn)
+ (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
+ }
+}
+
+/* Like oappend (below), but S is a string starting with '%'.
+ In Intel syntax, the '%' is elided. */
+static void
+oappend_maybe_intel (const char *s)
+{
+ oappend (s + intel_syntax);
+}
+
+static void
+OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ oappend_maybe_intel ("%st");
+}
+
+static void
+OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ sprintf (scratchbuf, "%%st(%d)", modrm.rm);
+ oappend_maybe_intel (scratchbuf);
+}
+
+/* Capital letters in template are macros. */
+static int
+putop (const char *in_template, int sizeflag)
+{
+ const char *p;
+ int alt = 0;
+ int cond = 1;
+ unsigned int l = 0, len = 1;
+ char last[4];
+
+#define SAVE_LAST(c) \
+ if (l < len && l < sizeof (last)) \
+ last[l++] = c; \
+ else \
+ abort ();
+
+ for (p = in_template; *p; p++)
+ {
+ switch (*p)
+ {
+ default:
+ *obufp++ = *p;
+ break;
+ case '%':
+ len++;
+ break;
+ case '!':
+ cond = 0;
+ break;
+ case '{':
+ if (intel_syntax)
+ {
+ while (*++p != '|')
+ if (*p == '}' || *p == '\0')
+ abort ();
+ }
+ /* Fall through. */
+ case 'I':
+ alt = 1;
+ continue;
+ case '|':
+ while (*++p != '}')
+ {
+ if (*p == '\0')
+ abort ();
+ }
+ break;
+ case '}':
+ break;
+ case 'A':
+ if (intel_syntax)
+ break;
+ if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = 'b';
+ break;
+ case 'B':
+ if (l == 0 && len == 1)
+ {
+case_B:
+ if (intel_syntax)
+ break;
+ if (sizeflag & SUFFIX_ALWAYS)
+ *obufp++ = 'b';
+ }
+ else
+ {
+ if (l != 1
+ || len != 2
+ || last[0] != 'L')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+
+ if (address_mode == mode_64bit
+ && !(prefixes & PREFIX_ADDR))
+ {
+ *obufp++ = 'a';
+ *obufp++ = 'b';
+ *obufp++ = 's';
+ }
+
+ goto case_B;
+ }
+ break;
+ case 'C':
+ if (intel_syntax && !alt)
+ break;
+ if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = intel_syntax ? 'w' : 's';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case 'D':
+ if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
+ break;
+ USED_REX (REX_W);
+ if (modrm.mod == 3)
+ {
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ else
+ *obufp++ = 'w';
+ break;
+ case 'E': /* For jcxz/jecxz */
+ if (address_mode == mode_64bit)
+ {
+ if (sizeflag & AFLAG)
+ *obufp++ = 'r';
+ else
+ *obufp++ = 'e';
+ }
+ else
+ if (sizeflag & AFLAG)
+ *obufp++ = 'e';
+ used_prefixes |= (prefixes & PREFIX_ADDR);
+ break;
+ case 'F':
+ if (intel_syntax)
+ break;
+ if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (sizeflag & AFLAG)
+ *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
+ else
+ *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
+ used_prefixes |= (prefixes & PREFIX_ADDR);
+ }
+ break;
+ case 'G':
+ if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ if ((rex & REX_W) || (sizeflag & DFLAG))
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case 'H':
+ if (intel_syntax)
+ break;
+ if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
+ || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
+ {
+ used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
+ *obufp++ = ',';
+ *obufp++ = 'p';
+ if (prefixes & PREFIX_DS)
+ *obufp++ = 't';
+ else
+ *obufp++ = 'n';
+ }
+ break;
+ case 'J':
+ if (intel_syntax)
+ break;
+ *obufp++ = 'l';
+ break;
+ case 'K':
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ *obufp++ = 'd';
+ break;
+ case 'Z':
+ if (l != 0 || len != 1)
+ {
+ if (l != 1 || len != 2 || last[0] != 'X')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+ if (!need_vex || !vex.evex)
+ abort ();
+ if (intel_syntax
+ || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ switch (vex.length)
+ {
+ case 128:
+ *obufp++ = 'x';
+ break;
+ case 256:
+ *obufp++ = 'y';
+ break;
+ case 512:
+ *obufp++ = 'z';
+ break;
+ default:
+ abort ();
+ }
+ break;
+ }
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
+ goto case_L;
+ case 'L':
+ if (l != 0 || len != 1)
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+case_L:
+ if (intel_syntax)
+ break;
+ if (sizeflag & SUFFIX_ALWAYS)
+ *obufp++ = 'l';
+ break;
+ case 'M':
+ if (intel_mnemonic != cond)
+ *obufp++ = 'r';
+ break;
+ case 'N':
+ if ((prefixes & PREFIX_FWAIT) == 0)
+ *obufp++ = 'n';
+ else
+ used_prefixes |= PREFIX_FWAIT;
+ break;
+ case 'O':
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'o';
+ else if (intel_syntax && (sizeflag & DFLAG))
+ *obufp++ = 'q';
+ else
+ *obufp++ = 'd';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case '&':
+ if (!intel_syntax
+ && address_mode == mode_64bit
+ && isa64 == intel64)
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
+ case 'T':
+ if (!intel_syntax
+ && address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
+ goto case_P;
+ case 'P':
+ if (l == 0 && len == 1)
+ {
+case_P:
+ if (intel_syntax)
+ {
+ if ((rex & REX_W) == 0
+ && (prefixes & PREFIX_DATA))
+ {
+ if ((sizeflag & DFLAG) == 0)
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ }
+ if ((prefixes & PREFIX_DATA)
+ || (rex & REX_W)
+ || (sizeflag & SUFFIX_ALWAYS))
+ {
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ }
+ else
+ {
+ if (l != 1 || len != 2 || last[0] != 'L')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+
+ if ((prefixes & PREFIX_DATA)
+ || (rex & REX_W)
+ || (sizeflag & SUFFIX_ALWAYS))
+ {
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ }
+ break;
+ case 'U':
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
+ goto case_Q;
+ case 'Q':
+ if (l == 0 && len == 1)
+ {
+case_Q:
+ if (intel_syntax && !alt)
+ break;
+ USED_REX (REX_W);
+ if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ }
+ else
+ {
+ if (l != 1 || len != 2 || last[0] != 'L')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+ if (intel_syntax
+ || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ if ((rex & REX_W))
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ }
+ else
+ *obufp++ = 'l';
+ }
+ break;
+ case 'R':
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else if (sizeflag & DFLAG)
+ {
+ if (intel_syntax)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 'l';
+ }
+ else
+ *obufp++ = 'w';
+ if (intel_syntax && !p[1]
+ && ((rex & REX_W) || (sizeflag & DFLAG)))
+ *obufp++ = 'e';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case 'V':
+ if (l == 0 && len == 1)
+ {
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ if (sizeflag & SUFFIX_ALWAYS)
+ *obufp++ = 'q';
+ break;
+ }
+ }
+ else
+ {
+ if (l != 1
+ || len != 2
+ || last[0] != 'L')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+
+ if (rex & REX_W)
+ {
+ *obufp++ = 'a';
+ *obufp++ = 'b';
+ *obufp++ = 's';
+ }
+ }
+ /* Fall through. */
+ goto case_S;
+ case 'S':
+ if (l == 0 && len == 1)
+ {
+case_S:
+ if (intel_syntax)
+ break;
+ if (sizeflag & SUFFIX_ALWAYS)
+ {
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ }
+ }
+ else
+ {
+ if (l != 1
+ || len != 2
+ || last[0] != 'L')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+
+ if (address_mode == mode_64bit
+ && !(prefixes & PREFIX_ADDR))
+ {
+ *obufp++ = 'a';
+ *obufp++ = 'b';
+ *obufp++ = 's';
+ }
+
+ goto case_S;
+ }
+ break;
+ case 'X':
+ if (l != 0 || len != 1)
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+ if (need_vex && vex.prefix)
+ {
+ if (vex.prefix == DATA_PREFIX_OPCODE)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 's';
+ }
+ else
+ {
+ if (prefixes & PREFIX_DATA)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 's';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case 'Y':
+ if (l == 0 && len == 1)
+ {
+ if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
+ break;
+ if (rex & REX_W)
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ }
+ break;
+ }
+ else
+ {
+ if (l != 1 || len != 2 || last[0] != 'X')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+ if (!need_vex)
+ abort ();
+ if (intel_syntax
+ || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ switch (vex.length)
+ {
+ case 128:
+ *obufp++ = 'x';
+ break;
+ case 256:
+ *obufp++ = 'y';
+ break;
+ case 512:
+ if (!vex.evex)
+ default:
+ abort ();
+ }
+ }
+ break;
+ case 'W':
+ if (l == 0 && len == 1)
+ {
+ /* operand size flag for cwtl, cbtw */
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ {
+ if (intel_syntax)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 'l';
+ }
+ else if (sizeflag & DFLAG)
+ *obufp++ = 'w';
+ else
+ *obufp++ = 'b';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ else
+ {
+ if (l != 1
+ || len != 2
+ || (last[0] != 'X'
+ && last[0] != 'L'))
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+ if (!need_vex)
+ abort ();
+ if (last[0] == 'X')
+ *obufp++ = vex.w ? 'd': 's';
+ else
+ *obufp++ = vex.w ? 'q': 'd';
+ }
+ break;
+ case '^':
+ if (intel_syntax)
+ break;
+ if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case '@':
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit
+ && (isa64 == intel64
+ || ((sizeflag & DFLAG) || (rex & REX_W))))
+ *obufp++ = 'q';
+ else if ((prefixes & PREFIX_DATA))
+ {
+ if (!(sizeflag & DFLAG))
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ }
+ alt = 0;
+ }
+ *obufp = 0;
+ mnemonicendp = obufp;
+ return 0;
+}
+
+static void
+oappend (const char *s)
+{
+ obufp = stpcpy (obufp, s);
+}
+
+static void
+append_seg (void)
+{
+ /* Only print the active segment register. */
+ if (!active_seg_prefix)
+ return;
+
+ used_prefixes |= active_seg_prefix;
+ switch (active_seg_prefix)
+ {
+ case PREFIX_CS:
+ oappend_maybe_intel ("%cs:");
+ break;
+ case PREFIX_DS:
+ oappend_maybe_intel ("%ds:");
+ break;
+ case PREFIX_SS:
+ oappend_maybe_intel ("%ss:");
+ break;
+ case PREFIX_ES:
+ oappend_maybe_intel ("%es:");
+ break;
+ case PREFIX_FS:
+ oappend_maybe_intel ("%fs:");
+ break;
+ case PREFIX_GS:
+ oappend_maybe_intel ("%gs:");
+ break;
+ default:
+ break;
+ }
+}
+
+static void
+OP_indirE (int bytemode, int sizeflag)
+{
+ if (!intel_syntax)
+ oappend ("*");
+ OP_E (bytemode, sizeflag);
+}
+
+static void
+print_operand_value (char *buf, int hex, bfd_vma disp)
+{
+ if (address_mode == mode_64bit)
+ {
+ if (hex)
+ {
+ char tmp[30];
+ int i;
+ buf[0] = '0';
+ buf[1] = 'x';
+ sprintf_vma (tmp, disp);
+ for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
+ strcpy (buf + 2, tmp + i);
+ }
+ else
+ {
+ bfd_signed_vma v = disp;
+ char tmp[30];
+ int i;
+ if (v < 0)
+ {
+ *(buf++) = '-';
+ v = -disp;
+ /* Check for possible overflow on 0x8000000000000000. */
+ if (v < 0)
+ {
+ strcpy (buf, "9223372036854775808");
+ return;
+ }
+ }
+ if (!v)
+ {
+ strcpy (buf, "0");
+ return;
+ }
+
+ i = 0;
+ tmp[29] = 0;
+ while (v)
+ {
+ tmp[28 - i] = (v % 10) + '0';
+ v /= 10;
+ i++;
+ }
+ strcpy (buf, tmp + 29 - i);
+ }
+ }
+ else
+ {
+ if (hex)
+ sprintf (buf, "0x%x", (unsigned int) disp);
+ else
+ sprintf (buf, "%d", (int) disp);
+ }
+}
+
+/* Put DISP in BUF as signed hex number. */
+
+static void
+print_displacement (char *buf, bfd_vma disp)
+{
+ bfd_signed_vma val = disp;
+ char tmp[30];
+ int i, j = 0;
+
+ if (val < 0)
+ {
+ buf[j++] = '-';
+ val = -disp;
+
+ /* Check for possible overflow. */
+ if (val < 0)
+ {
+ switch (address_mode)
+ {
+ case mode_64bit:
+ strcpy (buf + j, "0x8000000000000000");
+ break;
+ case mode_32bit:
+ strcpy (buf + j, "0x80000000");
+ break;
+ case mode_16bit:
+ strcpy (buf + j, "0x8000");
+ break;
+ }
+ return;
+ }
+ }
+
+ buf[j++] = '0';
+ buf[j++] = 'x';
+
+ sprintf_vma (tmp, (bfd_vma) val);
+ for (i = 0; tmp[i] == '0'; i++)
+ continue;
+ if (tmp[i] == '\0')
+ i--;
+ strcpy (buf + j, tmp + i);
+}
+
+static void
+intel_operand_size (int bytemode, int sizeflag)
+{
+ if (vex.evex
+ && vex.b
+ && (bytemode == x_mode
+ || bytemode == evex_half_bcst_xmmq_mode))
+ {
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ return;
+ }
+ switch (bytemode)
+ {
+ case b_mode:
+ case b_swap_mode:
+ case dqb_mode:
+ case db_mode:
+ oappend ("BYTE PTR ");
+ break;
+ case w_mode:
+ case dw_mode:
+ case dqw_mode:
+ case dqw_swap_mode:
+ oappend ("WORD PTR ");
+ break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ oappend ("QWORD PTR ");
+ break;
+ }
+ /* Fall through. */
+ case stack_v_mode:
+ if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ oappend ("QWORD PTR ");
+ break;
+ }
+ /* Fall through. */
+ case v_mode:
+ case v_swap_mode:
+ case dq_mode:
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ oappend ("QWORD PTR ");
+ else
+ {
+ if ((sizeflag & DFLAG) || bytemode == dq_mode)
+ oappend ("DWORD PTR ");
+ else
+ oappend ("WORD PTR ");
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case z_mode:
+ if ((rex & REX_W) || (sizeflag & DFLAG))
+ *obufp++ = 'D';
+ oappend ("WORD PTR ");
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case a_mode:
+ if (sizeflag & DFLAG)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case d_mode:
+ case d_scalar_mode:
+ case d_scalar_swap_mode:
+ case d_swap_mode:
+ case dqd_mode:
+ oappend ("DWORD PTR ");
+ break;
+ case q_mode:
+ case q_scalar_mode:
+ case q_scalar_swap_mode:
+ case q_swap_mode:
+ oappend ("QWORD PTR ");
+ break;
+ case m_mode:
+ if (address_mode == mode_64bit)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ break;
+ case f_mode:
+ if (sizeflag & DFLAG)
+ oappend ("FWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case t_mode:
+ oappend ("TBYTE PTR ");
+ break;
+ case x_mode:
+ case x_swap_mode:
+ case evex_x_gscat_mode:
+ case evex_x_nobcst_mode:
+ if (need_vex)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("XMMWORD PTR ");
+ break;
+ case 256:
+ oappend ("YMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ }
+ else
+ oappend ("XMMWORD PTR ");
+ break;
+ case xmm_mode:
+ oappend ("XMMWORD PTR ");
+ break;
+ case ymm_mode:
+ oappend ("YMMWORD PTR ");
+ break;
+ case xmmq_mode:
+ case evex_half_bcst_xmmq_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("QWORD PTR ");
+ break;
+ case 256:
+ oappend ("XMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("YMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_mb_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("BYTE PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_mw_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("WORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_md_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("DWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_mq_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("QWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmmdw_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("WORD PTR ");
+ break;
+ case 256:
+ oappend ("DWORD PTR ");
+ break;
+ case 512:
+ oappend ("QWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmmqd_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("DWORD PTR ");
+ break;
+ case 256:
+ oappend ("QWORD PTR ");
+ break;
+ case 512:
+ oappend ("XMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case ymmq_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("QWORD PTR ");
+ break;
+ case 256:
+ oappend ("YMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case ymmxmm_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ oappend ("XMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case o_mode:
+ oappend ("OWORD PTR ");
+ break;
+ case xmm_mdq_mode:
+ case vex_w_dq_mode:
+ case vex_scalar_w_dq_mode:
+ if (!need_vex)
+ abort ();
+
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ break;
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_q_w_dq_mode:
+ if (!need_vex)
+ abort ();
+
+ if (!vex.evex)
+ {
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ }
+ else
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("XMMWORD PTR ");
+ break;
+ case 256:
+ oappend ("YMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ }
+ break;
+ case vex_vsib_q_w_d_mode:
+ case vex_vsib_d_w_d_mode:
+ if (!need_vex || !vex.evex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("QWORD PTR ");
+ break;
+ case 256:
+ oappend ("XMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("YMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+
+ break;
+ case mask_bd_mode:
+ if (!need_vex || vex.length != 128)
+ abort ();
+ if (vex.w)
+ oappend ("DWORD PTR ");
+ else
+ oappend ("BYTE PTR ");
+ break;
+ case mask_mode:
+ if (!need_vex)
+ abort ();
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("WORD PTR ");
+ break;
+ case v_bnd_mode:
+ default:
+ break;
+ }
+}
+
+static void
+OP_E_register (int bytemode, int sizeflag)
+{
+ int reg = modrm.rm;
+ const char **names;
+
+ USED_REX (REX_B);
+ if ((rex & REX_B))
+ reg += 8;
+
+ if ((sizeflag & SUFFIX_ALWAYS)
+ && (bytemode == b_swap_mode
+ || bytemode == v_swap_mode
+ || bytemode == dqw_swap_mode))
+ swap_operand ();
+
+ switch (bytemode)
+ {
+ case b_mode:
+ case b_swap_mode:
+ USED_REX (0);
+ if (rex)
+ names = names8rex;
+ else
+ names = names8;
+ break;
+ case w_mode:
+ names = names16;
+ break;
+ case d_mode:
+ case dw_mode:
+ case db_mode:
+ names = names32;
+ break;
+ case q_mode:
+ names = names64;
+ break;
+ case m_mode:
+ case v_bnd_mode:
+ names = address_mode == mode_64bit ? names64 : names32;
+ break;
+ case bnd_mode:
+ names = names_bnd;
+ break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ names = names64;
+ break;
+ }
+ /* Fall through. */
+ case stack_v_mode:
+ if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ names = names64;
+ break;
+ }
+ bytemode = v_mode;
+ /* Fall through. */
+ case v_mode:
+ case v_swap_mode:
+ case dq_mode:
+ case dqb_mode:
+ case dqd_mode:
+ case dqw_mode:
+ case dqw_swap_mode:
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ names = names64;
+ else
+ {
+ if ((sizeflag & DFLAG)
+ || (bytemode != v_mode
+ && bytemode != v_swap_mode))
+ names = names32;
+ else
+ names = names16;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case mask_bd_mode:
+ case mask_mode:
+ if (reg > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_mask;
+ break;
+ case 0:
+ return;
+ default:
+ oappend (INTERNAL_DISASSEMBLER_ERROR);
+ return;
+ }
+ oappend (names[reg]);
+}
+
+static void
+OP_E_memory (int bytemode, int sizeflag)
+{
+ bfd_vma disp = 0;
+ int add = (rex & REX_B) ? 8 : 0;
+ int riprel = 0;
+ int shift;
+
+ if (vex.evex)
+ {
+ /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
+ if (vex.b
+ && bytemode != x_mode
+ && bytemode != xmmq_mode
+ && bytemode != evex_half_bcst_xmmq_mode)
+ {
+ BadOp ();
+ return;
+ }
+ switch (bytemode)
+ {
+ case dqw_mode:
+ case dw_mode:
+ case dqw_swap_mode:
+ shift = 1;
+ break;
+ case dqb_mode:
+ case db_mode:
+ shift = 0;
+ break;
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_d_w_d_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ case evex_x_gscat_mode:
+ case xmm_mdq_mode:
+ shift = vex.w ? 3 : 2;
+ break;
+ case x_mode:
+ case evex_half_bcst_xmmq_mode:
+ case xmmq_mode:
+ if (vex.b)
+ {
+ shift = vex.w ? 3 : 2;
+ break;
+ }
+ /* Fall through. */
+ case xmmqd_mode:
+ case xmmdw_mode:
+ case ymmq_mode:
+ case evex_x_nobcst_mode:
+ case x_swap_mode:
+ switch (vex.length)
+ {
+ case 128:
+ shift = 4;
+ break;
+ case 256:
+ shift = 5;
+ break;
+ case 512:
+ shift = 6;
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case ymm_mode:
+ shift = 5;
+ break;
+ case xmm_mode:
+ shift = 4;
+ break;
+ case xmm_mq_mode:
+ case q_mode:
+ case q_scalar_mode:
+ case q_swap_mode:
+ case q_scalar_swap_mode:
+ shift = 3;
+ break;
+ case dqd_mode:
+ case xmm_md_mode:
+ case d_mode:
+ case d_scalar_mode:
+ case d_swap_mode:
+ case d_scalar_swap_mode:
+ shift = 2;
+ break;
+ case xmm_mw_mode:
+ shift = 1;
+ break;
+ case xmm_mb_mode:
+ shift = 0;
+ break;
+ default:
+ abort ();
+ }
+ /* Make necessary corrections to shift for modes that need it.
+ For these modes we currently have shift 4, 5 or 6 depending on
+ vex.length (it corresponds to xmmword, ymmword or zmmword
+ operand). We might want to make it 3, 4 or 5 (e.g. for
+ xmmq_mode). In case of broadcast enabled the corrections
+ aren't needed, as element size is always 32 or 64 bits. */
+ if (!vex.b
+ && (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode))
+ shift -= 1;
+ else if (bytemode == xmmqd_mode)
+ shift -= 2;
+ else if (bytemode == xmmdw_mode)
+ shift -= 3;
+ else if (bytemode == ymmq_mode && vex.length == 128)
+ shift -= 1;
+ }
+ else
+ shift = 0;
+
+ USED_REX (REX_B);
+ if (intel_syntax)
+ intel_operand_size (bytemode, sizeflag);
+ append_seg ();
+
+ if ((sizeflag & AFLAG) || address_mode == mode_64bit)
+ {
+ /* 32/64 bit address mode */
+ int havedisp;
+ int havesib;
+ int havebase;
+ int haveindex;
+ int needindex;
+ int base, rbase;
+ int vindex = 0;
+ int scale = 0;
+ int addr32flag = !((sizeflag & AFLAG)
+ || bytemode == v_bnd_mode
+ || bytemode == bnd_mode);
+ const char **indexes64 = names64;
+ const char **indexes32 = names32;
+
+ havesib = 0;
+ havebase = 1;
+ haveindex = 0;
+ base = modrm.rm;
+
+ if (base == 4)
+ {
+ havesib = 1;
+ vindex = sib.index;
+ USED_REX (REX_X);
+ if (rex & REX_X)
+ vindex += 8;
+ switch (bytemode)
+ {
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_d_w_d_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ if (!need_vex)
+ abort ();
+ if (vex.evex)
+ {
+ if (!vex.v)
+ vindex += 16;
+ }
+
+ haveindex = 1;
+ switch (vex.length)
+ {
+ case 128:
+ indexes64 = indexes32 = names_xmm;
+ break;
+ case 256:
+ if (!vex.w
+ || bytemode == vex_vsib_q_w_dq_mode
+ || bytemode == vex_vsib_q_w_d_mode)
+ indexes64 = indexes32 = names_ymm;
+ else
+ indexes64 = indexes32 = names_xmm;
+ break;
+ case 512:
+ if (!vex.w
+ || bytemode == vex_vsib_q_w_dq_mode
+ || bytemode == vex_vsib_q_w_d_mode)
+ indexes64 = indexes32 = names_zmm;
+ else
+ indexes64 = indexes32 = names_ymm;
+ break;
+ default:
+ abort ();
+ }
+ break;
+ default:
+ haveindex = vindex != 4;
+ break;
+ }
+ scale = sib.scale;
+ base = sib.base;
+ codep++;
+ }
+ rbase = base + add;
+
+ switch (modrm.mod)
+ {
+ case 0:
+ if (base == 5)
+ {
+ havebase = 0;
+ if (address_mode == mode_64bit && !havesib)
+ riprel = 1;
+ disp = get32s ();
+ }
+ break;
+ case 1:
+ FETCH_DATA (the_info, codep + 1);
+ disp = *codep++;
+ if ((disp & 0x80) != 0)
+ disp -= 0x100;
+ if (vex.evex && shift > 0)
+ disp <<= shift;
+ break;
+ case 2:
+ disp = get32s ();
+ break;
+ }
+
+ /* In 32bit mode, we need index register to tell [offset] from
+ [eiz*1 + offset]. */
+ needindex = (havesib
+ && !havebase
+ && !haveindex
+ && address_mode == mode_32bit);
+ havedisp = (havebase
+ || needindex
+ || (havesib && (haveindex || scale != 0)));
+
+ if (!intel_syntax)
+ if (modrm.mod != 0 || base == 5)
+ {
+ if (havedisp || riprel)
+ print_displacement (scratchbuf, disp);
+ else
+ print_operand_value (scratchbuf, 1, disp);
+ oappend (scratchbuf);
+ if (riprel)
+ {
+ set_op (disp, 1);
+ oappend (!addr32flag ? "(%rip)" : "(%eip)");
+ }
+ }
+
+ if ((havebase || haveindex || riprel)
+ && (bytemode != v_bnd_mode)
+ && (bytemode != bnd_mode))
+ used_prefixes |= PREFIX_ADDR;
+
+ if (havedisp || (intel_syntax && riprel))
+ {
+ *obufp++ = open_char;
+ if (intel_syntax && riprel)
+ {
+ set_op (disp, 1);
+ oappend (!addr32flag ? "rip" : "eip");
+ }
+ *obufp = '\0';
+ if (havebase)
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? names64[rbase] : names32[rbase]);
+ if (havesib)
+ {
+ /* ESP/RSP won't allow index. If base isn't ESP/RSP,
+ print index to tell base + index from base. */
+ if (scale != 0
+ || needindex
+ || haveindex
+ || (havebase && base != ESP_REG_NUM))
+ {
+ if (!intel_syntax || havebase)
+ {
+ *obufp++ = separator_char;
+ *obufp = '\0';
+ }
+ if (haveindex)
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? indexes64[vindex] : indexes32[vindex]);
+ else
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? index64 : index32);
+
+ *obufp++ = scale_char;
+ *obufp = '\0';
+ sprintf (scratchbuf, "%d", 1 << scale);
+ oappend (scratchbuf);
+ }
+ }
+ if (intel_syntax
+ && (disp || modrm.mod != 0 || base == 5))
+ {
+ if (!havedisp || (bfd_signed_vma) disp >= 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (modrm.mod != 1 && disp != -disp)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
+
+ if (havedisp)
+ print_displacement (scratchbuf, disp);
+ else
+ print_operand_value (scratchbuf, 1, disp);
+ oappend (scratchbuf);
+ }
+
+ *obufp++ = close_char;
+ *obufp = '\0';
+ }
+ else if (intel_syntax)
+ {
+ if (modrm.mod != 0 || base == 5)
+ {
+ if (!active_seg_prefix)
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
+ print_operand_value (scratchbuf, 1, disp);
+ oappend (scratchbuf);
+ }
+ }
+ }
+ else
+ {
+ /* 16 bit address mode */
+ used_prefixes |= prefixes & PREFIX_ADDR;
+ switch (modrm.mod)
+ {
+ case 0:
+ if (modrm.rm == 6)
+ {
+ disp = get16 ();
+ if ((disp & 0x8000) != 0)
+ disp -= 0x10000;
+ }
+ break;
+ case 1:
+ FETCH_DATA (the_info, codep + 1);
+ disp = *codep++;
+ if ((disp & 0x80) != 0)
+ disp -= 0x100;
+ break;
+ case 2:
+ disp = get16 ();
+ if ((disp & 0x8000) != 0)
+ disp -= 0x10000;
+ break;
+ }
+
+ if (!intel_syntax)
+ if (modrm.mod != 0 || modrm.rm == 6)
+ {
+ print_displacement (scratchbuf, disp);
+ oappend (scratchbuf);
+ }
+
+ if (modrm.mod != 0 || modrm.rm != 6)
+ {
+ *obufp++ = open_char;
+ *obufp = '\0';
+ oappend (index16[modrm.rm]);
+ if (intel_syntax
+ && (disp || modrm.mod != 0 || modrm.rm == 6))
+ {
+ if ((bfd_signed_vma) disp >= 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (modrm.mod != 1)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
+
+ print_displacement (scratchbuf, disp);
+ oappend (scratchbuf);
+ }
+
+ *obufp++ = close_char;
+ *obufp = '\0';
+ }
+ else if (intel_syntax)
+ {
+ if (!active_seg_prefix)
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
+ print_operand_value (scratchbuf, 1, disp & 0xffff);
+ oappend (scratchbuf);
+ }
+ }
+ if (vex.evex && vex.b
+ && (bytemode == x_mode
+ || bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode))
+ {
+ if (vex.w
+ || bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("{1to2}");
+ break;
+ case 256:
+ oappend ("{1to4}");
+ break;
+ case 512:
+ oappend ("{1to8}");
+ break;
+ default:
+ abort ();
+ }
+ }
+ else
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("{1to4}");
+ break;
+ case 256:
+ oappend ("{1to8}");
+ break;
+ case 512:
+ oappend ("{1to16}");
+ break;
+ default:
+ abort ();
+ }
+ }
+ }
+}
+
+static void
+OP_E (int bytemode, int sizeflag)
+{
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+
+ if (modrm.mod == 3)
+ OP_E_register (bytemode, sizeflag);
+ else
+ OP_E_memory (bytemode, sizeflag);
+}
+
+static void
+OP_G (int bytemode, int sizeflag)
+{
+ int add = 0;
+ USED_REX (REX_R);
+ if (rex & REX_R)
+ add += 8;
+ switch (bytemode)
+ {
+ case b_mode:
+ USED_REX (0);
+ if (rex)
+ oappend (names8rex[modrm.reg + add]);
+ else
+ oappend (names8[modrm.reg + add]);
+ break;
+ case w_mode:
+ oappend (names16[modrm.reg + add]);
+ break;
+ case d_mode:
+ case db_mode:
+ case dw_mode:
+ oappend (names32[modrm.reg + add]);
+ break;
+ case q_mode:
+ oappend (names64[modrm.reg + add]);
+ break;
+ case bnd_mode:
+ oappend (names_bnd[modrm.reg]);
+ break;
+ case v_mode:
+ case dq_mode:
+ case dqb_mode:
+ case dqd_mode:
+ case dqw_mode:
+ case dqw_swap_mode:
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ oappend (names64[modrm.reg + add]);
+ else
+ {
+ if ((sizeflag & DFLAG) || bytemode != v_mode)
+ oappend (names32[modrm.reg + add]);
+ else
+ oappend (names16[modrm.reg + add]);
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case m_mode:
+ if (address_mode == mode_64bit)
+ oappend (names64[modrm.reg + add]);
+ else
+ oappend (names32[modrm.reg + add]);
+ break;
+ case mask_bd_mode:
+ case mask_mode:
+ if ((modrm.reg + add) > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ oappend (names_mask[modrm.reg + add]);
+ break;
+ default:
+ oappend (INTERNAL_DISASSEMBLER_ERROR);
+ break;
+ }
+}
+
+static bfd_vma
+get64 (void)
+{
+ bfd_vma x;
+#ifdef BFD64
+ unsigned int a;
+ unsigned int b;