+ { "CPU_ANY_AVX512_4FMAPS_FLAGS",
+ "CpuAVX512_4FMAPS" },
+ { "CPU_ANY_AVX512_4VNNIW_FLAGS",
+ "CpuAVX512_4VNNIW" },
+ { "CPU_ANY_AVX512_VPOPCNTDQ_FLAGS",
+ "CpuAVX512_VPOPCNTDQ" },
+ { "CPU_ANY_IBT_FLAGS",
+ "CpuIBT" },
+ { "CPU_ANY_SHSTK_FLAGS",
+ "CpuSHSTK" },
+ { "CPU_ANY_AVX512_VBMI2_FLAGS",
+ "CpuAVX512_VBMI2" },
+ { "CPU_ANY_AVX512_VNNI_FLAGS",
+ "CpuAVX512_VNNI" },
+ { "CPU_ANY_AVX512_BITALG_FLAGS",
+ "CpuAVX512_BITALG" },
+ { "CPU_ANY_AVX512_BF16_FLAGS",
+ "CpuAVX512_BF16" },
+ { "CPU_ANY_MOVDIRI_FLAGS",
+ "CpuMOVDIRI" },
+ { "CPU_ANY_MOVDIR64B_FLAGS",
+ "CpuMOVDIR64B" },
+ { "CPU_ANY_ENQCMD_FLAGS",
+ "CpuENQCMD" },
+ { "CPU_ANY_AVX512_VP2INTERSECT_FLAGS",
+ "CpuAVX512_VP2INTERSECT" },
+};
+
+static const initializer operand_type_shorthands[] =
+{
+ { "Reg8", "Reg|Byte" },
+ { "Reg16", "Reg|Word" },
+ { "Reg32", "Reg|Dword" },
+ { "Reg64", "Reg|Qword" },
+ { "FloatAcc", "Acc|Tbyte" },
+ { "FloatReg", "Reg|Tbyte" },
+ { "RegXMM", "RegSIMD|Xmmword" },
+ { "RegYMM", "RegSIMD|Ymmword" },
+ { "RegZMM", "RegSIMD|Zmmword" },