+ "CPU_XSAVE_FLAGS|CpuXSAVEC" },
+ { "CPU_PREFETCHWT1_FLAGS",
+ "CpuPREFETCHWT1" },
+ { "CPU_SE1_FLAGS",
+ "CpuSE1" },
+ { "CPU_CLWB_FLAGS",
+ "CpuCLWB" },
+ { "CPU_CLZERO_FLAGS",
+ "CpuCLZERO" },
+ { "CPU_MWAITX_FLAGS",
+ "CpuMWAITX" },
+ { "CPU_OSPKE_FLAGS",
+ "CpuOSPKE" },
+ { "CPU_RDPID_FLAGS",
+ "CpuRDPID" },
+ { "CPU_PTWRITE_FLAGS",
+ "CpuPTWRITE" },
+ { "CPU_CET_FLAGS",
+ "CpuCET" },
+ { "CPU_ANY_X87_FLAGS",
+ "CPU_ANY_287_FLAGS|Cpu8087" },
+ { "CPU_ANY_287_FLAGS",
+ "CPU_ANY_387_FLAGS|Cpu287" },
+ { "CPU_ANY_387_FLAGS",
+ "CPU_ANY_687_FLAGS|Cpu387" },
+ { "CPU_ANY_687_FLAGS",
+ "Cpu687|CpuFISTTP" },
+ { "CPU_ANY_MMX_FLAGS",
+ "CPU_3DNOWA_FLAGS" },
+ { "CPU_ANY_SSE_FLAGS",
+ "CPU_ANY_SSE2_FLAGS|CpuSSE|CpuSSE4a" },
+ { "CPU_ANY_SSE2_FLAGS",
+ "CPU_ANY_SSE3_FLAGS|CpuSSE2" },
+ { "CPU_ANY_SSE3_FLAGS",
+ "CPU_ANY_SSSE3_FLAGS|CpuSSE3" },
+ { "CPU_ANY_SSSE3_FLAGS",
+ "CPU_ANY_SSE4_1_FLAGS|CpuSSSE3" },
+ { "CPU_ANY_SSE4_1_FLAGS",
+ "CPU_ANY_SSE4_2_FLAGS|CpuSSE4_1" },
+ { "CPU_ANY_SSE4_2_FLAGS",
+ "CpuSSE4_2" },
+ { "CPU_ANY_AVX_FLAGS",
+ "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
+ { "CPU_ANY_AVX2_FLAGS",
+ "CpuAVX2" },
+ { "CPU_ANY_AVX512F_FLAGS",
+ "CpuVREX|CpuRegZMM|CpuRegMask|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CpuAVX512BW|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512F" },
+ { "CPU_ANY_AVX512CD_FLAGS",
+ "CpuAVX512CD" },
+ { "CPU_ANY_AVX512ER_FLAGS",
+ "CpuAVX512ER" },
+ { "CPU_ANY_AVX512PF_FLAGS",
+ "CpuAVX512PF" },
+ { "CPU_ANY_AVX512DQ_FLAGS",
+ "CpuAVX512DQ" },
+ { "CPU_ANY_AVX512BW_FLAGS",
+ "CpuAVX512BW" },
+ { "CPU_ANY_AVX512VL_FLAGS",
+ "CpuAVX512VL" },
+ { "CPU_ANY_AVX512IFMA_FLAGS",
+ "CpuAVX512IFMA" },
+ { "CPU_ANY_AVX512VBMI_FLAGS",
+ "CpuAVX512VBMI" },
+ { "CPU_ANY_AVX512_4FMAPS_FLAGS",
+ "CpuAVX512_4FMAPS" },
+ { "CPU_ANY_AVX512_4VNNIW_FLAGS",
+ "CpuAVX512_4VNNIW" },
+ { "CPU_ANY_AVX512_VPOPCNTDQ_FLAGS",
+ "CpuAVX512_VPOPCNTDQ" },