-/* has direction bit. */
-#define D 0
-/* set if operands can be words or dwords encoded the canonical way */
-#define W (D + 1)
-/* Skip the current insn and use the next insn in i386-opc.tbl to swap
- operand in encoding. */
-#define S (W + 1)
-/* insn has a modrm byte. */
-#define Modrm (S + 1)
-/* register is in low 3 bits of opcode */
-#define ShortForm (Modrm + 1)
-/* special case for jump insns. */
-#define Jump (ShortForm + 1)
-/* call and jump */
-#define JumpDword (Jump + 1)
-/* loop and jecxz */
-#define JumpByte (JumpDword + 1)
-/* special case for intersegment leaps/calls */
-#define JumpInterSegment (JumpByte + 1)
-/* FP insn memory format bit, sized by 0x4 */
-#define FloatMF (JumpInterSegment + 1)
-/* src/dest swap for floats. */
-#define FloatR (FloatMF + 1)
-/* has float insn direction bit. */
-#define FloatD (FloatR + 1)
-/* needs size prefix if in 32-bit mode */
-#define Size16 (FloatD + 1)
-/* needs size prefix if in 16-bit mode */
-#define Size32 (Size16 + 1)
-/* needs size prefix if in 64-bit mode */
-#define Size64 (Size32 + 1)
-/* instruction ignores operand size prefix and in Intel mode ignores
- mnemonic size suffix check. */
-#define IgnoreSize (Size64 + 1)
-/* default insn size depends on mode */
-#define DefaultSize (IgnoreSize + 1)
-/* b suffix on instruction illegal */
-#define No_bSuf (DefaultSize + 1)
-/* w suffix on instruction illegal */
-#define No_wSuf (No_bSuf + 1)
-/* l suffix on instruction illegal */
-#define No_lSuf (No_wSuf + 1)
-/* s suffix on instruction illegal */
-#define No_sSuf (No_lSuf + 1)
-/* q suffix on instruction illegal */
-#define No_qSuf (No_sSuf + 1)
-/* long double suffix on instruction illegal */
-#define No_ldSuf (No_qSuf + 1)
-/* instruction needs FWAIT */
-#define FWait (No_ldSuf + 1)
-/* quick test for string instructions */
-#define IsString (FWait + 1)
-/* fake an extra reg operand for clr, imul and special register
- processing for some instructions. */
-#define RegKludge (IsString + 1)
-/* The first operand must be xmm0 */
-#define FirstXmm0 (RegKludge + 1)
-/* An implicit xmm0 as the first operand */
-#define Implicit1stXmm0 (FirstXmm0 + 1)
-/* BYTE is OK in Intel syntax. */
-#define ByteOkIntel (Implicit1stXmm0 + 1)
-/* Convert to DWORD */
-#define ToDword (ByteOkIntel + 1)
-/* Convert to QWORD */
-#define ToQword (ToDword + 1)
-/* Address prefix changes operand 0 */
-#define AddrPrefixOp0 (ToQword + 1)
-/* opcode is a prefix */
-#define IsPrefix (AddrPrefixOp0 + 1)
-/* instruction has extension in 8 bit imm */
-#define ImmExt (IsPrefix + 1)
-/* instruction don't need Rex64 prefix. */
-#define NoRex64 (ImmExt + 1)
-/* instruction require Rex64 prefix. */
-#define Rex64 (NoRex64 + 1)
-/* deprecated fp insn, gets a warning */
-#define Ugh (Rex64 + 1)
-#define Drex (Ugh + 1)
-/* instruction needs DREX with multiple encodings for memory ops */
-#define Drexv (Drex + 1)
-/* special DREX for comparisons */
-#define Drexc (Drexv + 1)
-/* insn has VEX prefix. */
-#define Vex (Drexc + 1)
-/* insn has 256bit VEX prefix. */
-#define Vex256 (Vex + 1)
-/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
- We use VexNDS on insns with VEX DDS since the register-only source
- is the second source register. */
-#define VexNDS (Vex256 + 1)
-/* insn has VEX NDD. Register destination is encoded in Vex
- prefix. */
-#define VexNDD (VexNDS + 1)
-/* insn has VEX W0. */
-#define VexW0 (VexNDD + 1)
-/* insn has VEX W1. */
-#define VexW1 (VexW0 + 1)
-/* insn has VEX 0x0F opcode prefix. */
-#define Vex0F (VexW1 + 1)
-/* insn has VEX 0x0F38 opcode prefix. */
-#define Vex0F38 (Vex0F + 1)
-/* insn has VEX 0x0F3A opcode prefix. */
-#define Vex0F3A (Vex0F38 + 1)
-/* insn has VEX prefix with 3 soures. */
-#define Vex3Sources (Vex0F3A + 1)
-/* instruction has VEX 8 bit imm */
-#define VexImmExt (Vex3Sources + 1)
-/* SSE to AVX support required */
-#define SSE2AVX (VexImmExt + 1)
-/* No AVX equivalent */
-#define NoAVX (SSE2AVX + 1)
-/* Compatible with old (<= 2.8.1) versions of gcc */
-#define OldGcc (NoAVX + 1)
-/* AT&T mnemonic. */
-#define ATTMnemonic (OldGcc + 1)
-/* AT&T syntax. */
-#define ATTSyntax (ATTMnemonic + 1)
-/* Intel syntax. */
-#define IntelSyntax (ATTSyntax + 1)
-/* The last bitfield in i386_opcode_modifier. */
-#define Opcode_Modifier_Max IntelSyntax
+enum
+{
+ /* has direction bit. */
+ D = 0,
+ /* set if operands can be words or dwords encoded the canonical way */
+ W,
+ /* Skip the current insn and use the next insn in i386-opc.tbl to swap
+ operand in encoding. */
+ S,
+ /* insn has a modrm byte. */
+ Modrm,
+ /* register is in low 3 bits of opcode */
+ ShortForm,
+ /* special case for jump insns. */
+ Jump,
+ /* call and jump */
+ JumpDword,
+ /* loop and jecxz */
+ JumpByte,
+ /* special case for intersegment leaps/calls */
+ JumpInterSegment,
+ /* FP insn memory format bit, sized by 0x4 */
+ FloatMF,
+ /* src/dest swap for floats. */
+ FloatR,
+ /* has float insn direction bit. */
+ FloatD,
+ /* needs size prefix if in 32-bit mode */
+ Size16,
+ /* needs size prefix if in 16-bit mode */
+ Size32,
+ /* needs size prefix if in 64-bit mode */
+ Size64,
+ /* check register size. */
+ CheckRegSize,
+ /* instruction ignores operand size prefix and in Intel mode ignores
+ mnemonic size suffix check. */
+ IgnoreSize,
+ /* default insn size depends on mode */
+ DefaultSize,
+ /* b suffix on instruction illegal */
+ No_bSuf,
+ /* w suffix on instruction illegal */
+ No_wSuf,
+ /* l suffix on instruction illegal */
+ No_lSuf,
+ /* s suffix on instruction illegal */
+ No_sSuf,
+ /* q suffix on instruction illegal */
+ No_qSuf,
+ /* long double suffix on instruction illegal */
+ No_ldSuf,
+ /* instruction needs FWAIT */
+ FWait,
+ /* quick test for string instructions */
+ IsString,
+ /* quick test for lockable instructions */
+ IsLockable,
+ /* fake an extra reg operand for clr, imul and special register
+ processing for some instructions. */
+ RegKludge,
+ /* The first operand must be xmm0 */
+ FirstXmm0,
+ /* An implicit xmm0 as the first operand */
+ Implicit1stXmm0,
+ /* Convert to DWORD */
+ ToDword,
+ /* Convert to QWORD */
+ ToQword,
+ /* Address prefix changes operand 0 */
+ AddrPrefixOp0,
+ /* opcode is a prefix */
+ IsPrefix,
+ /* instruction has extension in 8 bit imm */
+ ImmExt,
+ /* instruction don't need Rex64 prefix. */
+ NoRex64,
+ /* instruction require Rex64 prefix. */
+ Rex64,
+ /* deprecated fp insn, gets a warning */
+ Ugh,
+ /* insn has VEX prefix:
+ 1: 128bit VEX prefix.
+ 2: 256bit VEX prefix.
+ 3: Scalar VEX prefix.
+ */
+#define VEX128 1
+#define VEX256 2
+#define VEXScalar 3
+ Vex,
+ /* How to encode VEX.vvvv:
+ 0: VEX.vvvv must be 1111b.
+ 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
+ the content of source registers will be preserved.
+ VEX.DDS. The second register operand is encoded in VEX.vvvv
+ where the content of first source register will be overwritten
+ by the result.
+ VEX.NDD2. The second destination register operand is encoded in
+ VEX.vvvv for instructions with 2 destination register operands.
+ For assembler, there are no difference between VEX.NDS, VEX.DDS
+ and VEX.NDD2.
+ 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
+ instructions with 1 destination register operand.
+ 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
+ of the operands can access a memory location.
+ */
+#define VEXXDS 1
+#define VEXNDD 2
+#define VEXLWP 3
+ VexVVVV,
+ /* How the VEX.W bit is used:
+ 0: Set by the REX.W bit.
+ 1: VEX.W0. Should always be 0.
+ 2: VEX.W1. Should always be 1.
+ */
+#define VEXW0 1
+#define VEXW1 2
+ VexW,
+ /* VEX opcode prefix:
+ 0: VEX 0x0F opcode prefix.
+ 1: VEX 0x0F38 opcode prefix.
+ 2: VEX 0x0F3A opcode prefix
+ 3: XOP 0x08 opcode prefix.
+ 4: XOP 0x09 opcode prefix
+ 5: XOP 0x0A opcode prefix.
+ */
+#define VEX0F 0
+#define VEX0F38 1
+#define VEX0F3A 2
+#define XOP08 3
+#define XOP09 4
+#define XOP0A 5
+ VexOpcode,
+ /* number of VEX source operands:
+ 0: <= 2 source operands.
+ 1: 2 XOP source operands.
+ 2: 3 source operands.
+ */
+#define XOP2SOURCES 1
+#define VEX3SOURCES 2
+ VexSources,
+ /* instruction has VEX 8 bit imm */
+ VexImmExt,
+ /* Instruction with vector SIB byte:
+ 1: 128bit vector register.
+ 2: 256bit vector register.
+ */
+#define VecSIB128 1
+#define VecSIB256 2
+ VecSIB,
+ /* SSE to AVX support required */
+ SSE2AVX,
+ /* No AVX equivalent */
+ NoAVX,
+ /* Compatible with old (<= 2.8.1) versions of gcc */
+ OldGcc,
+ /* AT&T mnemonic. */
+ ATTMnemonic,
+ /* AT&T syntax. */
+ ATTSyntax,
+ /* Intel syntax. */
+ IntelSyntax,
+ /* The last bitfield in i386_opcode_modifier. */
+ Opcode_Modifier_Max
+};
projects / deliverable / binutils-gdb.git / blobdiff