+/* insn has VEX prefix. */
+#define Vex (Drexc + 1)
+/* insn has 256bit VEX prefix. */
+#define Vex256 (Vex + 1)
+/* insn has VEX NDS. Register-only source is encoded in Vex
+ prefix. */
+#define VexNDS (Vex256 + 1)
+/* insn has VEX NDD. Register destination is encoded in Vex
+ prefix. */
+#define VexNDD (VexNDS + 1)
+/* insn has VEX W0. */
+#define VexW0 (VexNDD + 1)
+/* insn has VEX W1. */
+#define VexW1 (VexW0 + 1)
+/* insn has VEX 0x0F opcode prefix. */
+#define Vex0F (VexW1 + 1)
+/* insn has VEX 0x0F38 opcode prefix. */
+#define Vex0F38 (Vex0F + 1)
+/* insn has VEX 0x0F3A opcode prefix. */
+#define Vex0F3A (Vex0F38 + 1)
+/* insn has VEX prefix with 3 soures. */
+#define Vex3Sources (Vex0F3A + 1)
+/* instruction has VEX 8 bit imm */
+#define VexImmExt (Vex3Sources + 1)
+/* SSE to AVX support required */
+#define SSE2AVX (VexImmExt + 1)
+/* No AVX equivalent */
+#define NoAVX (SSE2AVX + 1)