-/* i186 or better required */
-#define Cpu186 0
-/* i286 or better required */
-#define Cpu286 (Cpu186 + 1)
-/* i386 or better required */
-#define Cpu386 (Cpu286 + 1)
-/* i486 or better required */
-#define Cpu486 (Cpu386 + 1)
-/* i585 or better required */
-#define Cpu586 (Cpu486 + 1)
-/* i686 or better required */
-#define Cpu686 (Cpu586 + 1)
-/* CLFLUSH Instuction support required */
-#define CpuClflush (Cpu686 + 1)
-/* SYSCALL Instuctions support required */
-#define CpuSYSCALL (CpuClflush + 1)
-/* Floating point support required */
-#define Cpu8087 (CpuSYSCALL + 1)
-/* i287 support required */
-#define Cpu287 (Cpu8087 + 1)
-/* i387 support required */
-#define Cpu387 (Cpu287 + 1)
-/* i686 and floating point support required */
-#define Cpu687 (Cpu387 + 1)
-/* SSE3 and floating point support required */
-#define CpuFISTTP (Cpu687 + 1)
-/* MMX support required */
-#define CpuMMX (CpuFISTTP + 1)
-/* SSE support required */
-#define CpuSSE (CpuMMX + 1)
-/* SSE2 support required */
-#define CpuSSE2 (CpuSSE + 1)
-/* 3dnow! support required */
-#define Cpu3dnow (CpuSSE2 + 1)
-/* 3dnow! Extensions support required */
-#define Cpu3dnowA (Cpu3dnow + 1)
-/* SSE3 support required */
-#define CpuSSE3 (Cpu3dnowA + 1)
-/* VIA PadLock required */
-#define CpuPadLock (CpuSSE3 + 1)
-/* AMD Secure Virtual Machine Ext-s required */
-#define CpuSVME (CpuPadLock + 1)
-/* VMX Instructions required */
-#define CpuVMX (CpuSVME + 1)
-/* SMX Instructions required */
-#define CpuSMX (CpuVMX + 1)
-/* SSSE3 support required */
-#define CpuSSSE3 (CpuSMX + 1)
-/* SSE4a support required */
-#define CpuSSE4a (CpuSSSE3 + 1)
-/* ABM New Instructions required */
-#define CpuABM (CpuSSE4a + 1)
-/* SSE4.1 support required */
-#define CpuSSE4_1 (CpuABM + 1)
-/* SSE4.2 support required */
-#define CpuSSE4_2 (CpuSSE4_1 + 1)
-/* AVX support required */
-#define CpuAVX (CpuSSE4_2 + 1)
-/* Intel L1OM support required */
-#define CpuL1OM (CpuAVX + 1)
-/* Xsave/xrstor New Instuctions support required */
-#define CpuXsave (CpuL1OM + 1)
-/* AES support required */
-#define CpuAES (CpuXsave + 1)
-/* PCLMUL support required */
-#define CpuPCLMUL (CpuAES + 1)
-/* FMA support required */
-#define CpuFMA (CpuPCLMUL + 1)
-/* FMA4 support required */
-#define CpuFMA4 (CpuFMA + 1)
-/* MOVBE Instuction support required */
-#define CpuMovbe (CpuFMA4 + 1)
-/* EPT Instructions required */
-#define CpuEPT (CpuMovbe + 1)
-/* RDTSCP Instuction support required */
-#define CpuRdtscp (CpuEPT + 1)
-/* 64bit support available, used by -march= in assembler. */
-#define CpuLM (CpuRdtscp + 1)
-/* 64bit support required */
-#define Cpu64 (CpuLM + 1)
-/* Not supported in the 64bit mode */
-#define CpuNo64 (Cpu64 + 1)
-/* The last bitfield in i386_cpu_flags. */
-#define CpuMax CpuNo64
+enum
+{
+ /* i186 or better required */
+ Cpu186 = 0,
+ /* i286 or better required */
+ Cpu286,
+ /* i386 or better required */
+ Cpu386,
+ /* i486 or better required */
+ Cpu486,
+ /* i585 or better required */
+ Cpu586,
+ /* i686 or better required */
+ Cpu686,
+ /* CMOV Instruction support required */
+ CpuCMOV,
+ /* FXSR Instruction support required */
+ CpuFXSR,
+ /* CLFLUSH Instruction support required */
+ CpuClflush,
+ /* NOP Instruction support required */
+ CpuNop,
+ /* SYSCALL Instructions support required */
+ CpuSYSCALL,
+ /* Floating point support required */
+ Cpu8087,
+ /* i287 support required */
+ Cpu287,
+ /* i387 support required */
+ Cpu387,
+ /* i686 and floating point support required */
+ Cpu687,
+ /* SSE3 and floating point support required */
+ CpuFISTTP,
+ /* MMX support required */
+ CpuMMX,
+ /* SSE support required */
+ CpuSSE,
+ /* SSE2 support required */
+ CpuSSE2,
+ /* 3dnow! support required */
+ Cpu3dnow,
+ /* 3dnow! Extensions support required */
+ Cpu3dnowA,
+ /* SSE3 support required */
+ CpuSSE3,
+ /* VIA PadLock required */
+ CpuPadLock,
+ /* AMD Secure Virtual Machine Ext-s required */
+ CpuSVME,
+ /* VMX Instructions required */
+ CpuVMX,
+ /* SMX Instructions required */
+ CpuSMX,
+ /* SSSE3 support required */
+ CpuSSSE3,
+ /* SSE4a support required */
+ CpuSSE4a,
+ /* LZCNT support required */
+ CpuLZCNT,
+ /* POPCNT support required */
+ CpuPOPCNT,
+ /* SSE4.1 support required */
+ CpuSSE4_1,
+ /* SSE4.2 support required */
+ CpuSSE4_2,
+ /* AVX support required */
+ CpuAVX,
+ /* AVX2 support required */
+ CpuAVX2,
+ /* Intel AVX-512 Foundation Instructions support required */
+ CpuAVX512F,
+ /* Intel AVX-512 Conflict Detection Instructions support required */
+ CpuAVX512CD,
+ /* Intel AVX-512 Exponential and Reciprocal Instructions support
+ required */
+ CpuAVX512ER,
+ /* Intel AVX-512 Prefetch Instructions support required */
+ CpuAVX512PF,
+ /* Intel AVX-512 VL Instructions support required. */
+ CpuAVX512VL,
+ /* Intel AVX-512 DQ Instructions support required. */
+ CpuAVX512DQ,
+ /* Intel AVX-512 BW Instructions support required. */
+ CpuAVX512BW,
+ /* Intel L1OM support required */
+ CpuL1OM,
+ /* Intel K1OM support required */
+ CpuK1OM,
+ /* Intel IAMCU support required */
+ CpuIAMCU,
+ /* Xsave/xrstor New Instructions support required */
+ CpuXsave,
+ /* Xsaveopt New Instructions support required */
+ CpuXsaveopt,
+ /* AES support required */
+ CpuAES,
+ /* PCLMUL support required */
+ CpuPCLMUL,
+ /* FMA support required */
+ CpuFMA,
+ /* FMA4 support required */
+ CpuFMA4,
+ /* XOP support required */
+ CpuXOP,
+ /* LWP support required */
+ CpuLWP,
+ /* BMI support required */
+ CpuBMI,
+ /* TBM support required */
+ CpuTBM,
+ /* MOVBE Instruction support required */
+ CpuMovbe,
+ /* CMPXCHG16B instruction support required. */
+ CpuCX16,
+ /* EPT Instructions required */
+ CpuEPT,
+ /* RDTSCP Instruction support required */
+ CpuRdtscp,
+ /* FSGSBASE Instructions required */
+ CpuFSGSBase,
+ /* RDRND Instructions required */
+ CpuRdRnd,
+ /* F16C Instructions required */
+ CpuF16C,
+ /* Intel BMI2 support required */
+ CpuBMI2,
+ /* HLE support required */
+ CpuHLE,
+ /* RTM support required */
+ CpuRTM,
+ /* INVPCID Instructions required */
+ CpuINVPCID,
+ /* VMFUNC Instruction required */
+ CpuVMFUNC,
+ /* Intel MPX Instructions required */
+ CpuMPX,
+ /* 64bit support available, used by -march= in assembler. */
+ CpuLM,
+ /* RDRSEED instruction required. */
+ CpuRDSEED,
+ /* Multi-presisionn add-carry instructions are required. */
+ CpuADX,
+ /* Supports prefetchw and prefetch instructions. */
+ CpuPRFCHW,
+ /* SMAP instructions required. */
+ CpuSMAP,
+ /* SHA instructions required. */
+ CpuSHA,
+ /* CLFLUSHOPT instruction required */
+ CpuClflushOpt,
+ /* XSAVES/XRSTORS instruction required */
+ CpuXSAVES,
+ /* XSAVEC instruction required */
+ CpuXSAVEC,
+ /* PREFETCHWT1 instruction required */
+ CpuPREFETCHWT1,
+ /* SE1 instruction required */
+ CpuSE1,
+ /* CLWB instruction required */
+ CpuCLWB,
+ /* Intel AVX-512 IFMA Instructions support required. */
+ CpuAVX512IFMA,
+ /* Intel AVX-512 VBMI Instructions support required. */
+ CpuAVX512VBMI,
+ /* Intel AVX-512 4FMAPS Instructions support required. */
+ CpuAVX512_4FMAPS,
+ /* Intel AVX-512 4VNNIW Instructions support required. */
+ CpuAVX512_4VNNIW,
+ /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
+ CpuAVX512_VPOPCNTDQ,
+ /* Intel AVX-512 VBMI2 Instructions support required. */
+ CpuAVX512_VBMI2,
+ /* Intel AVX-512 VNNI Instructions support required. */
+ CpuAVX512_VNNI,
+ /* Intel AVX-512 BITALG Instructions support required. */
+ CpuAVX512_BITALG,
+ /* Intel AVX-512 BF16 Instructions support required. */
+ CpuAVX512_BF16,
+ /* Intel AVX-512 VP2INTERSECT Instructions support required. */
+ CpuAVX512_VP2INTERSECT,
+ /* mwaitx instruction required */
+ CpuMWAITX,
+ /* Clzero instruction required */
+ CpuCLZERO,
+ /* OSPKE instruction required */
+ CpuOSPKE,
+ /* RDPID instruction required */
+ CpuRDPID,
+ /* PTWRITE instruction required */
+ CpuPTWRITE,
+ /* CET instructions support required */
+ CpuIBT,
+ CpuSHSTK,
+ /* GFNI instructions required */
+ CpuGFNI,
+ /* VAES instructions required */
+ CpuVAES,
+ /* VPCLMULQDQ instructions required */
+ CpuVPCLMULQDQ,
+ /* WBNOINVD instructions required */
+ CpuWBNOINVD,
+ /* PCONFIG instructions required */
+ CpuPCONFIG,
+ /* WAITPKG instructions required */
+ CpuWAITPKG,
+ /* CLDEMOTE instruction required */
+ CpuCLDEMOTE,
+ /* MOVDIRI instruction support required */
+ CpuMOVDIRI,
+ /* MOVDIRR64B instruction required */
+ CpuMOVDIR64B,
+ /* ENQCMD instruction required */
+ CpuENQCMD,
+ /* SERIALIZE instruction required */
+ CpuSERIALIZE,
+ /* RDPRU instruction required */
+ CpuRDPRU,
+ /* MCOMMIT instruction required */
+ CpuMCOMMIT,
+ /* SEV-ES instruction(s) required */
+ CpuSEV_ES,
+ /* TSXLDTRK instruction required */
+ CpuTSXLDTRK,
+ /* 64bit support required */
+ Cpu64,
+ /* Not supported in the 64bit mode */
+ CpuNo64,
+ /* The last bitfield in i386_cpu_flags. */
+ CpuMax = CpuNo64
+};