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[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0fa7e85d873c9c5e6878b236a547996571e8fd6c..bfb3ce434e0e38f26b0952f5d48db445510822c2 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1,5 +1,5 @@
 /* Declarations for Intel 80386 opcode table
 /* Declarations for Intel 80386 opcode table

-   Copyright 2007, 2008, 2009, 2010
+   Copyright 2007, 2008, 2009, 2010, 2012

    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.


@@ -44,9 +44,11 @@ enum
   Cpu586,
   /* i686 or better required */
   Cpu686,
   Cpu586,
   /* i686 or better required */
   Cpu686,

-  /* CLFLUSH Instuction support required */
+  /* CLFLUSH Instruction support required */

   CpuClflush,
   CpuClflush,

-  /* SYSCALL Instuctions support required */
+  /* NOP Instruction support required */
+  CpuNop,
+  /* SYSCALL Instructions support required */

   CpuSYSCALL,
   /* Floating point support required */
   Cpu8087,
   CpuSYSCALL,
   /* Floating point support required */
   Cpu8087,


@@ -90,11 +92,15 @@ enum
   CpuSSE4_2,
   /* AVX support required */
   CpuAVX,
   CpuSSE4_2,
   /* AVX support required */
   CpuAVX,

+  /* AVX2 support required */
+  CpuAVX2,

   /* Intel L1OM support required */
   CpuL1OM,
   /* Intel L1OM support required */
   CpuL1OM,

-  /* Xsave/xrstor New Instuctions support required */
+  /* Intel K1OM support required */
+  CpuK1OM,
+  /* Xsave/xrstor New Instructions support required */

   CpuXsave,
   CpuXsave,

-  /* Xsaveopt New Instuctions support required */
+  /* Xsaveopt New Instructions support required */

   CpuXsaveopt,
   /* AES support required */
   CpuAES,
   CpuXsaveopt,
   /* AES support required */
   CpuAES,


@@ -108,20 +114,44 @@ enum
   CpuXOP,
   /* LWP support required */
   CpuLWP,
   CpuXOP,
   /* LWP support required */
   CpuLWP,

-  /* MOVBE Instuction support required */
+  /* BMI support required */
+  CpuBMI,
+  /* TBM support required */
+  CpuTBM,
+  /* MOVBE Instruction support required */

   CpuMovbe,
   CpuMovbe,

+  /* CMPXCHG16B instruction support required.  */
+  CpuCX16,

   /* EPT Instructions required */
   CpuEPT,
   /* EPT Instructions required */
   CpuEPT,

-  /* RDTSCP Instuction support required */
+  /* RDTSCP Instruction support required */

   CpuRdtscp,
   CpuRdtscp,

-  /* FSBSBASE Instructions required */
+  /* FSGSBASE Instructions required */

   CpuFSGSBase,
   /* RDRND Instructions required */
   CpuRdRnd,
   /* F16C Instructions required */
   CpuF16C,
   CpuFSGSBase,
   /* RDRND Instructions required */
   CpuRdRnd,
   /* F16C Instructions required */
   CpuF16C,

+  /* Intel BMI2 support required */
+  CpuBMI2,
+  /* LZCNT support required */
+  CpuLZCNT,
+  /* HLE support required */
+  CpuHLE,
+  /* RTM support required */
+  CpuRTM,
+  /* INVPCID Instructions required */
+  CpuINVPCID,
+  /* VMFUNC Instruction required */
+  CpuVMFUNC,

   /* 64bit support available, used by -march= in assembler.  */
   CpuLM,
   /* 64bit support available, used by -march= in assembler.  */
   CpuLM,

+  /* RDRSEED instruction required.  */
+  CpuRDSEED,
+  /* Multi-presisionn add-carry instructions are required.  */
+  CpuADX,
+  /* Supports prefetchw and prefetch instructions.  */
+  CpuPRFCHW,

   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */


@@ -152,6 +182,7 @@ typedef union i386_cpu_flags
       unsigned int cpui586:1;
       unsigned int cpui686:1;
       unsigned int cpuclflush:1;
       unsigned int cpui586:1;
       unsigned int cpui686:1;
       unsigned int cpuclflush:1;

+      unsigned int cpunop:1;

       unsigned int cpusyscall:1;
       unsigned int cpu8087:1;
       unsigned int cpu287:1;
       unsigned int cpusyscall:1;
       unsigned int cpu8087:1;
       unsigned int cpu287:1;


@@ -174,7 +205,9 @@ typedef union i386_cpu_flags
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpuavx:1;
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpuavx:1;

+      unsigned int cpuavx2:1;

       unsigned int cpul1om:1;
       unsigned int cpul1om:1;

+      unsigned int cpuk1om:1;

       unsigned int cpuxsave:1;
       unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;
       unsigned int cpuxsave:1;
       unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;


@@ -183,13 +216,25 @@ typedef union i386_cpu_flags
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;

+      unsigned int cpubmi:1;
+      unsigned int cputbm:1;

       unsigned int cpumovbe:1;
       unsigned int cpumovbe:1;

+      unsigned int cpucx16:1;

       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
       unsigned int cpufsgsbase:1;
       unsigned int cpurdrnd:1;
       unsigned int cpuf16c:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
       unsigned int cpufsgsbase:1;
       unsigned int cpurdrnd:1;
       unsigned int cpuf16c:1;

+      unsigned int cpubmi2:1;
+      unsigned int cpulzcnt:1;
+      unsigned int cpuhle:1;
+      unsigned int cpurtm:1;
+      unsigned int cpuinvpcid:1;
+      unsigned int cpuvmfunc:1;

       unsigned int cpulm:1;
       unsigned int cpulm:1;

+      unsigned int cpurdseed:1;
+      unsigned int cpuadx:1;
+      unsigned int cpuprfchw:1;

       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused


@@ -234,6 +279,8 @@ enum
   Size32,
   /* needs size prefix if in 64-bit mode */
   Size64,
   Size32,
   /* needs size prefix if in 64-bit mode */
   Size64,

+  /* check register size.  */
+  CheckRegSize,

   /* instruction ignores operand size prefix and in Intel mode ignores
      mnemonic size suffix check.  */
   IgnoreSize,
   /* instruction ignores operand size prefix and in Intel mode ignores
      mnemonic size suffix check.  */
   IgnoreSize,


@@ -264,6 +311,18 @@ enum
   FirstXmm0,
   /* An implicit xmm0 as the first operand */
   Implicit1stXmm0,
   FirstXmm0,
   /* An implicit xmm0 as the first operand */
   Implicit1stXmm0,

+  /* The HLE prefix is OK:
+     1. With a LOCK prefix.
+     2. With or without a LOCK prefix.
+     3. With a RELEASE (0xf3) prefix.
+   */
+#define HLEPrefixNone          0
+#define HLEPrefixLock          1
+#define HLEPrefixAny           2
+#define HLEPrefixRelease       3
+  HLEPrefixOk,
+  /* An instruction on which a "rep" prefix is acceptable.  */
+  RepPrefixOk,

   /* Convert to DWORD */
   ToDword,
   /* Convert to QWORD */
   /* Convert to DWORD */
   ToDword,
   /* Convert to QWORD */


@@ -293,12 +352,15 @@ enum
      0: VEX.vvvv must be 1111b.
      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
        the content of source registers will be preserved.
      0: VEX.vvvv must be 1111b.
      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
        the content of source registers will be preserved.

-       VEX.DDS.  The second register operand is encoded in VEX.vvvv 
+       VEX.DDS.  The second register operand is encoded in VEX.vvvv

        where the content of first source register will be overwritten
        by the result.
        where the content of first source register will be overwritten
        by the result.

-       For assembler, there are no difference between VEX.NDS and
-       VEX.DDS.
-     2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
+       VEX.NDD2.  The second destination register operand is encoded in
+       VEX.vvvv for instructions with 2 destination register operands.
+       For assembler, there are no difference between VEX.NDS, VEX.DDS
+       and VEX.NDD2.
+     2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
+     instructions with 1 destination register operand.

      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
        of the operands can access a memory location.
    */
      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
        of the operands can access a memory location.
    */


@@ -339,6 +401,13 @@ enum
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,

+  /* Instruction with vector SIB byte:
+       1: 128bit vector register.
+       2: 256bit vector register.
+   */
+#define VecSIB128      1
+#define VecSIB256      2
+  VecSIB,

   /* SSE to AVX support required */
   SSE2AVX,
   /* No AVX equivalent */
   /* SSE to AVX support required */
   SSE2AVX,
   /* No AVX equivalent */


@@ -372,6 +441,7 @@ typedef struct i386_opcode_modifier
   unsigned int size16:1;
   unsigned int size32:1;
   unsigned int size64:1;
   unsigned int size16:1;
   unsigned int size32:1;
   unsigned int size64:1;

+  unsigned int checkregsize:1;

   unsigned int ignoresize:1;
   unsigned int defaultsize:1;
   unsigned int no_bsuf:1;
   unsigned int ignoresize:1;
   unsigned int defaultsize:1;
   unsigned int no_bsuf:1;


@@ -386,6 +456,8 @@ typedef struct i386_opcode_modifier
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
   unsigned int implicit1stxmm0:1;
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
   unsigned int implicit1stxmm0:1;

+  unsigned int hleprefixok:2;
+  unsigned int repprefixok:1;

   unsigned int todword:1;
   unsigned int toqword:1;
   unsigned int addrprefixop0:1;
   unsigned int todword:1;
   unsigned int toqword:1;
   unsigned int addrprefixop0:1;


@@ -400,6 +472,7 @@ typedef struct i386_opcode_modifier
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
   unsigned int veximmext:1;
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
   unsigned int veximmext:1;

+  unsigned int vecsib:2;

   unsigned int sse2avx:1;
   unsigned int noavx:1;
   unsigned int oldgcc:1;
   unsigned int sse2avx:1;
   unsigned int noavx:1;
   unsigned int oldgcc:1;


@@ -604,7 +677,7 @@ typedef struct insn_template
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
      AMD 3DNow! instructions.
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
      AMD 3DNow! instructions.

-     If this template has no extension opcode (the usual case) use None 
+     If this template has no extension opcode (the usual case) use None

      Instructions */
   unsigned int extension_opcode;
 #define None 0xffff            /* If no extension_opcode is possible.  */
      Instructions */
   unsigned int extension_opcode;
 #define None 0xffff            /* If no extension_opcode is possible.  */