+mm0, RegMMX, 0, 0, 29, 41
+mm1, RegMMX, 0, 1, 30, 42
+mm2, RegMMX, 0, 2, 31, 43
+mm3, RegMMX, 0, 3, 32, 44
+mm4, RegMMX, 0, 4, 33, 45
+mm5, RegMMX, 0, 5, 34, 46
+mm6, RegMMX, 0, 6, 35, 47
+mm7, RegMMX, 0, 7, 36, 48
+xmm0, RegXMM, 0, 0, 21, 17
+xmm1, RegXMM, 0, 1, 22, 18
+xmm2, RegXMM, 0, 2, 23, 19
+xmm3, RegXMM, 0, 3, 24, 20
+xmm4, RegXMM, 0, 4, 25, 21
+xmm5, RegXMM, 0, 5, 26, 22
+xmm6, RegXMM, 0, 6, 27, 23
+xmm7, RegXMM, 0, 7, 28, 24
+xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
+xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
+xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
+xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
+xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
+xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
+xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
+xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
+xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67
+xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68
+xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69
+xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70
+xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71
+xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72
+xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73
+xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74
+xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75
+xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76
+xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77
+xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78
+xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79
+xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80
+xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81
+xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82
+// AVX registers.
+ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
+ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
+ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
+ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
+ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
+ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
+ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
+ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
+ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
+ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
+ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
+ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
+ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
+ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
+ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
+ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
+ymm16, RegYMM, RegVRex, 0, Dw2Inval, Dw2Inval
+ymm17, RegYMM, RegVRex, 1, Dw2Inval, Dw2Inval
+ymm18, RegYMM, RegVRex, 2, Dw2Inval, Dw2Inval
+ymm19, RegYMM, RegVRex, 3, Dw2Inval, Dw2Inval
+ymm20, RegYMM, RegVRex, 4, Dw2Inval, Dw2Inval
+ymm21, RegYMM, RegVRex, 5, Dw2Inval, Dw2Inval
+ymm22, RegYMM, RegVRex, 6, Dw2Inval, Dw2Inval
+ymm23, RegYMM, RegVRex, 7, Dw2Inval, Dw2Inval
+ymm24, RegYMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
+ymm25, RegYMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
+ymm26, RegYMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
+ymm27, RegYMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
+ymm28, RegYMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
+ymm29, RegYMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
+ymm30, RegYMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
+ymm31, RegYMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+// AVX512 registers.
+zmm0, RegZMM, 0, 0, Dw2Inval, Dw2Inval
+zmm1, RegZMM, 0, 1, Dw2Inval, Dw2Inval
+zmm2, RegZMM, 0, 2, Dw2Inval, Dw2Inval
+zmm3, RegZMM, 0, 3, Dw2Inval, Dw2Inval
+zmm4, RegZMM, 0, 4, Dw2Inval, Dw2Inval
+zmm5, RegZMM, 0, 5, Dw2Inval, Dw2Inval
+zmm6, RegZMM, 0, 6, Dw2Inval, Dw2Inval
+zmm7, RegZMM, 0, 7, Dw2Inval, Dw2Inval
+zmm8, RegZMM, RegRex, 0, Dw2Inval, Dw2Inval
+zmm9, RegZMM, RegRex, 1, Dw2Inval, Dw2Inval
+zmm10, RegZMM, RegRex, 2, Dw2Inval, Dw2Inval
+zmm11, RegZMM, RegRex, 3, Dw2Inval, Dw2Inval
+zmm12, RegZMM, RegRex, 4, Dw2Inval, Dw2Inval
+zmm13, RegZMM, RegRex, 5, Dw2Inval, Dw2Inval
+zmm14, RegZMM, RegRex, 6, Dw2Inval, Dw2Inval
+zmm15, RegZMM, RegRex, 7, Dw2Inval, Dw2Inval
+zmm16, RegZMM, RegVRex, 0, Dw2Inval, Dw2Inval
+zmm17, RegZMM, RegVRex, 1, Dw2Inval, Dw2Inval
+zmm18, RegZMM, RegVRex, 2, Dw2Inval, Dw2Inval
+zmm19, RegZMM, RegVRex, 3, Dw2Inval, Dw2Inval
+zmm20, RegZMM, RegVRex, 4, Dw2Inval, Dw2Inval
+zmm21, RegZMM, RegVRex, 5, Dw2Inval, Dw2Inval
+zmm22, RegZMM, RegVRex, 6, Dw2Inval, Dw2Inval
+zmm23, RegZMM, RegVRex, 7, Dw2Inval, Dw2Inval
+zmm24, RegZMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
+zmm25, RegZMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
+zmm26, RegZMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
+zmm27, RegZMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
+zmm28, RegZMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
+zmm29, RegZMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
+zmm30, RegZMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
+zmm31, RegZMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+// Bound registers for MPX
+bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
+bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
+bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
+bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
+// No type will make these registers rejected for all purposes except
+// for addressing. This saves creating one extra type for RIP/EIP.
+rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
+eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
+// No type will make these registers rejected for all purposes except
+// for addressing.
+riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
+eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval