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2005-11-02 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git]
/
opcodes
/
i860-dis.c
diff --git
a/opcodes/i860-dis.c
b/opcodes/i860-dis.c
index d969200a49d12097172520a1970c1b369a6e494b..9566bad4580bc5512f6e3d0da16b5683a2f86768 100644
(file)
--- a/
opcodes/i860-dis.c
+++ b/
opcodes/i860-dis.c
@@
-1,5
+1,5
@@
/* Disassembler for the i860.
/* Disassembler for the i860.
- Copyright 2000 Free Software Foundation, Inc.
+ Copyright 2000
, 2003
Free Software Foundation, Inc.
Contributed by Jason Eckhardt <jle@cygnus.com>.
Contributed by Jason Eckhardt <jle@cygnus.com>.
@@
-15,7
+15,7
@@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
-Foundation, Inc., 5
9 Temple Place - Suite 330, Boston, MA 02111-1307
, USA. */
+Foundation, Inc., 5
1 Franklin Street - Fifth Floor, Boston, MA 02110-1301
, USA. */
#include "dis-asm.h"
#include "opcode/i860.h"
#include "dis-asm.h"
#include "opcode/i860.h"
@@
-37,15
+37,13
@@
static const char *const frnames[] =
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
-/* Control/status register names (encoded as 0..5 in the instruction). */
+/* Control/status register names (encoded as 0..11 in the instruction).
+ Registers bear, ccr, p0, p1, p2 and p3 are XP only. */
static const char *const crnames[] =
static const char *const crnames[] =
- {"fir", "psr", "dirbase", "db", "fsr", "epsr", "", ""};
+ {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
+ "p0", "p1", "p2", "p3", "--", "--", "--", "--" };
-/* Prototypes. */
-static int sign_ext PARAMS((unsigned int, int));
-static void print_br_address PARAMS((disassemble_info *, bfd_vma, int));
-
/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \
/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \
@@
-58,9
+56,7
@@
static void print_br_address PARAMS((disassemble_info *, bfd_vma, int));
/* Sign extend N-bit number. */
static int
/* Sign extend N-bit number. */
static int
-sign_ext (x, n)
- unsigned int x;
- int n;
+sign_ext (unsigned int x, int n)
{
int t;
t = x >> (n - 1);
{
int t;
t = x >> (n - 1);
@@
-72,15
+68,12
@@
sign_ext (x, n)
/* Print a PC-relative branch offset. VAL is the sign extended value
from the branch instruction. */
static void
/* Print a PC-relative branch offset. VAL is the sign extended value
from the branch instruction. */
static void
-print_br_address (info, memaddr, val)
- disassemble_info *info;
- bfd_vma memaddr;
- int val;
+print_br_address (disassemble_info *info, bfd_vma memaddr, long val)
{
{
-
int adj =
memaddr + 4 + (val << 2);
+
long adj = (long)
memaddr + 4 + (val << 2);
- (*info->fprintf_func) (info->stream, "0x%08x", adj);
+ (*info->fprintf_func) (info->stream, "0x%08
l
x", adj);
/* Attempt to obtain a symbol for the target address. */
/* Attempt to obtain a symbol for the target address. */
@@
-94,9
+87,7
@@
print_br_address (info, memaddr, val)
/* Print one instruction. */
int
/* Print one instruction. */
int
-print_insn_i860 (memaddr, info)
- bfd_vma memaddr;
- disassemble_info *info;
+print_insn_i860 (bfd_vma memaddr, disassemble_info *info)
{
bfd_byte buff[4];
unsigned int insn, i;
{
bfd_byte buff[4];
unsigned int insn, i;
@@
-138,8
+129,11
@@
print_insn_i860 (memaddr, info)
const char *s;
int val;
const char *s;
int val;
- /* If this a flop and its dual bit is set, prefix with 'd.'. */
- if ((insn & 0xfc000000) == 0x48000000 && (insn & 0x200))
+ /* If this a flop (or a shrd) and its dual bit is set,
+ prefix with 'd.'. */
+ if (((insn & 0xfc000000) == 0x48000000
+ || (insn & 0xfc000000) == 0xb0000000)
+ && (insn & 0x200))
(*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
else
(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
(*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
else
(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
@@
-187,7
+181,7
@@
print_insn_i860 (memaddr, info)
/* Control register. */
case 'c':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
/* Control register. */
case 'c':
(*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
- crnames[(insn >> 21) & 0x
7
]);
+ crnames[(insn >> 21) & 0x
f
]);
break;
/* 16-bit immediate (sign extend, except for bitwise ops). */
break;
/* 16-bit immediate (sign extend, except for bitwise ops). */
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