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Change `function_symbols' to std::vector
[deliverable/binutils-gdb.git]
/
opcodes
/
m32c-dis.c
diff --git
a/opcodes/m32c-dis.c
b/opcodes/m32c-dis.c
index 43f93e2b2b87f879b507f8938471c4d0dc8f79fe..fc8ee0b3861b0eef8e478cb76a494eb153b3bdb4 100644
(file)
--- a/
opcodes/m32c-dis.c
+++ b/
opcodes/m32c-dis.c
@@
-1,23
+1,23
@@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
- Free Software Foundation, Inc.
+ Copyright (C) 1996-2018 Free Software Foundation, Inc.
- This file is part of
the GNU Binutils and GDB, the GNU debugger
.
+ This file is part of
libopcodes
.
- This
program
is free software; you can redistribute it and/or modify
+ This
library
is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version
2
, or (at your option)
+ the Free Software Foundation; either version
3
, or (at your option)
any later version.
any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-
GNU General Public
License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
@@
-29,7
+29,7
@@
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
-#include "dis
-asm
.h"
+#include "dis
assemble
.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
@@
-204,27
+204,27
@@
print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
int length ATTRIBUTE_UNUSED,
int push)
{
int length ATTRIBUTE_UNUSED,
int push)
{
- static char * m16c_register_names [] =
+ static char * m16c_register_names [] =
{
"r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
};
disassemble_info *info = dis_info;
int mask;
{
"r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb"
};
disassemble_info *info = dis_info;
int mask;
- int index = 0;
+ int
reg_
index = 0;
char* comma = "";
if (push)
mask = 0x80;
else
mask = 1;
char* comma = "";
if (push)
mask = 0x80;
else
mask = 1;
-
+
if (value & mask)
{
(*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]);
comma = ",";
}
if (value & mask)
{
(*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]);
comma = ",";
}
- for (
index = 1; index <= 7; ++
index)
+ for (
reg_index = 1; reg_index <= 7; ++reg_
index)
{
if (push)
mask >>= 1;
{
if (push)
mask >>= 1;
@@
-234,7
+234,7
@@
print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
if (value & mask)
{
(*info->fprintf_func) (info->stream, "%s%s", comma,
if (value & mask)
{
(*info->fprintf_func) (info->stream, "%s%s", comma,
- m16c_register_names [index]);
+ m16c_register_names [
reg_
index]);
comma = ",";
}
}
comma = ",";
}
}
@@
-321,6
+321,9
@@
m32c_cgen_print_operand (CGEN_CPU_DESC cd,
case M32C_OPERAND_BIT16RN :
print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0);
break;
case M32C_OPERAND_BIT16RN :
print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0);
break;
+ case M32C_OPERAND_BIT3_S :
+ print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case M32C_OPERAND_BIT32ANPREFIXED :
print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0);
break;
case M32C_OPERAND_BIT32ANPREFIXED :
print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0);
break;
@@
-450,6
+453,9
@@
m32c_cgen_print_operand (CGEN_CPU_DESC cd,
case M32C_OPERAND_DSP_40_U16 :
print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length);
break;
case M32C_OPERAND_DSP_40_U16 :
print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length);
break;
+ case M32C_OPERAND_DSP_40_U20 :
+ print_normal (cd, info, fields->f_dsp_40_u20, 0, pc, length);
+ break;
case M32C_OPERAND_DSP_40_U24 :
print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length);
break;
case M32C_OPERAND_DSP_40_U24 :
print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length);
break;
@@
-465,6
+471,9
@@
m32c_cgen_print_operand (CGEN_CPU_DESC cd,
case M32C_OPERAND_DSP_48_U16 :
print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length);
break;
case M32C_OPERAND_DSP_48_U16 :
print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length);
break;
+ case M32C_OPERAND_DSP_48_U20 :
+ print_normal (cd, info, fields->f_dsp_48_u20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case M32C_OPERAND_DSP_48_U24 :
print_normal (cd, info, fields->f_dsp_48_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case M32C_OPERAND_DSP_48_U24 :
print_normal (cd, info, fields->f_dsp_48_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
@@
-658,7
+667,7
@@
m32c_cgen_print_operand (CGEN_CPU_DESC cd,
print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_IMM_8_S4N :
print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_IMM_8_S4N :
- print_
normal
(cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ print_
signed4n
(cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case M32C_OPERAND_IMM_SH_12_S4 :
print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_12_s4, 0);
break;
case M32C_OPERAND_IMM_SH_12_S4 :
print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_12_s4, 0);
@@
-679,13
+688,13
@@
m32c_cgen_print_operand (CGEN_CPU_DESC cd,
print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_24_8 :
print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_24_8 :
- print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_
RELAX)|(1<<CGEN_OPERAND_
PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_32_8 :
break;
case M32C_OPERAND_LAB_32_8 :
- print_address (cd, info, fields->f_lab_32_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_32_8, 0|(1<<CGEN_OPERAND_
RELAX)|(1<<CGEN_OPERAND_
PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_40_8 :
break;
case M32C_OPERAND_LAB_40_8 :
- print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_
RELAX)|(1<<CGEN_OPERAND_
PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_5_3 :
print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_5_3 :
print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
@@
-694,7
+703,7
@@
m32c_cgen_print_operand (CGEN_CPU_DESC cd,
print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_24 :
print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_24 :
- print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+ print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_
RELAX)|(1<<CGEN_OPERAND_
ABS_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_8 :
print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case M32C_OPERAND_LAB_8_8 :
print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
@@
-879,13
+888,14
@@
m32c_cgen_print_operand (CGEN_CPU_DESC cd,
default :
/* xgettext:c-format */
default :
/* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
- opindex);
- abort ();
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while printing insn"),
+ opindex);
+ abort ();
}
}
}
}
-cgen_print_fn * const m32c_cgen_print_handlers[] =
+cgen_print_fn * const m32c_cgen_print_handlers[] =
{
print_insn_normal,
};
{
print_insn_normal,
};
@@
-913,10
+923,6
@@
print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
{
disassemble_info *info = (disassemble_info *) dis_info;
{
disassemble_info *info = (disassemble_info *) dis_info;
-#ifdef CGEN_PRINT_NORMAL
- CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
-#endif
-
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
@@
-938,10
+944,6
@@
print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
{
disassemble_info *info = (disassemble_info *) dis_info;
{
disassemble_info *info = (disassemble_info *) dis_info;
-#ifdef CGEN_PRINT_ADDRESS
- CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
-#endif
-
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* Nothing to do. */
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* Nothing to do. */
@@
-1083,7
+1085,7
@@
print_insn (CGEN_CPU_DESC cd,
int length;
unsigned long insn_value_cropped;
int length;
unsigned long insn_value_cropped;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! m32c_cgen_insn_supported (cd, insn))
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! m32c_cgen_insn_supported (cd, insn))
@@
-1101,7
+1103,7
@@
print_insn (CGEN_CPU_DESC cd,
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
@@
-1220,7
+1222,7
@@
print_insn_m32c (bfd_vma pc, disassemble_info *info)
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
-
+
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
@@
-1261,7
+1263,7
@@
print_insn_m32c (bfd_vma pc, disassemble_info *info)
break;
}
}
break;
}
}
- }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
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0.026402 seconds
and
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