+ (*info->fprintf_func) (info->stream, " -> ");
+
+ /* The "& 3" is to pass a consistent address.
+ Parallel insns arguably both begin on the word boundary.
+ Also, branch insns are calculated relative to the word boundary. */
+ if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
+ (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+
+ return (pc & 3) ? 2 : 4;
+}
+
+/* -- */
+
+void m32r_cgen_print_operand
+ (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
+
+/* Main entry point for printing operands.
+ XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+ of dis-asm.h on cgen.h.
+
+ This function is basically just a big switch statement. Earlier versions
+ used tables to look up the function to use, but
+ - if the table contains both assembler and disassembler functions then
+ the disassembler contains much of the assembler and vice-versa,
+ - there's a lot of inlining possibilities as things grow,
+ - using a switch statement avoids the function call overhead.
+
+ This function could be moved into `print_insn_normal', but keeping it
+ separate makes clear the interface between `print_insn_normal' and each of
+ the handlers. */
+
+void
+m32r_cgen_print_operand (CGEN_CPU_DESC cd,
+ int opindex,
+ void * xinfo,
+ CGEN_FIELDS *fields,
+ void const *attrs ATTRIBUTE_UNUSED,
+ bfd_vma pc,
+ int length)
+{
+ disassemble_info *info = (disassemble_info *) xinfo;
+
+ switch (opindex)
+ {
+ case M32R_OPERAND_ACC :
+ print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
+ break;
+ case M32R_OPERAND_ACCD :
+ print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
+ break;
+ case M32R_OPERAND_ACCS :
+ print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
+ break;
+ case M32R_OPERAND_DCR :
+ print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
+ break;
+ case M32R_OPERAND_DISP16 :
+ print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case M32R_OPERAND_DISP24 :
+ print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case M32R_OPERAND_DISP8 :
+ print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case M32R_OPERAND_DR :
+ print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
+ break;
+ case M32R_OPERAND_HASH :
+ print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case M32R_OPERAND_HI16 :
+ print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
+ break;
+ case M32R_OPERAND_IMM1 :
+ print_unsigned_with_hash_prefix (cd, info, fields->f_imm1, 0, pc, length);
+ break;
+ case M32R_OPERAND_SCR :
+ print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
+ break;
+ case M32R_OPERAND_SIMM16 :
+ print_signed_with_hash_prefix (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case M32R_OPERAND_SIMM8 :
+ print_signed_with_hash_prefix (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case M32R_OPERAND_SLO16 :
+ print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case M32R_OPERAND_SR :
+ print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
+ break;
+ case M32R_OPERAND_SRC1 :
+ print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
+ break;
+ case M32R_OPERAND_SRC2 :
+ print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
+ break;
+ case M32R_OPERAND_UIMM16 :
+ print_unsigned_with_hash_prefix (cd, info, fields->f_uimm16, 0, pc, length);
+ break;
+ case M32R_OPERAND_UIMM24 :
+ print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+ break;
+ case M32R_OPERAND_UIMM3 :
+ print_unsigned_with_hash_prefix (cd, info, fields->f_uimm3, 0, pc, length);
+ break;
+ case M32R_OPERAND_UIMM4 :
+ print_unsigned_with_hash_prefix (cd, info, fields->f_uimm4, 0, pc, length);
+ break;
+ case M32R_OPERAND_UIMM5 :
+ print_unsigned_with_hash_prefix (cd, info, fields->f_uimm5, 0, pc, length);
+ break;
+ case M32R_OPERAND_UIMM8 :
+ print_unsigned_with_hash_prefix (cd, info, fields->f_uimm8, 0, pc, length);
+ break;
+ case M32R_OPERAND_ULO16 :
+ print_normal (cd, info, fields->f_uimm16, 0, pc, length);
+ break;