+static const CGEN_IFMT ifmt_ldi16a ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_rac_d ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_rac_ds ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_rach_d ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_rach_ds ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_st_2 ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_st_d2 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_stb_2 ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_stb_d2 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sth_2 ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_sth_d2 ATTRIBUTE_UNUSED = {
+ 32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_push ATTRIBUTE_UNUSED = {
+ 16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
+};
+
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities. */
+
+#define A(a) (1 << CGEN_INSN_##a)
+#define OPERAND(op) M32R_OPERAND_##op
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table. */
+
+static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
+{
+/* bc $disp8 */
+ {
+ -1, "bc8r", "bc", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* bc $disp24 */
+ {
+ -1, "bc24r", "bc", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* bl $disp8 */
+ {
+ -1, "bl8r", "bl", 16,
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* bl $disp24 */
+ {
+ -1, "bl24r", "bl", 32,
+ { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* bcl $disp8 */
+ {
+ -1, "bcl8r", "bcl", 16,
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* bcl $disp24 */
+ {
+ -1, "bcl24r", "bcl", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* bnc $disp8 */
+ {
+ -1, "bnc8r", "bnc", 16,
+ { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* bnc $disp24 */
+ {
+ -1, "bnc24r", "bnc", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* bra $disp8 */
+ {
+ -1, "bra8r", "bra", 16,
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* bra $disp24 */
+ {
+ -1, "bra24r", "bra", 32,
+ { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* bncl $disp8 */
+ {
+ -1, "bncl8r", "bncl", 16,
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* bncl $disp24 */
+ {
+ -1, "bncl24r", "bncl", 32,
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* ld $dr,@($sr) */
+ {
+ -1, "ld-2", "ld", 16,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* ld $dr,@($sr,$slo16) */
+ {
+ -1, "ld-d2", "ld", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* ldb $dr,@($sr) */
+ {
+ -1, "ldb-2", "ldb", 16,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* ldb $dr,@($sr,$slo16) */
+ {
+ -1, "ldb-d2", "ldb", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* ldh $dr,@($sr) */
+ {
+ -1, "ldh-2", "ldh", 16,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* ldh $dr,@($sr,$slo16) */
+ {
+ -1, "ldh-d2", "ldh", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* ldub $dr,@($sr) */
+ {
+ -1, "ldub-2", "ldub", 16,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* ldub $dr,@($sr,$slo16) */
+ {
+ -1, "ldub-d2", "ldub", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* lduh $dr,@($sr) */
+ {
+ -1, "lduh-2", "lduh", 16,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* lduh $dr,@($sr,$slo16) */
+ {
+ -1, "lduh-d2", "lduh", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* pop $dr */
+ {
+ -1, "pop", "pop", 16,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* ldi $dr,$simm8 */
+ {
+ -1, "ldi8a", "ldi", 16,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+ },
+/* ldi $dr,$hash$slo16 */
+ {
+ -1, "ldi16a", "ldi", 32,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* rac $accd */
+ {
+ -1, "rac-d", "rac", 16,
+ { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
+ },
+/* rac $accd,$accs */
+ {
+ -1, "rac-ds", "rac", 16,
+ { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
+ },
+/* rach $accd */
+ {
+ -1, "rach-d", "rach", 16,
+ { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
+ },
+/* rach $accd,$accs */
+ {
+ -1, "rach-ds", "rach", 16,
+ { 0|A(ALIAS), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
+ },
+/* st $src1,@($src2) */
+ {
+ -1, "st-2", "st", 16,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* st $src1,@($src2,$slo16) */
+ {
+ -1, "st-d2", "st", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* stb $src1,@($src2) */
+ {
+ -1, "stb-2", "stb", 16,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* stb $src1,@($src2,$slo16) */
+ {
+ -1, "stb-d2", "stb", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* sth $src1,@($src2) */
+ {
+ -1, "sth-2", "sth", 16,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+/* sth $src1,@($src2,$slo16) */
+ {
+ -1, "sth-d2", "sth", 32,
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
+ },
+/* push $src1 */
+ {
+ -1, "push", "push", 16,
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
+ },
+};
+
+/* The macro instruction opcode table. */
+
+static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
+{
+/* bc $disp8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ & ifmt_bc8r, { 0x7c00 }
+ },
+/* bc $disp24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ & ifmt_bc24r, { 0xfc000000 }
+ },
+/* bl $disp8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ & ifmt_bl8r, { 0x7e00 }
+ },
+/* bl $disp24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ & ifmt_bl24r, { 0xfe000000 }
+ },
+/* bcl $disp8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ & ifmt_bcl8r, { 0x7800 }
+ },
+/* bcl $disp24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ & ifmt_bcl24r, { 0xf8000000 }
+ },
+/* bnc $disp8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ & ifmt_bnc8r, { 0x7d00 }
+ },
+/* bnc $disp24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ & ifmt_bnc24r, { 0xfd000000 }
+ },
+/* bra $disp8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ & ifmt_bra8r, { 0x7f00 }
+ },
+/* bra $disp24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ & ifmt_bra24r, { 0xff000000 }
+ },
+/* bncl $disp8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP8), 0 } },
+ & ifmt_bncl8r, { 0x7900 }
+ },
+/* bncl $disp24 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP24), 0 } },
+ & ifmt_bncl24r, { 0xf9000000 }
+ },
+/* ld $dr,@($sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ & ifmt_ld_2, { 0x20c0 }
+ },
+/* ld $dr,@($sr,$slo16) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ & ifmt_ld_d2, { 0xa0c00000 }
+ },
+/* ldb $dr,@($sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ & ifmt_ldb_2, { 0x2080 }
+ },
+/* ldb $dr,@($sr,$slo16) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ & ifmt_ldb_d2, { 0xa0800000 }
+ },
+/* ldh $dr,@($sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ & ifmt_ldh_2, { 0x20a0 }
+ },
+/* ldh $dr,@($sr,$slo16) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ & ifmt_ldh_d2, { 0xa0a00000 }
+ },
+/* ldub $dr,@($sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ & ifmt_ldub_2, { 0x2090 }
+ },
+/* ldub $dr,@($sr,$slo16) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ & ifmt_ldub_d2, { 0xa0900000 }
+ },
+/* lduh $dr,@($sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
+ & ifmt_lduh_2, { 0x20b0 }
+ },
+/* lduh $dr,@($sr,$slo16) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
+ & ifmt_lduh_d2, { 0xa0b00000 }
+ },
+/* pop $dr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), 0 } },
+ & ifmt_pop, { 0x20ef }
+ },
+/* ldi $dr,$simm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
+ & ifmt_ldi8a, { 0x6000 }
+ },
+/* ldi $dr,$hash$slo16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
+ & ifmt_ldi16a, { 0x90f00000 }
+ },
+/* rac $accd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ACCD), 0 } },
+ & ifmt_rac_d, { 0x5090 }
+ },
+/* rac $accd,$accs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
+ & ifmt_rac_ds, { 0x5090 }
+ },
+/* rach $accd */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ACCD), 0 } },
+ & ifmt_rach_d, { 0x5080 }
+ },
+/* rach $accd,$accs */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
+ & ifmt_rach_ds, { 0x5080 }
+ },
+/* st $src1,@($src2) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ & ifmt_st_2, { 0x2040 }
+ },
+/* st $src1,@($src2,$slo16) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ & ifmt_st_d2, { 0xa0400000 }
+ },
+/* stb $src1,@($src2) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ & ifmt_stb_2, { 0x2000 }
+ },
+/* stb $src1,@($src2,$slo16) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ & ifmt_stb_d2, { 0xa0000000 }
+ },
+/* sth $src1,@($src2) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
+ & ifmt_sth_2, { 0x2020 }
+ },
+/* sth $src1,@($src2,$slo16) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
+ & ifmt_sth_d2, { 0xa0200000 }
+ },
+/* push $src1 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), 0 } },
+ & ifmt_push, { 0x207f }
+ },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+#ifndef CGEN_ASM_HASH_P
+#define CGEN_ASM_HASH_P(insn) 1
+#endif
+
+#ifndef CGEN_DIS_HASH_P
+#define CGEN_DIS_HASH_P(insn) 1
+#endif
+
+/* Return non-zero if INSN is to be added to the hash table.
+ Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
+
+static int
+asm_hash_insn_p (insn)
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED;
+{
+ return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (insn)
+ const CGEN_INSN *insn;
+{
+ /* If building the hash table and the NO-DIS attribute is present,
+ ignore. */
+ if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
+ return 0;
+ return CGEN_DIS_HASH_P (insn);
+}
+
+#ifndef CGEN_ASM_HASH
+#define CGEN_ASM_HASH_SIZE 127
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+/* It doesn't make much sense to provide a default here,
+ but while this is under development we do.
+ BUFFER is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
+#endif
+
+/* The result is the hash value of the insn.
+ Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
+
+static unsigned int
+asm_hash_insn (mnem)
+ const char * mnem;
+{
+ return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the bytes of the insn, target order.
+ VALUE is the first base_insn_bitsize bits as an int in host order. */
+
+static unsigned int
+dis_hash_insn (buf, value)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value ATTRIBUTE_UNUSED;
+{
+ return CGEN_DIS_HASH (buf, value);
+}
+
+/* Set the recorded length of the insn in the CGEN_FIELDS struct. */
+
+static void
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
+{
+ CGEN_FIELDS_BITSIZE (fields) = size;
+}
+
+/* Function to call before using the operand instance table.
+ This plugs the opcode entries and macro instructions into the cpu table. */
+
+void
+m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd)
+{
+ int i;
+ int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
+ sizeof (m32r_cgen_macro_insn_table[0]));
+ const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
+ const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
+ CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
+ /* This test has been added to avoid a warning generated
+ if memset is called with a third argument of value zero. */
+ if (num_macros >= 1)
+ memset (insns, 0, num_macros * sizeof (CGEN_INSN));
+ for (i = 0; i < num_macros; ++i)
+ {
+ insns[i].base = &ib[i];
+ insns[i].opcode = &oc[i];
+ m32r_cgen_build_insn_regex (& insns[i]);
+ }
+ cd->macro_insn_table.init_entries = insns;
+ cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->macro_insn_table.num_init_entries = num_macros;
+
+ oc = & m32r_cgen_insn_opcode_table[0];
+ insns = (CGEN_INSN *) cd->insn_table.init_entries;
+ for (i = 0; i < MAX_INSNS; ++i)
+ {
+ insns[i].opcode = &oc[i];
+ m32r_cgen_build_insn_regex (& insns[i]);
+ }
+
+ cd->sizeof_fields = sizeof (CGEN_FIELDS);
+ cd->set_fields_bitsize = set_fields_bitsize;
+
+ cd->asm_hash_p = asm_hash_insn_p;
+ cd->asm_hash = asm_hash_insn;
+ cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+
+ cd->dis_hash_p = dis_hash_insn_p;
+ cd->dis_hash = dis_hash_insn;
+ cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+}