-/* Attributes. */
-
-static const CGEN_ATTR_ENTRY MACH_attr[] =
-{
- { "base", MACH_BASE },
- { "m32r", MACH_M32R },
-/* start-sanitize-m32rx */
- { "m32rx", MACH_M32RX },
-/* end-sanitize-m32rx */
- { "max", MACH_MAX },
- { 0, 0 }
-};
-
-/* start-sanitize-m32rx */
-static const CGEN_ATTR_ENTRY PIPE_attr[] =
-{
- { "NONE", PIPE_NONE },
- { "O", PIPE_O },
- { "S", PIPE_S },
- { "OS", PIPE_OS },
- { 0, 0 }
-};
-
-/* end-sanitize-m32rx */
-const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
-{
- { "MACH", & MACH_attr[0] },
- { "CACHE-ADDR", NULL },
- { "FUN-ACCESS", NULL },
- { "PC", NULL },
- { "PROFILE", NULL },
- { "SIGN-OPT", NULL },
- { "UNSIGNED", NULL },
- { 0, 0 }
-};
-
-const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
-{
- { "ABS-ADDR", NULL },
- { "HASH-PREFIX", NULL },
- { "NEGATIVE", NULL },
- { "PCREL-ADDR", NULL },
- { "RELAX", NULL },
- { "RELOC", NULL },
- { "SEM-ONLY", NULL },
- { "SIGN-OPT", NULL },
- { "UNSIGNED", NULL },
- { 0, 0 }
-};
-
-const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
-{
- { "MACH", & MACH_attr[0] },
-/* start-sanitize-m32rx */
- { "PIPE", & PIPE_attr[0] },
-/* end-sanitize-m32rx */
- { "ALIAS", NULL },
- { "COND-CTI", NULL },
- { "FILL-SLOT", NULL },
- { "NO-DIS", NULL },
- { "RELAX", NULL },
- { "RELAXABLE", NULL },
- { "SKIP-CTI", NULL },
- { "SPECIAL", NULL },
- { "UNCOND-CTI", NULL },
- { "VIRTUAL", NULL },
- { 0, 0 }
-};
-
-CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
-{
- { "fp", 13 },
- { "lr", 14 },
- { "sp", 15 },
- { "r0", 0 },
- { "r1", 1 },
- { "r2", 2 },
- { "r3", 3 },
- { "r4", 4 },
- { "r5", 5 },
- { "r6", 6 },
- { "r7", 7 },
- { "r8", 8 },
- { "r9", 9 },
- { "r10", 10 },
- { "r11", 11 },
- { "r12", 12 },
- { "r13", 13 },
- { "r14", 14 },
- { "r15", 15 }
-};
-
-CGEN_KEYWORD m32r_cgen_opval_h_gr =
-{
- & m32r_cgen_opval_h_gr_entries[0],
- 19
-};
-
-CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
-{
- { "psw", 0 },
- { "cbr", 1 },
- { "spi", 2 },
- { "spu", 3 },
- { "bpc", 6 },
- { "bbpsw", 8 },
- { "bbpc", 14 },
- { "cr0", 0 },
- { "cr1", 1 },
- { "cr2", 2 },
- { "cr3", 3 },
- { "cr4", 4 },
- { "cr5", 5 },
- { "cr6", 6 },
- { "cr7", 7 },
- { "cr8", 8 },
- { "cr9", 9 },
- { "cr10", 10 },
- { "cr11", 11 },
- { "cr12", 12 },
- { "cr13", 13 },
- { "cr14", 14 },
- { "cr15", 15 }
-};
-
-CGEN_KEYWORD m32r_cgen_opval_h_cr =
-{
- & m32r_cgen_opval_h_cr_entries[0],
- 23
-};
-
-/* start-sanitize-m32rx */
-CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
-{
- { "a0", 0 },
- { "a1", 1 }
-};
-
-CGEN_KEYWORD m32r_cgen_opval_h_accums =
-{
- & m32r_cgen_opval_h_accums_entries[0],
- 2
-};
-
-/* end-sanitize-m32rx */
-
-/* The hardware table. */
-
-#define HW_ENT(n) m32r_cgen_hw_entries[n]
-static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
-{
- { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
- { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_SIGN_OPT)|(1<<CGEN_HW_UNSIGNED), { (1<<MACH_BASE) } } },
- { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
- { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
- { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
-/* start-sanitize-m32rx */
- { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_M32RX) } } },
-/* end-sanitize-m32rx */
- { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_PSW, & HW_ENT (HW_H_PSW + 1), "h-psw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
- { HW_H_BPSW, & HW_ENT (HW_H_BPSW + 1), "h-bpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_BBPSW, & HW_ENT (HW_H_BBPSW + 1), "h-bbpsw", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { 0 }
-};
-
-/* The operand table. */
-
-#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
-#define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
-
-const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
-{
-/* pc: program counter */
- { "pc", & HW_ENT (HW_H_PC), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-/* sr: source register */
- { "sr", & HW_ENT (HW_H_GR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* dr: destination register */
- { "dr", & HW_ENT (HW_H_GR), 4, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* src1: source register 1 */
- { "src1", & HW_ENT (HW_H_GR), 4, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* src2: source register 2 */
- { "src2", & HW_ENT (HW_H_GR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* scr: source control register */
- { "scr", & HW_ENT (HW_H_CR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* dcr: destination control register */
- { "dcr", & HW_ENT (HW_H_CR), 4, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* simm8: 8 bit signed immediate */
- { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
-/* simm16: 16 bit signed immediate */
- { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
-/* uimm4: 4 bit trap number */
- { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* uimm5: 5 bit shift count */
- { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* uimm16: 16 bit unsigned immediate */
- { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* start-sanitize-m32rx */
-/* imm1: 1 bit immediate */
- { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* accd: accumulator destination register */
- { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* accs: accumulator source register */
- { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* acc: accumulator reg (d) */
- { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* end-sanitize-m32rx */
-/* hash: # prefix */
- { "hash", & HW_ENT (HW_H_SINT), 0, 0,
- { 0, 0, { 0 } } },
-/* hi16: high 16 bit immediate, sign optional */
- { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* slo16: 16 bit signed immediate, for low() */
- { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
- { 0, 0, { 0 } } },
-/* ulo16: 16 bit unsigned immediate, for low() */
- { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* uimm24: 24 bit address */
- { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* disp8: 8 bit displacement */
- { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
-/* disp16: 16 bit displacement */
- { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
-/* disp24: 24 bit displacement */
- { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
- { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
-/* condbit: condition bit */
- { "condbit", & HW_ENT (HW_H_COND), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-/* accum: accumulator */
- { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
-};
-
-/* Operand references. */
-
-#define INPUT CGEN_OPERAND_INSTANCE_INPUT
-#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
-
-static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { 0 }
-};
-
-static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { 0 }
-};
-
-/* start-sanitize-m32rx */
-static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { 0 }
-};
-
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { 0 }
-};