+
+static int
+msp430x_calla_instr (disassemble_info * info,
+ bfd_vma addr,
+ unsigned short insn,
+ char * op1,
+ char * comm1,
+ int * cycles)
+{
+ unsigned int ureg = insn & 0xf;
+ int reg = insn & 0xf;
+ int am = (insn & 0xf0) >> 4;
+ int cmd_len = 2;
+ unsigned short udst = 0;
+ short dst = 0;
+
+ switch (am)
+ {
+ case 4: /* CALLA Rdst */
+ *cycles = 1;
+ sprintf (op1, "r%d", reg);
+ break;
+
+ case 5: /* CALLA x(Rdst) */
+ *cycles = 3;
+ dst = msp430dis_opcode (addr + 2, info);
+ cmd_len += 2;
+ sprintf (op1, "%d(r%d)", dst, reg);
+ if (reg == 0)
+ sprintf (comm1, "PC rel. 0x%05lx", (long) (addr + 2 + dst));
+ else
+ sprintf (comm1, "0x%05x", dst);
+ break;
+
+ case 6: /* CALLA @Rdst */
+ *cycles = 2;
+ sprintf (op1, "@r%d", reg);
+ break;
+
+ case 7: /* CALLA @Rdst+ */
+ *cycles = 2;
+ sprintf (op1, "@r%d+", reg);
+ break;
+
+ case 8: /* CALLA &abs20 */
+ udst = msp430dis_opcode (addr + 2, info);
+ cmd_len += 2;
+ *cycles = 4;
+ sprintf (op1, "&%d", (ureg << 16) + udst);
+ sprintf (comm1, "0x%05x", (ureg << 16) + udst);
+ break;
+
+ case 9: /* CALLA pcrel-sym */
+ dst = msp430dis_opcode (addr + 2, info);
+ cmd_len += 2;
+ *cycles = 4;
+ sprintf (op1, "%d(PC)", (reg << 16) + dst);
+ sprintf (comm1, "PC rel. 0x%05lx",
+ (long) (addr + 2 + dst + (reg << 16)));
+ break;
+
+ case 11: /* CALLA #imm20 */
+ udst = msp430dis_opcode (addr + 2, info);
+ cmd_len += 2;
+ *cycles = 4;
+ sprintf (op1, "#%d", (ureg << 16) + udst);
+ sprintf (comm1, "0x%05x", (ureg << 16) + udst);
+ break;
+
+ default:
+ strcpy (comm1, _("unercognised CALLA addressing mode"));
+ return -1;
+ }
+
+ return cmd_len;
+}
+
+int
+print_insn_msp430 (bfd_vma addr, disassemble_info *info)
+{
+ void *stream = info->stream;
+ fprintf_ftype prin = info->fprintf_func;
+ struct msp430_opcode_s *opcode;
+ char op1[32], op2[32], comm1[64], comm2[64];
+ int cmd_len = 0;
+ unsigned short insn;
+ int cycles = 0;
+ char *bc = "";
+ unsigned short extension_word = 0;
+
+ insn = msp430dis_opcode (addr, info);
+ if (insn == (unsigned short) -1)
+ {
+ prin (stream, ".word 0xffff; ????");
+ return 2;
+ }
+
+ if (((int) addr & 0xffff) > 0xffdf)
+ {
+ (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);
+ return 2;
+ }
+
+ *comm1 = 0;
+ *comm2 = 0;
+
+ /* Check for an extension word. */
+ if ((insn & 0xf800) == 0x1800)
+ {
+ extension_word = insn;
+ addr += 2;
+ insn = msp430dis_opcode (addr, info);
+ if (insn == (unsigned short) -1)
+ {
+ prin (stream, ".word 0x%04x, 0xffff; ????",
+ extension_word);
+ return 4;
+ }
+ }
+
+ for (opcode = msp430_opcodes; opcode->name; opcode++)
+ {
+ if ((insn & opcode->bin_mask) == opcode->bin_opcode
+ && opcode->bin_opcode != 0x9300)
+ {
+ *op1 = 0;
+ *op2 = 0;
+ *comm1 = 0;
+ *comm2 = 0;
+
+ /* r0 as destination. Ad should be zero. */
+ if (opcode->insn_opnumb == 3
+ && (insn & 0x000f) == 0
+ && (insn & 0x0080) == 0)
+ {
+ cmd_len +=
+ msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
+ &cycles);
+ if (cmd_len)
+ break;
+ }
+
+ switch (opcode->insn_opnumb)
+ {
+ int n;
+ int reg;
+
+ case 4:
+ cmd_len += msp430x_calla_instr (info, addr, insn,
+ op1, comm1, & cycles);
+ break;
+
+ case 5: /* PUSHM/POPM */
+ n = (insn & 0xf0) >> 4;
+ reg = (insn & 0xf);
+
+ sprintf (op1, "#%d", n + 1);
+ if (opcode->bin_opcode == 0x1400)
+ /* PUSHM */
+ sprintf (op2, "r%d", reg);
+ else
+ /* POPM */
+ sprintf (op2, "r%d", reg + n);
+ if (insn & 0x100)
+ sprintf (comm1, "16-bit words");
+ else
+ {
+ sprintf (comm1, "20-bit words");
+ bc =".a";
+ }
+
+ cycles = 2; /*FIXME*/
+ cmd_len = 2;
+ break;
+
+ case 6: /* RRAM, RRCM, RRUM, RLAM. */
+ n = ((insn >> 10) & 0x3) + 1;
+ reg = (insn & 0xf);
+ if ((insn & 0x10) == 0)
+ bc =".a";
+ sprintf (op1, "#%d", n);
+ sprintf (op2, "r%d", reg);
+ cycles = 2; /*FIXME*/
+ cmd_len = 2;
+ break;
+
+ case 8: /* ADDA, CMPA, SUBA. */
+ reg = (insn & 0xf);
+ n = (insn >> 8) & 0xf;
+ if (insn & 0x40)
+ {
+ sprintf (op1, "r%d", n);
+ cmd_len = 2;
+ }
+ else
+ {
+ n <<= 16;
+ n |= msp430dis_opcode (addr + 2, info);
+ sprintf (op1, "#%d", n);
+ if (n > 9 || n < 0)
+ sprintf (comm1, "0x%05x", n);
+ cmd_len = 4;
+ }
+ sprintf (op2, "r%d", reg);
+ cycles = 2; /*FIXME*/
+ break;
+
+ case 9: /* MOVA */
+ reg = (insn & 0xf);
+ n = (insn >> 8) & 0xf;
+ switch ((insn >> 4) & 0xf)
+ {
+ case 0: /* MOVA @Rsrc, Rdst */
+ cmd_len = 2;
+ sprintf (op1, "@r%d", n);
+ if (strcmp (opcode->name, "bra") != 0)
+ sprintf (op2, "r%d", reg);
+ break;
+
+ case 1: /* MOVA @Rsrc+, Rdst */
+ cmd_len = 2;
+ if (strcmp (opcode->name, "reta") != 0)
+ {
+ sprintf (op1, "@r%d+", n);
+ if (strcmp (opcode->name, "bra") != 0)
+ sprintf (op2, "r%d", reg);
+ }
+ break;
+
+ case 2: /* MOVA &abs20, Rdst */
+ cmd_len = 4;
+ n <<= 16;
+ n |= msp430dis_opcode (addr + 2, info);
+ sprintf (op1, "&%d", n);
+ if (n > 9 || n < 0)
+ sprintf (comm1, "0x%05x", n);
+ if (strcmp (opcode->name, "bra") != 0)
+ sprintf (op2, "r%d", reg);
+ break;
+
+ case 3: /* MOVA x(Rsrc), Rdst */
+ cmd_len = 4;
+ if (strcmp (opcode->name, "bra") != 0)
+ sprintf (op2, "r%d", reg);
+ reg = n;
+ n = msp430dis_opcode (addr + 2, info);
+ if (n & 0x8000)
+ n |= -1 << 16;
+ sprintf (op1, "%d(r%d)", n, reg);
+ if (n > 9 || n < 0)
+ {
+ if (reg == 0)
+ sprintf (comm1, "PC rel. 0x%05lx",
+ (long) (addr + 2 + n));
+ else
+ sprintf (comm1, "0x%05x", n);
+ }
+ break;
+
+ case 6: /* MOVA Rsrc, &abs20 */
+ cmd_len = 4;
+ reg <<= 16;
+ reg |= msp430dis_opcode (addr + 2, info);
+ sprintf (op1, "r%d", n);
+ sprintf (op2, "&%d", reg);
+ if (reg > 9 || reg < 0)
+ sprintf (comm2, "0x%05x", reg);
+ break;
+
+ case 7: /* MOVA Rsrc, x(Rdst) */
+ cmd_len = 4;
+ sprintf (op1, "r%d", n);
+ n = msp430dis_opcode (addr + 2, info);
+ if (n & 0x8000)
+ n |= -1 << 16;
+ sprintf (op2, "%d(r%d)", n, reg);
+ if (n > 9 || n < 0)
+ {
+ if (reg == 0)
+ sprintf (comm2, "PC rel. 0x%05lx",
+ (long) (addr + 2 + n));
+ else
+ sprintf (comm2, "0x%05x", n);
+ }
+ break;
+
+ case 8: /* MOVA #imm20, Rdst */
+ cmd_len = 4;
+ n <<= 16;
+ n |= msp430dis_opcode (addr + 2, info);
+ if (n & 0x80000)
+ n |= -1 << 20;
+ sprintf (op1, "#%d", n);
+ if (n > 9 || n < 0)
+ sprintf (comm1, "0x%05x", n);
+ if (strcmp (opcode->name, "bra") != 0)
+ sprintf (op2, "r%d", reg);
+ break;
+
+ case 12: /* MOVA Rsrc, Rdst */
+ cmd_len = 2;
+ sprintf (op1, "r%d", n);
+ if (strcmp (opcode->name, "bra") != 0)
+ sprintf (op2, "r%d", reg);
+ break;
+
+ default:
+ break;
+ }
+ cycles = 2; /* FIXME */
+ break;
+ }
+
+ if (cmd_len)
+ break;
+
+ switch (opcode->insn_opnumb)
+ {
+ case 0:
+ cmd_len += msp430_nooperands (opcode, addr, insn, comm1, &cycles);
+ break;
+ case 2:
+ cmd_len +=
+ msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
+ comm1, comm2,
+ extension_word,
+ &cycles);
+ if (insn & BYTE_OPERATION)
+ {
+ if (extension_word != 0 && ((extension_word & BYTE_OPERATION) == 0))
+ bc = ".a";
+ else
+ bc = ".b";
+ }
+ else if (extension_word)
+ {
+ if (extension_word & (1 << 6))
+ bc = ".w";
+ else
+ {
+ bc = ".?";
+ sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
+ }
+ }
+
+ break;
+ case 1:
+ cmd_len +=
+ msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
+ extension_word,
+ &cycles);
+ if (extension_word
+ && (strcmp (opcode->name, "swpb") == 0
+ || strcmp (opcode->name, "sxt") == 0))
+ {
+ if (insn & BYTE_OPERATION)
+ {
+ bc = ".?";
+ sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
+ }
+ else if (extension_word & BYTE_OPERATION)
+ bc = ".w";
+ else
+ bc = ".a";
+ }
+ else if (insn & BYTE_OPERATION && opcode->fmt != 3)
+ {
+ if (extension_word != 0 && ((extension_word & BYTE_OPERATION) == 0))
+ bc = ".a";
+ else
+ bc = ".b";
+ }
+ else if (extension_word)
+ {
+ if (extension_word & (1 << 6))
+ bc = ".w";
+ else
+ {
+ bc = ".?";
+ sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
+ }
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (cmd_len)
+ break;
+ }
+
+ if (cmd_len < 1)
+ {
+ /* Unknown opcode, or invalid combination of operands. */
+ if (extension_word)
+ {
+ prin (stream, ".word 0x%04x, 0x%04x; ????", extension_word, PS (insn));
+ if (*comm1)
+ prin (stream, "\t %s", comm1);
+ return 4;
+ }
+ (*prin) (stream, ".word 0x%04x; ????", PS (insn));
+ return 2;
+ }
+
+ /* Display the repeat count (if set) for extended register mode. */
+ if (cmd_len == 2 && ((extension_word & 0xf) != 0))
+ {
+ if (extension_word & (1 << 7))
+ prin (stream, "rpt r%d { ", extension_word & 0xf);
+ else
+ prin (stream, "rpt #%d { ", (extension_word & 0xf) + 1);
+ }
+
+ if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
+ (*prin) (stream, "%sx%s", opcode->name, bc);
+ else
+ (*prin) (stream, "%s%s", opcode->name, bc);
+
+ if (*op1)
+ (*prin) (stream, "\t%s", op1);
+ if (*op2)
+ (*prin) (stream, ",");
+
+ if (strlen (op1) < 7)
+ (*prin) (stream, "\t");
+ if (!strlen (op1))
+ (*prin) (stream, "\t");
+
+ if (*op2)
+ (*prin) (stream, "%s", op2);
+ if (strlen (op2) < 8)
+ (*prin) (stream, "\t");
+
+ if (*comm1 || *comm2)
+ (*prin) (stream, ";");
+ else if (cycles)
+ {
+ if (*op2)
+ (*prin) (stream, ";");
+ else
+ {
+ if (strlen (op1) < 7)
+ (*prin) (stream, ";");
+ else
+ (*prin) (stream, "\t;");
+ }
+ }
+ if (*comm1)
+ (*prin) (stream, "%s", comm1);
+ if (*comm1 && *comm2)
+ (*prin) (stream, ",");
+ if (*comm2)
+ (*prin) (stream, " %s", comm2);
+
+ if (extension_word)
+ cmd_len += 2;
+
+ return cmd_len;
+}