*** empty log message ***

[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 204c16b371e1888767fefaa7be31eca7cc409374..9936f3ead44d57b374589af151cfe08ccd37a7ba 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1,24 +1,24 @@
 /* ppc-opc.c -- PowerPC opcode list
 /* ppc-opc.c -- PowerPC opcode list

-   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004

    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 

-This file is part of GDB, GAS, and the GNU binutils.
+   This file is part of GDB, GAS, and the GNU binutils.

 
 

-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-2, or (at your option) any later version.
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.

 
 

-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.

 
 

-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */

 
 #include <stdio.h>
 #include "sysdep.h"
 
 #include <stdio.h>
 #include "sysdep.h"


@@ -38,102 +38,60 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 \f
 /* Local insertion and extraction functions.  */
 
 \f
 /* Local insertion and extraction functions.  */
 

-static unsigned long insert_bat
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bat
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bba
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bba
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bd
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bd
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bdm
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bdm
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bdp
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bdp
-  PARAMS ((unsigned long, int, int *));
-static int valid_bo
-  PARAMS ((long, int));
-static unsigned long insert_bo
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bo
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_boe
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_boe
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ds
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_ds
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_de
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_de
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_des
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_des
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_li
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_li
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_mbe
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_mbe
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_mb6
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_mb6
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_nb
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_nb
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_nsi
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_nsi
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ral
-  PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_ram
-  PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_ras
-  PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_rbs
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_rbs
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_sh6
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_sh6
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_spr
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_spr
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_tbr
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_tbr
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ev2
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_ev2
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ev4
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_ev4
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ev8
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_ev8
-  PARAMS ((unsigned long, int, int *));
+static unsigned long insert_bat (unsigned long, long, int, const char **);
+static long extract_bat (unsigned long, int, int *);
+static unsigned long insert_bba (unsigned long, long, int, const char **);
+static long extract_bba (unsigned long, int, int *);
+static unsigned long insert_bd (unsigned long, long, int, const char **);
+static long extract_bd (unsigned long, int, int *);
+static unsigned long insert_bdm (unsigned long, long, int, const char **);
+static long extract_bdm (unsigned long, int, int *);
+static unsigned long insert_bdp (unsigned long, long, int, const char **);
+static long extract_bdp (unsigned long, int, int *);
+static unsigned long insert_bo (unsigned long, long, int, const char **);
+static long extract_bo (unsigned long, int, int *);
+static unsigned long insert_boe (unsigned long, long, int, const char **);
+static long extract_boe (unsigned long, int, int *);
+static unsigned long insert_dq (unsigned long, long, int, const char **);
+static long extract_dq (unsigned long, int, int *);
+static unsigned long insert_ds (unsigned long, long, int, const char **);
+static long extract_ds (unsigned long, int, int *);
+static unsigned long insert_de (unsigned long, long, int, const char **);
+static long extract_de (unsigned long, int, int *);
+static unsigned long insert_des (unsigned long, long, int, const char **);
+static long extract_des (unsigned long, int, int *);
+static unsigned long insert_fxm (unsigned long, long, int, const char **);
+static long extract_fxm (unsigned long, int, int *);
+static unsigned long insert_li (unsigned long, long, int, const char **);
+static long extract_li (unsigned long, int, int *);
+static unsigned long insert_mbe (unsigned long, long, int, const char **);
+static long extract_mbe (unsigned long, int, int *);
+static unsigned long insert_mb6 (unsigned long, long, int, const char **);
+static long extract_mb6 (unsigned long, int, int *);
+static unsigned long insert_nb (unsigned long, long, int, const char **);
+static long extract_nb (unsigned long, int, int *);
+static unsigned long insert_nsi (unsigned long, long, int, const char **);
+static long extract_nsi (unsigned long, int, int *);
+static unsigned long insert_ral (unsigned long, long, int, const char **);
+static unsigned long insert_ram (unsigned long, long, int, const char **);
+static unsigned long insert_raq (unsigned long, long, int, const char **);
+static unsigned long insert_ras (unsigned long, long, int, const char **);
+static unsigned long insert_rbs (unsigned long, long, int, const char **);
+static long extract_rbs (unsigned long, int, int *);
+static unsigned long insert_rsq (unsigned long, long, int, const char **);
+static unsigned long insert_rtq (unsigned long, long, int, const char **);
+static unsigned long insert_sh6 (unsigned long, long, int, const char **);
+static long extract_sh6 (unsigned long, int, int *);
+static unsigned long insert_spr (unsigned long, long, int, const char **);
+static long extract_spr (unsigned long, int, int *);
+static unsigned long insert_tbr (unsigned long, long, int, const char **);
+static long extract_tbr (unsigned long, int, int *);
+static unsigned long insert_ev2 (unsigned long, long, int, const char **);
+static long extract_ev2 (unsigned long, int, int *);
+static unsigned long insert_ev4 (unsigned long, long, int, const char **);
+static long extract_ev4 (unsigned long, int, int *);
+static unsigned long insert_ev8 (unsigned long, long, int, const char **);
+static long extract_ev8 (unsigned long, int, int *);

 \f
 /* The operands table.
 
 \f
 /* The operands table.
 


@@ -236,8 +194,11 @@ const struct powerpc_operand powerpc_operands[] =
 #define BOE BO + 1
   { 5, 21, insert_boe, extract_boe, 0 },
 
 #define BOE BO + 1
   { 5, 21, insert_boe, extract_boe, 0 },
 

+#define BH BOE + 1
+  { 2, 11, 0, 0, PPC_OPERAND_OPTIONAL },
+

   /* The BT field in an X or XL form instruction.  */
   /* The BT field in an X or XL form instruction.  */

-#define BT BOE + 1
+#define BT BH + 1

   { 5, 21, 0, 0, PPC_OPERAND_CR },
 
   /* The condition register number portion of the BI field in a B form
   { 5, 21, 0, 0, PPC_OPERAND_CR },
 
   /* The condition register number portion of the BI field in a B form


@@ -279,9 +240,15 @@ const struct powerpc_operand powerpc_operands[] =
 #define DES DE + 1
   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 
 #define DES DE + 1
   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 

+  /* The DQ field in a DQ form instruction.  This is like D, but the
+     lower four bits are forced to zero. */
+#define DQ DES + 1
+  { 16, 0, insert_dq, extract_dq,
+      PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
+

   /* The DS field in a DS form instruction.  This is like D, but the
      lower two bits are forced to zero.  */
   /* The DS field in a DS form instruction.  This is like D, but the
      lower two bits are forced to zero.  */

-#define DS DES + 1
+#define DS DQ + 1

   { 16, 0, insert_ds, extract_ds,
       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 
   { 16, 0, insert_ds, extract_ds,
       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 


@@ -325,10 +292,14 @@ const struct powerpc_operand powerpc_operands[] =
   /* The FXM field in an XFX instruction.  */
 #define FXM FRS + 1
 #define FXM_MASK (0xff << 12)
   /* The FXM field in an XFX instruction.  */
 #define FXM FRS + 1
 #define FXM_MASK (0xff << 12)

-  { 8, 12, 0, 0, 0 },
+  { 8, 12, insert_fxm, extract_fxm, 0 },
+
+  /* Power4 version for mfcr.  */
+#define FXM4 FXM + 1
+  { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },

 
   /* The L field in a D or X form instruction.  */
 
   /* The L field in a D or X form instruction.  */

-#define L FXM + 1
+#define L FXM4 + 1

   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 
   /* The LEV field in a POWER SC form instruction.  */
   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 
   /* The LEV field in a POWER SC form instruction.  */


@@ -376,7 +347,7 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The MO field in an mbar instruction.  */
 #define MO MB6 + 1
 
   /* The MO field in an mbar instruction.  */
 #define MO MB6 + 1

-  { 5, 21, 0, 0, 0 },
+  { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },

 
   /* The NB field in an X form instruction.  The value 32 is stored as
      0.  */
 
   /* The NB field in an X form instruction.  The value 32 is stored as
      0.  */


@@ -389,30 +360,43 @@ const struct powerpc_operand powerpc_operands[] =
   { 16, 0, insert_nsi, extract_nsi,
       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 
   { 16, 0, insert_nsi, extract_nsi,
       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 

-  /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
+  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */

 #define RA NSI + 1
 #define RA_MASK (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 
 #define RA NSI + 1
 #define RA_MASK (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 

+  /* As above, but 0 in the RA field means zero, not r0.  */
+#define RA0 RA + 1
+  { 5, 16, 0, 0, PPC_OPERAND_GPR_0 },
+
+  /* The RA field in the DQ form lq instruction, which has special
+     value restrictions.  */
+#define RAQ RA0 + 1
+  { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 },
+

   /* The RA field in a D or X form instruction which is an updating
      load, which means that the RA field may not be zero and may not
      equal the RT field.  */
   /* The RA field in a D or X form instruction which is an updating
      load, which means that the RA field may not be zero and may not
      equal the RT field.  */

-#define RAL RA + 1
-  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
+#define RAL RAQ + 1
+  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 },

 
   /* The RA field in an lmw instruction, which has special value
      restrictions.  */
 #define RAM RAL + 1
 
   /* The RA field in an lmw instruction, which has special value
      restrictions.  */
 #define RAM RAL + 1

-  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 },

 
   /* The RA field in a D or X form instruction which is an updating
      store or an updating floating point load, which means that the RA
      field may not be zero.  */
 #define RAS RAM + 1
 
   /* The RA field in a D or X form instruction which is an updating
      store or an updating floating point load, which means that the RA
      field may not be zero.  */
 #define RAS RAM + 1

-  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 },
+
+  /* The RA field of the tlbwe instruction, which is optional.  */
+#define RAOPT RAS + 1
+  { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },

 
   /* The RB field in an X, XO, M, or MDS form instruction.  */
 
   /* The RB field in an X, XO, M, or MDS form instruction.  */

-#define RB RAS + 1
+#define RB RAOPT + 1

 #define RB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 
 #define RB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_GPR },
 


@@ -430,8 +414,22 @@ const struct powerpc_operand powerpc_operands[] =
 #define RT_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 
 #define RT_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 

+  /* The RS field of the DS form stq instruction, which has special
+     value restrictions.  */
+#define RSQ RS + 1
+  { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 },
+
+  /* The RT field of the DQ form lq instruction, which has special
+     value restrictions.  */
+#define RTQ RSQ + 1
+  { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 },
+
+  /* The RS field of the tlbwe instruction, which is optional.  */
+#define RSO RTQ + 1
+  { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
+

   /* The SH field in an X or M form instruction.  */
   /* The SH field in an X or M form instruction.  */

-#define SH RS + 1
+#define SH RSO + 1

 #define SH_MASK (0x1f << 11)
   { 5, 11, 0, 0, 0 },
 
 #define SH_MASK (0x1f << 11)
   { 5, 11, 0, 0, 0 },
 


@@ -440,8 +438,12 @@ const struct powerpc_operand powerpc_operands[] =
 #define SH6_MASK ((0x1f << 11) | (1 << 1))
   { 6, 1, insert_sh6, extract_sh6, 0 },
 
 #define SH6_MASK ((0x1f << 11) | (1 << 1))
   { 6, 1, insert_sh6, extract_sh6, 0 },
 

+  /* The SH field of the tlbwe instruction, which is optional.  */
+#define SHO SH6 + 1
+  { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
+

   /* The SI field in a D form instruction.  */
   /* The SI field in a D form instruction.  */

-#define SI SH6 + 1
+#define SI SHO + 1

   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 
   /* The SI field in a D form instruction when we accept a wide range
   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
 
   /* The SI field in a D form instruction when we accept a wide range


@@ -497,52 +499,52 @@ const struct powerpc_operand powerpc_operands[] =
 #define UI U + 1
   { 16, 0, 0, 0, 0 },
 
 #define UI U + 1
   { 16, 0, 0, 0, 0 },
 

-  /* The VA field in a VA, VX or VXR form instruction. */
+  /* The VA field in a VA, VX or VXR form instruction.  */

 #define VA UI + 1
 #define VA_MASK        (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_VR },
 
 #define VA UI + 1
 #define VA_MASK        (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_VR },
 

-  /* The VB field in a VA, VX or VXR form instruction. */
+  /* The VB field in a VA, VX or VXR form instruction.  */

 #define VB VA + 1
 #define VB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_VR },
 
 #define VB VA + 1
 #define VB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_VR },
 

-  /* The VC field in a VA form instruction. */
+  /* The VC field in a VA form instruction.  */

 #define VC VB + 1
 #define VC_MASK (0x1f << 6)
   { 5, 6, 0, 0, PPC_OPERAND_VR },
 
 #define VC VB + 1
 #define VC_MASK (0x1f << 6)
   { 5, 6, 0, 0, PPC_OPERAND_VR },
 

-  /* The VD or VS field in a VA, VX, VXR or X form instruction. */
+  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */

 #define VD VC + 1
 #define VS VD
 #define VD_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_VR },
 
 #define VD VC + 1
 #define VS VD
 #define VD_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_VR },
 

-  /* The SIMM field in a VX form instruction. */
+  /* The SIMM field in a VX form instruction.  */

 #define SIMM VD + 1
   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 
 #define SIMM VD + 1
   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 

-  /* The UIMM field in a VX form instruction. */
+  /* The UIMM field in a VX form instruction.  */

 #define UIMM SIMM + 1
   { 5, 16, 0, 0, 0 },
 
 #define UIMM SIMM + 1
   { 5, 16, 0, 0, 0 },
 

-  /* The SHB field in a VA form instruction. */
+  /* The SHB field in a VA form instruction.  */

 #define SHB UIMM + 1
   { 4, 6, 0, 0, 0 },
 
 #define SHB UIMM + 1
   { 4, 6, 0, 0, 0 },
 

-  /* The other UIMM field in a EVX form instruction. */
+  /* The other UIMM field in a EVX form instruction.  */

 #define EVUIMM SHB + 1
   { 5, 11, 0, 0, 0 },
 
 #define EVUIMM SHB + 1
   { 5, 11, 0, 0, 0 },
 

-  /* The other UIMM field in a half word EVX form instruction. */
+  /* The other UIMM field in a half word EVX form instruction.  */

 #define EVUIMM_2 EVUIMM + 1
   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
 
 #define EVUIMM_2 EVUIMM + 1
   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
 

-  /* The other UIMM field in a word EVX form instruction. */
+  /* The other UIMM field in a word EVX form instruction.  */

 #define EVUIMM_4 EVUIMM_2 + 1
   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
 
 #define EVUIMM_4 EVUIMM_2 + 1
   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
 

-  /* The other UIMM field in a double EVX form instruction. */
+  /* The other UIMM field in a double EVX form instruction.  */

 #define EVUIMM_8 EVUIMM_4 + 1
   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
 
 #define EVUIMM_8 EVUIMM_4 + 1
   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
 


@@ -565,25 +567,21 @@ const struct powerpc_operand powerpc_operands[] =
    and the extraction function just checks that the fields are the
    same.  */
 
    and the extraction function just checks that the fields are the
    same.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_bat (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value ATTRIBUTE_UNUSED;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_bat (unsigned long insn,
+           long value ATTRIBUTE_UNUSED,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   return insn | (((insn >> 21) & 0x1f) << 16);
 }
 
 static long
 {
   return insn | (((insn >> 21) & 0x1f) << 16);
 }
 
 static long

-extract_bat (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_bat (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid)

 {
 {

-  if (invalid != (int *) NULL
-      && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
+  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))

     *invalid = 1;
   return 0;
 }
     *invalid = 1;
   return 0;
 }


@@ -594,25 +592,21 @@ extract_bat (insn, dialect, invalid)
    and the extraction function just checks that the fields are the
    same.  */
 
    and the extraction function just checks that the fields are the
    same.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_bba (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value ATTRIBUTE_UNUSED;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_bba (unsigned long insn,
+           long value ATTRIBUTE_UNUSED,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   return insn | (((insn >> 16) & 0x1f) << 11);
 }
 
 static long
 {
   return insn | (((insn >> 16) & 0x1f) << 11);
 }
 
 static long

-extract_bba (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_bba (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid)

 {
 {

-  if (invalid != (int *) NULL
-      && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
+  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))

     *invalid = 1;
   return 0;
 }
     *invalid = 1;
   return 0;
 }


@@ -620,23 +614,19 @@ extract_bba (insn, dialect, invalid)
 /* The BD field in a B form instruction.  The lower two bits are
    forced to zero.  */
 
 /* The BD field in a B form instruction.  The lower two bits are
    forced to zero.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_bd (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_bd (unsigned long insn,
+          long value,
+          int dialect ATTRIBUTE_UNUSED,
+          const char **errmsg ATTRIBUTE_UNUSED)

 {
   return insn | (value & 0xfffc);
 }
 
 {
   return insn | (value & 0xfffc);
 }
 

-/*ARGSUSED*/

 static long
 static long

-extract_bd (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_bd (unsigned long insn,
+           int dialect ATTRIBUTE_UNUSED,
+           int *invalid ATTRIBUTE_UNUSED)

 {
   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }
 {
   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }


@@ -654,13 +644,11 @@ extract_bd (insn, dialect, invalid)
    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
    for branch on CTR.  We only handle the taken/not-taken hint here.  */
 
    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
    for branch on CTR.  We only handle the taken/not-taken hint here.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_bdm (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_bdm (unsigned long insn,
+           long value,
+           int dialect,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   if ((dialect & PPC_OPCODE_POWER4) == 0)
     {
 {
   if ((dialect & PPC_OPCODE_POWER4) == 0)
     {


@@ -678,25 +666,22 @@ insert_bdm (insn, value, dialect, errmsg)
 }
 
 static long
 }
 
 static long

-extract_bdm (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect;
-     int *invalid;
+extract_bdm (unsigned long insn,
+            int dialect,
+            int *invalid)

 {
 {

-  if (invalid != (int *) NULL)
+  if ((dialect & PPC_OPCODE_POWER4) == 0)

     {
     {

-      if ((dialect & PPC_OPCODE_POWER4) == 0)
-       {
-         if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
-           *invalid = 1;
-       }
-      else
-       {
-         if ((insn & (0x17 << 21)) != (0x06 << 21)
-             && (insn & (0x1d << 21)) != (0x18 << 21))
-           *invalid = 1;
-       }
+      if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
+       *invalid = 1;

     }
     }

+  else
+    {
+      if ((insn & (0x17 << 21)) != (0x06 << 21)
+         && (insn & (0x1d << 21)) != (0x18 << 21))
+       *invalid = 1;
+    }
+

   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }
 
   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }
 


@@ -704,13 +689,11 @@ extract_bdm (insn, dialect, invalid)
    This is like BDM, above, except that the branch is expected to be
    taken.  */
 
    This is like BDM, above, except that the branch is expected to be
    taken.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_bdp (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_bdp (unsigned long insn,
+           long value,
+           int dialect,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   if ((dialect & PPC_OPCODE_POWER4) == 0)
     {
 {
   if ((dialect & PPC_OPCODE_POWER4) == 0)
     {


@@ -728,34 +711,29 @@ insert_bdp (insn, value, dialect, errmsg)
 }
 
 static long
 }
 
 static long

-extract_bdp (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect;
-     int *invalid;
+extract_bdp (unsigned long insn,
+            int dialect,
+            int *invalid)

 {
 {

-  if (invalid != (int *) NULL)
+  if ((dialect & PPC_OPCODE_POWER4) == 0)

     {
     {

-      if ((dialect & PPC_OPCODE_POWER4) == 0)
-       {
-         if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
-           *invalid = 1;
-       }
-      else
-       {
-         if ((insn & (0x17 << 21)) != (0x07 << 21)
-             && (insn & (0x1d << 21)) != (0x19 << 21))
-           *invalid = 1;
-       }
+      if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
+       *invalid = 1;
+    }
+  else
+    {
+      if ((insn & (0x17 << 21)) != (0x07 << 21)
+         && (insn & (0x1d << 21)) != (0x19 << 21))
+       *invalid = 1;

     }
     }

+

   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }
 
 /* Check for legal values of a BO field.  */
 
 static int
   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }
 
 /* Check for legal values of a BO field.  */
 
 static int

-valid_bo (value, dialect)
-     long value;
-     int dialect;
+valid_bo (long value, int dialect)

 {
   if ((dialect & PPC_OPCODE_POWER4) == 0)
     {
 {
   if ((dialect & PPC_OPCODE_POWER4) == 0)
     {


@@ -807,29 +785,25 @@ valid_bo (value, dialect)
    the field to an illegal value.  */
 
 static unsigned long
    the field to an illegal value.  */
 
 static unsigned long

-insert_bo (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect;
-     const char **errmsg;
+insert_bo (unsigned long insn,
+          long value,
+          int dialect,
+          const char **errmsg)

 {
 {

-  if (errmsg != (const char **) NULL
-      && ! valid_bo (value, dialect))
+  if (!valid_bo (value, dialect))

     *errmsg = _("invalid conditional option");
   return insn | ((value & 0x1f) << 21);
 }
 
 static long
     *errmsg = _("invalid conditional option");
   return insn | ((value & 0x1f) << 21);
 }
 
 static long

-extract_bo (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect;
-     int *invalid;
+extract_bo (unsigned long insn,
+           int dialect,
+           int *invalid)

 {
   long value;
 
   value = (insn >> 21) & 0x1f;
 {
   long value;
 
   value = (insn >> 21) & 0x1f;

-  if (invalid != (int *) NULL
-      && ! valid_bo (value, dialect))
+  if (!valid_bo (value, dialect))

     *invalid = 1;
   return value;
 }
     *invalid = 1;
   return value;
 }


@@ -839,102 +813,113 @@ extract_bo (insn, dialect, invalid)
    extracting it, we force it to be even.  */
 
 static unsigned long
    extracting it, we force it to be even.  */
 
 static unsigned long

-insert_boe (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect;
-     const char **errmsg;
+insert_boe (unsigned long insn,
+           long value,
+           int dialect,
+           const char **errmsg)

 {
 {

-  if (errmsg != (const char **) NULL)
-    {
-      if (! valid_bo (value, dialect))
-       *errmsg = _("invalid conditional option");
-      else if ((value & 1) != 0)
-       *errmsg = _("attempt to set y bit when using + or - modifier");
-    }
+  if (!valid_bo (value, dialect))
+    *errmsg = _("invalid conditional option");
+  else if ((value & 1) != 0)
+    *errmsg = _("attempt to set y bit when using + or - modifier");
+

   return insn | ((value & 0x1f) << 21);
 }
 
 static long
   return insn | ((value & 0x1f) << 21);
 }
 
 static long

-extract_boe (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect;
-     int *invalid;
+extract_boe (unsigned long insn,
+            int dialect,
+            int *invalid)

 {
   long value;
 
   value = (insn >> 21) & 0x1f;
 {
   long value;
 
   value = (insn >> 21) & 0x1f;

-  if (invalid != (int *) NULL
-      && ! valid_bo (value, dialect))
+  if (!valid_bo (value, dialect))

     *invalid = 1;
   return value & 0x1e;
 }
 
     *invalid = 1;
   return value & 0x1e;
 }
 

+/* The DQ field in a DQ form instruction.  This is like D, but the
+   lower four bits are forced to zero. */
+

 static unsigned long
 static unsigned long

-insert_ev2 (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char ** errmsg ATTRIBUTE_UNUSED;
+insert_dq (unsigned long insn,
+          long value,
+          int dialect ATTRIBUTE_UNUSED,
+          const char **errmsg)

 {
 {

-  if ((value & 1) != 0 && errmsg != NULL)
+  if ((value & 0xf) != 0)
+    *errmsg = _("offset not a multiple of 16");
+  return insn | (value & 0xfff0);
+}
+
+static long
+extract_dq (unsigned long insn,
+           int dialect ATTRIBUTE_UNUSED,
+           int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
+}
+
+static unsigned long
+insert_ev2 (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  if ((value & 1) != 0)

     *errmsg = _("offset not a multiple of 2");
     *errmsg = _("offset not a multiple of 2");

-  if ((value > 62) != 0 && errmsg != NULL)
+  if ((value > 62) != 0)

     *errmsg = _("offset greater than 62");
   return insn | ((value & 0x3e) << 10);
 }
 
 static long
     *errmsg = _("offset greater than 62");
   return insn | ((value & 0x3e) << 10);
 }
 
 static long

-extract_ev2 (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int * invalid ATTRIBUTE_UNUSED;
+extract_ev2 (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)

 {
   return (insn >> 10) & 0x3e;
 }
 
 static unsigned long
 {
   return (insn >> 10) & 0x3e;
 }
 
 static unsigned long

-insert_ev4 (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char ** errmsg ATTRIBUTE_UNUSED;
+insert_ev4 (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)

 {
 {

-  if ((value & 3) != 0 && errmsg != NULL)
+  if ((value & 3) != 0)

     *errmsg = _("offset not a multiple of 4");
     *errmsg = _("offset not a multiple of 4");

-  if ((value > 124) != 0 && errmsg != NULL)
+  if ((value > 124) != 0)

     *errmsg = _("offset greater than 124");
   return insn | ((value & 0x7c) << 9);
 }
 
 static long
     *errmsg = _("offset greater than 124");
   return insn | ((value & 0x7c) << 9);
 }
 
 static long

-extract_ev4 (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int * invalid ATTRIBUTE_UNUSED;
+extract_ev4 (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)

 {
   return (insn >> 9) & 0x7c;
 }
 
 static unsigned long
 {
   return (insn >> 9) & 0x7c;
 }
 
 static unsigned long

-insert_ev8 (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char ** errmsg ATTRIBUTE_UNUSED;
+insert_ev8 (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)

 {
 {

-  if ((value & 7) != 0 && errmsg != NULL)
+  if ((value & 7) != 0)

     *errmsg = _("offset not a multiple of 8");
     *errmsg = _("offset not a multiple of 8");

-  if ((value > 248) != 0 && errmsg != NULL)
+  if ((value > 248) != 0)

     *errmsg = _("offset greater than 248");
   return insn | ((value & 0xf8) << 8);
 }
 
 static long
     *errmsg = _("offset greater than 248");
   return insn | ((value & 0xf8) << 8);
 }
 
 static long

-extract_ev8 (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int * invalid ATTRIBUTE_UNUSED;
+extract_ev8 (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)

 {
   return (insn >> 8) & 0xf8;
 }
 {
   return (insn >> 8) & 0xf8;
 }


@@ -942,103 +927,159 @@ extract_ev8 (insn, dialect, invalid)
 /* The DS field in a DS form instruction.  This is like D, but the
    lower two bits are forced to zero.  */
 
 /* The DS field in a DS form instruction.  This is like D, but the
    lower two bits are forced to zero.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_ds (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_ds (unsigned long insn,
+          long value,
+          int dialect ATTRIBUTE_UNUSED,
+          const char **errmsg)

 {
 {

-  if ((value & 3) != 0 && errmsg != NULL)
+  if ((value & 3) != 0)

     *errmsg = _("offset not a multiple of 4");
   return insn | (value & 0xfffc);
 }
 
     *errmsg = _("offset not a multiple of 4");
   return insn | (value & 0xfffc);
 }
 

-/*ARGSUSED*/

 static long
 static long

-extract_ds (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_ds (unsigned long insn,
+           int dialect ATTRIBUTE_UNUSED,
+           int *invalid ATTRIBUTE_UNUSED)

 {
   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }
 
 /* The DE field in a DE form instruction.  */
 
 {
   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
 }
 
 /* The DE field in a DE form instruction.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_de (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_de (unsigned long insn,
+          long value,
+          int dialect ATTRIBUTE_UNUSED,
+          const char **errmsg)

 {
 {

-  if ((value > 2047 || value < -2048) && errmsg != NULL)
+  if (value > 2047 || value < -2048)

     *errmsg = _("offset not between -2048 and 2047");
   return insn | ((value << 4) & 0xfff0);
 }
 
     *errmsg = _("offset not between -2048 and 2047");
   return insn | ((value << 4) & 0xfff0);
 }
 

-/*ARGSUSED*/

 static long
 static long

-extract_de (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_de (unsigned long insn,
+           int dialect ATTRIBUTE_UNUSED,
+           int *invalid ATTRIBUTE_UNUSED)

 {
   return (insn & 0xfff0) >> 4;
 }
 
 /* The DES field in a DES form instruction.  */
 
 {
   return (insn & 0xfff0) >> 4;
 }
 
 /* The DES field in a DES form instruction.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_des (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_des (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)

 {
 {

-  if ((value > 8191 || value < -8192) && errmsg != NULL)
+  if (value > 8191 || value < -8192)

     *errmsg = _("offset not between -8192 and 8191");
     *errmsg = _("offset not between -8192 and 8191");

-  else if ((value & 3) != 0 && errmsg != NULL)
+  else if ((value & 3) != 0)

     *errmsg = _("offset not a multiple of 4");
   return insn | ((value << 2) & 0xfff0);
 }
 
     *errmsg = _("offset not a multiple of 4");
   return insn | ((value << 2) & 0xfff0);
 }
 

-/*ARGSUSED*/

 static long
 static long

-extract_des (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_des (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)

 {
   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 }
 
 {
   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 }
 

+/* FXM mask in mfcr and mtcrf instructions.  */
+
+static unsigned long
+insert_fxm (unsigned long insn,
+           long value,
+           int dialect,
+           const char **errmsg)
+{
+  /* If we're handling the mfocrf and mtocrf insns ensure that exactly
+     one bit of the mask field is set.  */
+  if ((insn & (1 << 20)) != 0)
+    {
+      if (value == 0 || (value & -value) != value)
+       {
+         *errmsg = _("invalid mask field");
+         value = 0;
+       }
+    }
+
+  /* If the optional field on mfcr is missing that means we want to use
+     the old form of the instruction that moves the whole cr.  In that
+     case we'll have VALUE zero.  There doesn't seem to be a way to
+     distinguish this from the case where someone writes mfcr %r3,0.  */
+  else if (value == 0)
+    ;
+
+  /* If only one bit of the FXM field is set, we can use the new form
+     of the instruction, which is faster.  Unlike the Power4 branch hint
+     encoding, this is not backward compatible.  Do not generate the
+     new form unless -mpower4 has been given, or -many and the two
+     operand form of mfcr was used.  */
+  else if ((value & -value) == value
+          && ((dialect & PPC_OPCODE_POWER4) != 0
+              || ((dialect & PPC_OPCODE_ANY) != 0
+                  && (insn & (0x3ff << 1)) == 19 << 1)))
+    insn |= 1 << 20;
+
+  /* Any other value on mfcr is an error.  */
+  else if ((insn & (0x3ff << 1)) == 19 << 1)
+    {
+      *errmsg = _("ignoring invalid mfcr mask");
+      value = 0;
+    }
+
+  return insn | ((value & 0xff) << 12);
+}
+
+static long
+extract_fxm (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid)
+{
+  long mask = (insn >> 12) & 0xff;
+
+  /* Is this a Power4 insn?  */
+  if ((insn & (1 << 20)) != 0)
+    {
+      /* Exactly one bit of MASK should be set.  */
+      if (mask == 0 || (mask & -mask) != mask)
+       *invalid = 1;
+    }
+
+  /* Check that non-power4 form of mfcr has a zero MASK.  */
+  else if ((insn & (0x3ff << 1)) == 19 << 1)
+    {
+      if (mask != 0)
+       *invalid = 1;
+    }
+
+  return mask;
+}
+

 /* The LI field in an I form instruction.  The lower two bits are
    forced to zero.  */
 
 /* The LI field in an I form instruction.  The lower two bits are
    forced to zero.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_li (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_li (unsigned long insn,
+          long value,
+          int dialect ATTRIBUTE_UNUSED,
+          const char **errmsg)

 {
 {

-  if ((value & 3) != 0 && errmsg != (const char **) NULL)
+  if ((value & 3) != 0)

     *errmsg = _("ignoring least significant bits in branch offset");
   return insn | (value & 0x3fffffc);
 }
 
     *errmsg = _("ignoring least significant bits in branch offset");
   return insn | (value & 0x3fffffc);
 }
 

-/*ARGSUSED*/

 static long
 static long

-extract_li (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_li (unsigned long insn,
+           int dialect ATTRIBUTE_UNUSED,
+           int *invalid ATTRIBUTE_UNUSED)

 {
   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
 }
 {
   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
 }


@@ -1049,11 +1090,10 @@ extract_li (insn, dialect, invalid)
    instruction which uses a field of this type.  */
 
 static unsigned long
    instruction which uses a field of this type.  */
 
 static unsigned long

-insert_mbe (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_mbe (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)

 {
   unsigned long uval, mask;
   int mb, me, mx, count, last;
 {
   unsigned long uval, mask;
   int mb, me, mx, count, last;


@@ -1062,8 +1102,7 @@ insert_mbe (insn, value, dialect, errmsg)
 
   if (uval == 0)
     {
 
   if (uval == 0)
     {

-      if (errmsg != (const char **) NULL)
-       *errmsg = _("illegal bitmask");
+      *errmsg = _("illegal bitmask");

       return insn;
     }
 
       return insn;
     }
 


@@ -1079,7 +1118,7 @@ insert_mbe (insn, value, dialect, errmsg)
   /* me: location of last 1->0 transition */
   /* count: # transitions */
 
   /* me: location of last 1->0 transition */
   /* count: # transitions */
 

-  for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1)
+  for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)

     {
       if ((uval & mask) && !last)
        {
     {
       if ((uval & mask) && !last)
        {


@@ -1098,26 +1137,21 @@ insert_mbe (insn, value, dialect, errmsg)
     me = 32;
 
   if (count != 2 && (count != 0 || ! last))
     me = 32;
 
   if (count != 2 && (count != 0 || ! last))

-    {
-      if (errmsg != (const char **) NULL)
-       *errmsg = _("illegal bitmask");
-    }
+    *errmsg = _("illegal bitmask");

 
   return insn | (mb << 6) | ((me - 1) << 1);
 }
 
 static long
 
   return insn | (mb << 6) | ((me - 1) << 1);
 }
 
 static long

-extract_mbe (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_mbe (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid)

 {
   long ret;
   int mb, me;
   int i;
 
 {
   long ret;
   int mb, me;
   int i;
 

-  if (invalid != (int *) NULL)
-    *invalid = 1;
+  *invalid = 1;

 
   mb = (insn >> 6) & 0x1f;
   me = (insn >> 1) & 0x1f;
 
   mb = (insn >> 6) & 0x1f;
   me = (insn >> 1) & 0x1f;


@@ -1125,15 +1159,15 @@ extract_mbe (insn, dialect, invalid)
     {
       ret = 0;
       for (i = mb; i <= me; i++)
     {
       ret = 0;
       for (i = mb; i <= me; i++)

-       ret |= (long) 1 << (31 - i);
+       ret |= 1L << (31 - i);

     }
   else if (mb == me + 1)
     ret = ~0;
   else /* (mb > me + 1) */
     {
     }
   else if (mb == me + 1)
     ret = ~0;
   else /* (mb > me + 1) */
     {

-      ret = ~ (long) 0;
+      ret = ~0;

       for (i = me + 1; i < mb; i++)
       for (i = me + 1; i < mb; i++)

-       ret &= ~ ((long) 1 << (31 - i));
+       ret &= ~(1L << (31 - i));

     }
   return ret;
 }
     }
   return ret;
 }


@@ -1141,23 +1175,19 @@ extract_mbe (insn, dialect, invalid)
 /* The MB or ME field in an MD or MDS form instruction.  The high bit
    is wrapped to the low end.  */
 
 /* The MB or ME field in an MD or MDS form instruction.  The high bit
    is wrapped to the low end.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_mb6 (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_mb6 (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 }
 
 {
   return insn | ((value & 0x1f) << 6) | (value & 0x20);
 }
 

-/*ARGSUSED*/

 static long
 static long

-extract_mb6 (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_mb6 (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)

 {
   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 }
 {
   return ((insn >> 6) & 0x1f) | (insn & 0x20);
 }


@@ -1166,11 +1196,10 @@ extract_mb6 (insn, dialect, invalid)
    0.  */
 
 static unsigned long
    0.  */
 
 static unsigned long

-insert_nb (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_nb (unsigned long insn,
+          long value,
+          int dialect ATTRIBUTE_UNUSED,
+          const char **errmsg)

 {
   if (value < 0 || value > 32)
     *errmsg = _("value out of range");
 {
   if (value < 0 || value > 32)
     *errmsg = _("value out of range");


@@ -1179,12 +1208,10 @@ insert_nb (insn, value, dialect, errmsg)
   return insn | ((value & 0x1f) << 11);
 }
 
   return insn | ((value & 0x1f) << 11);
 }
 

-/*ARGSUSED*/

 static long
 static long

-extract_nb (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_nb (unsigned long insn,
+           int dialect ATTRIBUTE_UNUSED,
+           int *invalid ATTRIBUTE_UNUSED)

 {
   long ret;
 
 {
   long ret;
 


@@ -1199,26 +1226,22 @@ extract_nb (insn, dialect, invalid)
    invalid, since we never want to recognize an instruction which uses
    a field of this type.  */
 
    invalid, since we never want to recognize an instruction which uses
    a field of this type.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_nsi (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_nsi (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
 {

-  return insn | ((- value) & 0xffff);
+  return insn | (-value & 0xffff);

 }
 
 static long
 }
 
 static long

-extract_nsi (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_nsi (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid)

 {
 {

-  if (invalid != (int *) NULL)
-    *invalid = 1;
-  return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
+  *invalid = 1;
+  return -(((insn & 0xffff) ^ 0x8000) - 0x8000);

 }
 
 /* The RA field in a D or X form instruction which is an updating
 }
 
 /* The RA field in a D or X form instruction which is an updating


@@ -1226,11 +1249,10 @@ extract_nsi (insn, dialect, invalid)
    equal the RT field.  */
 
 static unsigned long
    equal the RT field.  */
 
 static unsigned long

-insert_ral (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_ral (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)

 {
   if (value == 0
       || (unsigned long) value == ((insn >> 21) & 0x1f))
 {
   if (value == 0
       || (unsigned long) value == ((insn >> 21) & 0x1f))


@@ -1242,27 +1264,41 @@ insert_ral (insn, value, dialect, errmsg)
    restrictions.  */
 
 static unsigned long
    restrictions.  */
 
 static unsigned long

-insert_ram (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_ram (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)

 {
   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
     *errmsg = _("index register in load range");
   return insn | ((value & 0x1f) << 16);
 }
 
 {
   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
     *errmsg = _("index register in load range");
   return insn | ((value & 0x1f) << 16);
 }
 

+/* The RA field in the DQ form lq instruction, which has special
+   value restrictions.  */
+
+static unsigned long
+insert_raq (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  long rtvalue = (insn & RT_MASK) >> 21;
+
+  if (value == rtvalue)
+    *errmsg = _("source and target register operands must be different");
+  return insn | ((value & 0x1f) << 16);
+}
+

 /* The RA field in a D or X form instruction which is an updating
    store or an updating floating point load, which means that the RA
    field may not be zero.  */
 
 static unsigned long
 /* The RA field in a D or X form instruction which is an updating
    store or an updating floating point load, which means that the RA
    field may not be zero.  */
 
 static unsigned long

-insert_ras (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg;
+insert_ras (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)

 {
   if (value == 0)
     *errmsg = _("invalid register operand when updating");
 {
   if (value == 0)
     *errmsg = _("invalid register operand when updating");


@@ -1275,48 +1311,68 @@ insert_ras (insn, value, dialect, errmsg)
    function just copies the BT field into the BA field, and the
    extraction function just checks that the fields are the same.  */
 
    function just copies the BT field into the BA field, and the
    extraction function just checks that the fields are the same.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_rbs (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value ATTRIBUTE_UNUSED;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_rbs (unsigned long insn,
+           long value ATTRIBUTE_UNUSED,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   return insn | (((insn >> 21) & 0x1f) << 11);
 }
 
 static long
 {
   return insn | (((insn >> 21) & 0x1f) << 11);
 }
 
 static long

-extract_rbs (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid;
+extract_rbs (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid)

 {
 {

-  if (invalid != (int *) NULL
-      && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
+  if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))

     *invalid = 1;
   return 0;
 }
 
     *invalid = 1;
   return 0;
 }
 

+/* The RT field of the DQ form lq instruction, which has special
+   value restrictions.  */
+
+static unsigned long
+insert_rtq (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  if ((value & 1) != 0)
+    *errmsg = _("target register operand must be even");
+  return insn | ((value & 0x1f) << 21);
+}
+
+/* The RS field of the DS form stq instruction, which has special
+   value restrictions.  */
+
+static unsigned long
+insert_rsq (unsigned long insn,
+           long value ATTRIBUTE_UNUSED,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg)
+{
+  if ((value & 1) != 0)
+    *errmsg = _("source register operand must be even");
+  return insn | ((value & 0x1f) << 21);
+}
+

 /* The SH field in an MD form instruction.  This is split.  */
 
 /* The SH field in an MD form instruction.  This is split.  */
 

-/*ARGSUSED*/

 static unsigned long
 static unsigned long

-insert_sh6 (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_sh6 (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
 }
 
 {
   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
 }
 

-/*ARGSUSED*/

 static long
 static long

-extract_sh6 (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_sh6 (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)

 {
   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
 }
 {
   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
 }


@@ -1325,20 +1381,18 @@ extract_sh6 (insn, dialect, invalid)
    lower 5 bits are stored in the upper 5 and vice- versa.  */
 
 static unsigned long
    lower 5 bits are stored in the upper 5 and vice- versa.  */
 
 static unsigned long

-insert_spr (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_spr (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
 }
 
 static long
 {
   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
 }
 
 static long

-extract_spr (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_spr (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)

 {
   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
 }
 {
   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
 }


@@ -1354,11 +1408,10 @@ extract_spr (insn, dialect, invalid)
 #define TB (268)
 
 static unsigned long
 #define TB (268)
 
 static unsigned long

-insert_tbr (insn, value, dialect, errmsg)
-     unsigned long insn;
-     long value;
-     int dialect ATTRIBUTE_UNUSED;
-     const char **errmsg ATTRIBUTE_UNUSED;
+insert_tbr (unsigned long insn,
+           long value,
+           int dialect ATTRIBUTE_UNUSED,
+           const char **errmsg ATTRIBUTE_UNUSED)

 {
   if (value == 0)
     value = TB;
 {
   if (value == 0)
     value = TB;


@@ -1366,10 +1419,9 @@ insert_tbr (insn, value, dialect, errmsg)
 }
 
 static long
 }
 
 static long

-extract_tbr (insn, dialect, invalid)
-     unsigned long insn;
-     int dialect ATTRIBUTE_UNUSED;
-     int *invalid ATTRIBUTE_UNUSED;
+extract_tbr (unsigned long insn,
+            int dialect ATTRIBUTE_UNUSED,
+            int *invalid ATTRIBUTE_UNUSED)

 {
   long ret;
 
 {
   long ret;
 


@@ -1444,11 +1496,11 @@ extract_tbr (insn, dialect, invalid)
 
 /* An Context form instruction.  */
 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
 
 /* An Context form instruction.  */
 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))

-#define CTX_MASK       CTX(0x3f, 0x7)
+#define CTX_MASK CTX(0x3f, 0x7)

 
 /* An User Context form instruction.  */
 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
 
 /* An User Context form instruction.  */
 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))

-#define UCTX_MASK      UCTX(0x3f, 0x1f)
+#define UCTX_MASK UCTX(0x3f, 0x1f)

 
 /* The main opcode mask with the RA field clear.  */
 #define DRA_MASK (OP_MASK | RA_MASK)
 
 /* The main opcode mask with the RA field clear.  */
 #define DRA_MASK (OP_MASK | RA_MASK)


@@ -1499,22 +1551,22 @@ extract_tbr (insn, dialect, invalid)
 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
 
 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
 

-/* An VX form instruction. */
+/* An VX form instruction.  */

 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
 
 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
 

-/* The mask for an VX form instruction. */
+/* The mask for an VX form instruction.  */

 #define VX_MASK        VX(0x3f, 0x7ff)
 
 #define VX_MASK        VX(0x3f, 0x7ff)
 

-/* An VA form instruction. */
+/* An VA form instruction.  */

 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
 
 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
 

-/* The mask for an VA form instruction. */
+/* The mask for an VA form instruction.  */

 #define VXA_MASK VXA(0x3f, 0x3f)
 
 #define VXA_MASK VXA(0x3f, 0x3f)
 

-/* An VXR form instruction. */
+/* An VXR form instruction.  */

 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
 
 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
 

-/* The mask for a VXR form instruction. */
+/* The mask for a VXR form instruction.  */

 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
 
 /* An X form instruction.  */
 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
 
 /* An X form instruction.  */


@@ -1538,7 +1590,7 @@ extract_tbr (insn, dialect, invalid)
 /* An X_MASK with the RA and RB fields fixed.  */
 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 
 /* An X_MASK with the RA and RB fields fixed.  */
 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 

-/* An XRARB_MASK, but with the L bit clear. */
+/* An XRARB_MASK, but with the L bit clear.  */

 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
 
 /* An X_MASK with the RT and RA fields fixed.  */
 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
 
 /* An X_MASK with the RT and RA fields fixed.  */


@@ -1547,8 +1599,8 @@ extract_tbr (insn, dialect, invalid)
 /* An XRTRA_MASK, but with L bit clear.  */
 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
 
 /* An XRTRA_MASK, but with L bit clear.  */
 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
 

-/* An X form comparison instruction.  */
-#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
+/* An X form instruction with the L bit specified.  */
+#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))

 
 /* The mask for an X form comparison instruction.  */
 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
 
 /* The mask for an X form comparison instruction.  */
 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))


@@ -1613,6 +1665,9 @@ extract_tbr (insn, dialect, invalid)
 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
 
 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
 

+/* A mask for branch instructions using the BH field.  */
+#define XLBH_MASK (XL_MASK | (0x1c << 11))
+

 /* An XL_MASK with the BO and BB fields fixed.  */
 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
 
 /* An XL_MASK with the BO and BB fields fixed.  */
 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
 


@@ -1632,11 +1687,12 @@ extract_tbr (insn, dialect, invalid)
 #define XS_MASK XS (0x3f, 0x1ff, 1)
 
 /* A mask for the FXM version of an XFX form instruction.  */
 #define XS_MASK XS (0x3f, 0x1ff, 1)
 
 /* A mask for the FXM version of an XFX form instruction.  */

-#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
+#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))

 
 /* An XFX form instruction with the FXM field filled in.  */
 
 /* An XFX form instruction with the FXM field filled in.  */

-#define XFXM(op, xop, fxm) \
-  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
+#define XFXM(op, xop, fxm, p4) \
+  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
+   | ((unsigned long)(p4) << 20))

 
 /* An XFX form instruction with the SPR field filled in.  */
 #define XSPR(op, xop, spr) \
 
 /* An XFX form instruction with the SPR field filled in.  */
 #define XSPR(op, xop, spr) \


@@ -1715,26 +1771,26 @@ extract_tbr (insn, dialect, invalid)
 /* Smaller names for the flags so each entry in the opcodes table will
    fit on a single line.  */
 #undef PPC
 /* Smaller names for the flags so each entry in the opcodes table will
    fit on a single line.  */
 #undef PPC

-#define PPC     PPC_OPCODE_PPC | PPC_OPCODE_ANY
-#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
+#define PPC     PPC_OPCODE_PPC
+#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON

 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM

-#define POWER4 PPC_OPCODE_POWER4 | PPCCOM
-#define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
-#define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
-#define PPCONLY        PPC_OPCODE_PPC
+#define POWER4 PPC_OPCODE_POWER4
+#define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
+#define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC

 #define PPC403 PPC_OPCODE_403
 #define PPC405 PPC403
 #define PPC403 PPC_OPCODE_403
 #define PPC405 PPC403

+#define PPC440 PPC_OPCODE_440

 #define PPC750 PPC
 #define PPC860 PPC
 #define PPC750 PPC
 #define PPC860 PPC

-#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
-#define        POWER   PPC_OPCODE_POWER | PPC_OPCODE_ANY
-#define        POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
-#define PPCPWR2        PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
-#define        POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
-#define        COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
-#define        COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
-#define        M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
-#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
+#define PPCVEC PPC_OPCODE_ALTIVEC
+#define        POWER   PPC_OPCODE_POWER
+#define        POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
+#define PPCPWR2        PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
+#define        POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
+#define        COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
+#define        COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
+#define        M601    PPC_OPCODE_POWER | PPC_OPCODE_601
+#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON

 #define        MFDEC1  PPC_OPCODE_POWER
 #define        MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
 #define BOOKE  PPC_OPCODE_BOOKE
 #define        MFDEC1  PPC_OPCODE_POWER
 #define        MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
 #define BOOKE  PPC_OPCODE_BOOKE


@@ -1768,6 +1824,7 @@ extract_tbr (insn, dialect, invalid)
    sorted by major opcode.  */
 
 const struct powerpc_opcode powerpc_opcodes[] = {
    sorted by major opcode.  */
 
 const struct powerpc_opcode powerpc_opcodes[] = {

+{ "attn",    X(0,256), X_MASK,         POWER4,         { 0 } },

 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK, PPC64,          { RA, SI } },
 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK, PPC64,          { RA, SI } },
 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,  PPC64,          { RA, SI } },
 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK, PPC64,          { RA, SI } },
 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK, PPC64,          { RA, SI } },
 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,  PPC64,          { RA, SI } },


@@ -1815,90 +1872,90 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "twi",     OP(3),    OP_MASK,        PPCCOM,         { TO, RA, SI } },
 { "ti",      OP(3),    OP_MASK,        PWRCOM,         { TO, RA, SI } },
 
 { "twi",     OP(3),    OP_MASK,        PPCCOM,         { TO, RA, SI } },
 { "ti",      OP(3),    OP_MASK,        PWRCOM,         { TO, RA, SI } },
 

-{ "macchw",    XO(4,172,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchw.",   XO(4,172,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwo",   XO(4,172,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwo.",  XO(4,172,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchws",   XO(4,236,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchws.",  XO(4,236,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwso",  XO(4,236,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwsu",  XO(4,204,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwsuo.",        XO(4,204,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwu",   XO(4,140,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwu.",  XO(4,140,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwuo",  XO(4,140,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhw",    XO(4,44,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhw.",   XO(4,44,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwo",   XO(4,44,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwo.",  XO(4,44,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhws",   XO(4,108,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhws.",  XO(4,108,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwso",  XO(4,108,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwsu",  XO(4,76,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwsu.", XO(4,76,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwsuo", XO(4,76,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwsuo.",        XO(4,76,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwu",   XO(4,12,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwu.",  XO(4,12,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwuo",  XO(4,12,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwuo.", XO(4,12,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhw",    XO(4,428,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhw.",   XO(4,428,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwo",   XO(4,428,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwo.",  XO(4,428,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhws",   XO(4,492,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhws.",  XO(4,492,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwso",  XO(4,492,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwsu",  XO(4,460,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwsuo.",        XO(4,460,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwu",   XO(4,396,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwu.",  XO(4,396,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwuo",  XO(4,396,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "mulchw",    XRC(4,168,0),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulchw.",   XRC(4,168,1),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulchwu",   XRC(4,136,0),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulchwu.",  XRC(4,136,1),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulhhw",    XRC(4,40,0),   X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulhhw.",   XRC(4,40,1),   X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulhhwu",   XRC(4,8,0),    X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulhhwu.",  XRC(4,8,1),    X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mullhw",    XRC(4,424,0),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mullhw.",   XRC(4,424,1),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mullhwu",   XRC(4,392,0),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mullhwu.",  XRC(4,392,1),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "nmacchw",   XO(4,174,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchw.",  XO(4,174,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchwo",  XO(4,174,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchws",  XO(4,238,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchwso.",        XO(4,238,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhw",   XO(4,46,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhw.",  XO(4,46,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhwo",  XO(4,46,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhwo.", XO(4,46,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhws",  XO(4,110,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhwso.",        XO(4,110,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhw",   XO(4,430,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhw.",  XO(4,430,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhwo",  XO(4,430,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhws",  XO(4,494,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhwso.",        XO(4,494,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
+{ "macchw",    XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchw.",   XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwo",   XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwo.",  XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchws",   XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchws.",  XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwso",  XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsu",  XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsuo.",        XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwu",   XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwu.",  XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwuo",  XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhw",    XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhw.",   XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwo",   XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwo.",  XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhws",   XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhws.",  XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwso",  XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsu",  XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsu.", XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsuo", XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsuo.",        XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwu",   XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwu.",  XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwuo",  XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwuo.", XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhw",    XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhw.",   XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwo",   XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwo.",  XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhws",   XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhws.",  XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwso",  XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsu",  XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsuo.",        XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwu",   XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwu.",  XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwuo",  XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchw",    XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchw.",   XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchwu",   XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchwu.",  XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhw",    XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhw.",   XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhwu",   XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhwu.",  XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhw",    XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhw.",   XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhwu",   XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhwu.",  XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchw",   XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchw.",  XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwo",  XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchws",  XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwso.",        XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhw",   XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhw.",  XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwo",  XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwo.", XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhws",  XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwso.",        XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhw",   XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhw.",  XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwo",  XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhws",  XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwso.",        XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },

 { "mfvscr",  VX(4, 1540), VX_MASK,     PPCVEC,         { VD } },
 { "mtvscr",  VX(4, 1604), VX_MASK,     PPCVEC,         { VB } },
 { "vaddcuw", VX(4,  384), VX_MASK,     PPCVEC,         { VD, VA, VB } },
 { "mfvscr",  VX(4, 1540), VX_MASK,     PPCVEC,         { VD } },
 { "mtvscr",  VX(4, 1604), VX_MASK,     PPCVEC,         { VB } },
 { "vaddcuw", VX(4,  384), VX_MASK,     PPCVEC,         { VD, VA, VB } },


@@ -2320,12 +2377,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "cmplwi",  OPL(10,0),        OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
 { "cmpldi",  OPL(10,1), OPL_MASK,      PPC64,          { OBF, RA, UI } },
 
 { "cmplwi",  OPL(10,0),        OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
 { "cmpldi",  OPL(10,1), OPL_MASK,      PPC64,          { OBF, RA, UI } },

-{ "cmpli",   OP(10),   OP_MASK,        PPCONLY,        { BF, L, RA, UI } },
+{ "cmpli",   OP(10),   OP_MASK,        PPC,            { BF, L, RA, UI } },

 { "cmpli",   OP(10),   OP_MASK,        PWRCOM,         { BF, RA, UI } },
 
 { "cmpwi",   OPL(11,0),        OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
 { "cmpdi",   OPL(11,1),        OPL_MASK,       PPC64,          { OBF, RA, SI } },
 { "cmpli",   OP(10),   OP_MASK,        PWRCOM,         { BF, RA, UI } },
 
 { "cmpwi",   OPL(11,0),        OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
 { "cmpdi",   OPL(11,1),        OPL_MASK,       PPC64,          { OBF, RA, SI } },

-{ "cmpi",    OP(11),   OP_MASK,        PPCONLY,        { BF, L, RA, SI } },
+{ "cmpi",    OP(11),   OP_MASK,        PPC,            { BF, L, RA, SI } },

 { "cmpi",    OP(11),   OP_MASK,        PWRCOM,         { BF, RA, SI } },
 
 { "addic",   OP(12),   OP_MASK,        PPCCOM,         { RT, RA, SI } },
 { "cmpi",    OP(11),   OP_MASK,        PWRCOM,         { BF, RA, SI } },
 
 { "addic",   OP(12),   OP_MASK,        PPCCOM,         { RT, RA, SI } },


@@ -2338,45 +2395,45 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "li",             OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
 { "lil",     OP(14),   DRA_MASK,       PWRCOM,         { RT, SI } },
 
 { "li",             OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
 { "lil",     OP(14),   DRA_MASK,       PWRCOM,         { RT, SI } },

-{ "addi",    OP(14),   OP_MASK,        PPCCOM,         { RT, RA, SI } },
-{ "cal",     OP(14),   OP_MASK,        PWRCOM,         { RT, D, RA } },
-{ "subi",    OP(14),   OP_MASK,        PPCCOM,         { RT, RA, NSI } },
-{ "la",             OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA } },
+{ "addi",    OP(14),   OP_MASK,        PPCCOM,         { RT, RA0, SI } },
+{ "cal",     OP(14),   OP_MASK,        PWRCOM,         { RT, D, RA0 } },
+{ "subi",    OP(14),   OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
+{ "la",             OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },

 
 { "lis",     OP(15),   DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
 { "liu",     OP(15),   DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
 
 { "lis",     OP(15),   DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
 { "liu",     OP(15),   DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },

-{ "addis",   OP(15),   OP_MASK,        PPCCOM,         { RT,RA,SISIGNOPT } },
-{ "cau",     OP(15),   OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
-{ "subis",   OP(15),   OP_MASK,        PPCCOM,         { RT, RA, NSI } },
-
-{ "bdnz-",   BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,  { BDM } },
-{ "bdnz+",   BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,  { BDP } },
-{ "bdnz",    BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,  { BD } },
-{ "bdn",     BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM,  { BD } },
-{ "bdnzl-",  BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,  { BDM } },
-{ "bdnzl+",  BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,  { BDP } },
-{ "bdnzl",   BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,  { BD } },
-{ "bdnl",    BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM,  { BD } },
-{ "bdnza-",  BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,  { BDMA } },
-{ "bdnza+",  BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,  { BDPA } },
-{ "bdnza",   BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,  { BDA } },
-{ "bdna",    BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM,  { BDA } },
-{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,  { BDMA } },
-{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,  { BDPA } },
-{ "bdnzla",  BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,  { BDA } },
-{ "bdnla",   BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM,  { BDA } },
-{ "bdz-",    BBO(16,BODZ,0,0),  BBOATBI_MASK, PPCCOM,  { BDM } },
-{ "bdz+",    BBO(16,BODZ,0,0),  BBOATBI_MASK, PPCCOM,  { BDP } },
-{ "bdz",     BBO(16,BODZ,0,0),  BBOATBI_MASK, COM,     { BD } },
-{ "bdzl-",   BBO(16,BODZ,0,1),  BBOATBI_MASK, PPCCOM,  { BDM } },
-{ "bdzl+",   BBO(16,BODZ,0,1),  BBOATBI_MASK, PPCCOM,  { BDP } },
-{ "bdzl",    BBO(16,BODZ,0,1),  BBOATBI_MASK, COM,     { BD } },
-{ "bdza-",   BBO(16,BODZ,1,0),  BBOATBI_MASK, PPCCOM,  { BDMA } },
-{ "bdza+",   BBO(16,BODZ,1,0),  BBOATBI_MASK, PPCCOM,  { BDPA } },
-{ "bdza",    BBO(16,BODZ,1,0),  BBOATBI_MASK, COM,     { BDA } },
-{ "bdzla-",  BBO(16,BODZ,1,1),  BBOATBI_MASK, PPCCOM,  { BDMA } },
-{ "bdzla+",  BBO(16,BODZ,1,1),  BBOATBI_MASK, PPCCOM,  { BDPA } },
-{ "bdzla",   BBO(16,BODZ,1,1),  BBOATBI_MASK, COM,     { BDA } },
+{ "addis",   OP(15),   OP_MASK,        PPCCOM,         { RT,RA0,SISIGNOPT } },
+{ "cau",     OP(15),   OP_MASK,        PWRCOM,         { RT,RA0,SISIGNOPT } },
+{ "subis",   OP(15),   OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
+
+{ "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BDM } },
+{ "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BDP } },
+{ "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BD } },
+{ "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,     { BD } },
+{ "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BDM } },
+{ "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BDP } },
+{ "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BD } },
+{ "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,     { BD } },
+{ "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDMA } },
+{ "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDPA } },
+{ "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDA } },
+{ "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,     { BDA } },
+{ "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDMA } },
+{ "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDPA } },
+{ "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDA } },
+{ "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,     { BDA } },
+{ "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,     { BDM } },
+{ "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,     { BDP } },
+{ "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,                { BD } },
+{ "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,     { BDM } },
+{ "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,     { BDP } },
+{ "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,                { BD } },
+{ "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,     { BDMA } },
+{ "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,     { BDPA } },
+{ "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,                { BDA } },
+{ "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,     { BDMA } },
+{ "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,     { BDPA } },
+{ "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,                { BDA } },

 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,                { CR, BD } },
 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,                { CR, BD } },


@@ -2625,7 +2682,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "ba",      B(18,1,0),        B_MASK,         COM,            { LIA } },
 { "bla",     B(18,1,1),        B_MASK,         COM,            { LIA } },
 
 { "ba",      B(18,1,0),        B_MASK,         COM,            { LIA } },
 { "bla",     B(18,1,1),        B_MASK,         COM,            { LIA } },
 

-{ "mcrf",    XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
+{ "mcrf",    XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },

 
 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,  { 0 } },
 
 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,  { 0 } },


@@ -2633,186 +2690,186 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,  { 0 } },
 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM,        { 0 } },
 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,  { 0 } },
 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM,        { 0 } },
 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },

-{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,     { 0 } },

 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,      { 0 } },
 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,      { 0 } },

+{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,     { 0 } },

 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,      { 0 } },
 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM,        { 0 } },
 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,      { 0 } },
 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM,        { 0 } },
 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },

-{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,     { 0 } },

 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,      { 0 } },
 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,      { 0 } },

+{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,     { 0 } },

 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,      { 0 } },
 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,      { 0 } },
 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },

-{ "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },

 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },

+{ "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },

 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },

-{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },

 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },

+{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },

 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },

-{ "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },

 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,  { BI } },
 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,  { BI } },

+{ "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },

 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,  { BI } },
 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,    { BI } },
 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,  { BI } },
 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,    { BI } },
 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },

-{ "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },

 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,  { BI } },
 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,  { BI } },

+{ "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },

 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,  { BI } },
 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,    { BI } },
 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,  { BI } },
 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,    { BI } },
 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,    { BI } },
 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },

-{ "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },

 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,  { BI } },
 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,  { BI } },

+{ "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },

 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,  { BI } },
 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,    { BI } },
 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,  { BI } },
 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,    { BI } },
 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,    { BI } },
 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },

-{ "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },

 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,  { BI } },
 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,  { BI } },

+{ "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },

 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,  { BI } },
 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,    { BI } },
 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,  { BI } },
 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,    { BI } },
 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },


@@ -2839,12 +2896,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4,        { BI } },
 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4,        { BI } },
 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },

-{ "bclr",    XLLK(19,16,0), XLYBB_MASK,        PPCCOM,         { BO, BI } },
-{ "bclrl",   XLLK(19,16,1), XLYBB_MASK,        PPCCOM,         { BO, BI } },

 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,     { BOE, BI } },
 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,     { BOE, BI } },

+{ "bclr",    XLLK(19,16,0), XLBH_MASK, PPCCOM,         { BO, BI, BH } },
+{ "bclrl",   XLLK(19,16,1), XLBH_MASK, PPCCOM,         { BO, BI, BH } },

 { "bcr",     XLLK(19,16,0), XLBB_MASK, PWRCOM,         { BO, BI } },
 { "bcrl",    XLLK(19,16,1), XLBB_MASK, PWRCOM,         { BO, BI } },
 { "bclre",   XLLK(19,17,0), XLBB_MASK, BOOKE64,        { BO, BI } },
 { "bcr",     XLLK(19,16,0), XLBB_MASK, PWRCOM,         { BO, BI } },
 { "bcrl",    XLLK(19,16,1), XLBB_MASK, PWRCOM,         { BO, BI } },
 { "bclre",   XLLK(19,17,0), XLBB_MASK, BOOKE64,        { BO, BI } },


@@ -2854,12 +2911,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "crnot",   XL(19,33), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
 { "crnor",   XL(19,33),        XL_MASK,        COM,            { BT, BA, BB } },
 
 { "crnot",   XL(19,33), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
 { "crnor",   XL(19,33),        XL_MASK,        COM,            { BT, BA, BB } },

-{ "rfmci",    X(19,38),  0xffffffff,   PPCRFMCI,       { 0 } },
-
+{ "rfmci",    X(19,38), 0xffffffff,    PPCRFMCI,       { 0 } },

 
 { "rfi",     XL(19,50),        0xffffffff,     COM,            { 0 } },
 
 { "rfi",     XL(19,50),        0xffffffff,     COM,            { 0 } },

-{ "rfci",    XL(19,51),        0xffffffff,     PPC403,         { 0 } },
-{ "rfci",    XL(19,51),        0xffffffff,     BOOKE,          { 0 } },
+{ "rfci",    XL(19,51),        0xffffffff,     PPC403 | BOOKE, { 0 } },

 
 { "rfsvc",   XL(19,82),        0xffffffff,     POWER,          { 0 } },
 
 
 { "rfsvc",   XL(19,82),        0xffffffff,     POWER,          { 0 } },
 


@@ -2887,150 +2942,150 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,    { 0 } },
 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,    { 0 } },
 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },

-{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },

+{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },

 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,  { BI } },
 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4,        { BI } },
 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,  { BI } },
 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4,        { BI } },

-{ "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4,        { BI } },

 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },

+{ "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4,        { BI } },

 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,  { BI } },
 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4,        { BI } },
 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,  { BI } },
 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4,        { BI } },

-{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4,        { BI } },

 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },

+{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4,        { BI } },

 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,  { BI } },
 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,  { BI } },
 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },

-{ "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },

 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },

+{ "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },

 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,  { BI } },
 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,  { BI } },
 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },

-{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },

 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },

+{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },

 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },

-{ "bcctr",   XLLK(19,528,0),     XLYBB_MASK,  PPCCOM,  { BO, BI } },

 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },

-{ "bcctrl",  XLLK(19,528,1),     XLYBB_MASK,  PPCCOM,  { BO, BI } },

 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },
 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,  { BOE, BI } },

+{ "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,  { BO, BI, BH } },
+{ "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,  { BO, BI, BH } },

 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,  { BO, BI } },
 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,  { BO, BI } },
 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64, { BO, BI } },
 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,  { BO, BI } },
 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,  { BO, BI } },
 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64, { BO, BI } },


@@ -3109,9 +3164,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "rldcr",   MDS(30,9,0), MDS_MASK,    PPC64,          { RA, RS, RB, ME6 } },
 { "rldcr.",  MDS(30,9,1), MDS_MASK,    PPC64,          { RA, RS, RB, ME6 } },
 
 { "rldcr",   MDS(30,9,0), MDS_MASK,    PPC64,          { RA, RS, RB, ME6 } },
 { "rldcr.",  MDS(30,9,1), MDS_MASK,    PPC64,          { RA, RS, RB, ME6 } },
 

-{ "cmpw",    XCMPL(31,0,0), XCMPL_MASK, PPCCOM,                { OBF, RA, RB } },
-{ "cmpd",    XCMPL(31,0,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
-{ "cmp",     X(31,0),  XCMP_MASK,      PPCONLY,        { BF, L, RA, RB } },
+{ "cmpw",    XOPL(31,0,0), XCMPL_MASK, PPCCOM,         { OBF, RA, RB } },
+{ "cmpd",    XOPL(31,0,1), XCMPL_MASK, PPC64,          { OBF, RA, RB } },
+{ "cmp",     X(31,0),  XCMP_MASK,      PPC,            { BF, L, RA, RB } },

 { "cmp",     X(31,0),  XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
 
 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,                { RA, RB } },
 { "cmp",     X(31,0),  XCMPL_MASK,     PWRCOM,         { BF, RA, RB } },
 
 { "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,                { RA, RB } },


@@ -3179,15 +3234,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "iseleq",  X(31,79),      X_MASK,    PPCISEL,        { RT, RA, RB } },
 { "isel",    XISEL(31,15),  XISEL_MASK,        PPCISEL,        { RT, RA, RB, CRB } },
 
 { "iseleq",  X(31,79),      X_MASK,    PPCISEL,        { RT, RA, RB } },
 { "isel",    XISEL(31,15),  XISEL_MASK,        PPCISEL,        { RT, RA, RB, CRB } },
 

-{ "mfcr",    X(31,19), XRARB_MASK,     COM,            { RT } },
+{ "mfocrf",  XFXM(31,19,0,1), XFXFXM_MASK, COM,                { RT, FXM } },
+{ "mfcr",    X(31,19), XRARB_MASK,     NOPOWER4,       { RT } },
+{ "mfcr",    X(31,19), XFXFXM_MASK,    POWER4,         { RT, FXM4 } },

 
 

-{ "lwarx",   X(31,20), X_MASK,         PPC,            { RT, RA, RB } },
+{ "lwarx",   X(31,20), X_MASK,         PPC,            { RT, RA0, RB } },

 
 

-{ "ldx",     X(31,21), X_MASK,         PPC64,          { RT, RA, RB } },
+{ "ldx",     X(31,21), X_MASK,         PPC64,          { RT, RA0, RB } },

 
 { "icbt",    X(31,22), X_MASK,         BOOKE,          { CT, RA, RB } },
 
 { "icbt",    X(31,22), X_MASK,         BOOKE,          { CT, RA, RB } },

+{ "icbt",    X(31,262),        XRT_MASK,       PPC403,         { RA, RB } },

 
 

-{ "lwzx",    X(31,23), X_MASK,         PPCCOM,         { RT, RA, RB } },
+{ "lwzx",    X(31,23), X_MASK,         PPCCOM,         { RT, RA0, RB } },

 { "lx",      X(31,23), X_MASK,         PWRCOM,         { RT, RA, RB } },
 
 { "slw",     XRC(31,24,0), X_MASK,     PPCCOM,         { RA, RS, RB } },
 { "lx",      X(31,23), X_MASK,         PWRCOM,         { RT, RA, RB } },
 
 { "slw",     XRC(31,24,0), X_MASK,     PPCCOM,         { RA, RS, RB } },


@@ -3211,11 +3269,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "icbte",   X(31,30), X_MASK,         BOOKE64,        { CT, RA, RB } },
 
 
 { "icbte",   X(31,30), X_MASK,         BOOKE64,        { CT, RA, RB } },
 

-{ "lwzxe",   X(31,31), X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "lwzxe",   X(31,31), X_MASK,         BOOKE64,        { RT, RA0, RB } },

 
 

-{ "cmplw",   XCMPL(31,32,0), XCMPL_MASK, PPCCOM,       { OBF, RA, RB } },
-{ "cmpld",   XCMPL(31,32,1), XCMPL_MASK, PPC64,                { OBF, RA, RB } },
-{ "cmpl",    X(31,32), XCMP_MASK,       PPCONLY,       { BF, L, RA, RB } },
+{ "cmplw",   XOPL(31,32,0), XCMPL_MASK, PPCCOM,        { OBF, RA, RB } },
+{ "cmpld",   XOPL(31,32,1), XCMPL_MASK, PPC64,         { OBF, RA, RB } },
+{ "cmpl",    X(31,32), XCMP_MASK,       PPC,           { BF, L, RA, RB } },

 { "cmpl",    X(31,32), XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
 
 { "subf",    XO(31,40,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
 { "cmpl",    X(31,32), XCMPL_MASK,      PWRCOM,        { BF, RA, RB } },
 
 { "subf",    XO(31,40,0,0), XO_MASK,   PPC,            { RT, RA, RB } },


@@ -3266,19 +3324,22 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mulhw",   XO(31,75,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
 { "mulhw.",  XO(31,75,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
 
 { "mulhw",   XO(31,75,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
 { "mulhw.",  XO(31,75,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
 

+{ "dlmzb",   XRC(31,78,0),  X_MASK,    PPC403|PPC440,  { RA, RS, RB } },
+{ "dlmzb.",  XRC(31,78,1),  X_MASK,    PPC403|PPC440,  { RA, RS, RB } },
+

 { "mtsrd",   X(31,82), XRB_MASK|(1<<20), PPC64,        { SR, RS } },
 
 { "mfmsr",   X(31,83), XRARB_MASK,     COM,            { RT } },
 
 { "mtsrd",   X(31,82), XRB_MASK|(1<<20), PPC64,        { SR, RS } },
 
 { "mfmsr",   X(31,83), XRARB_MASK,     COM,            { RT } },
 

-{ "ldarx",   X(31,84), X_MASK,         PPC64,          { RT, RA, RB } },
+{ "ldarx",   X(31,84), X_MASK,         PPC64,          { RT, RA0, RB } },

 
 { "dcbf",    X(31,86), XRT_MASK,       PPC,            { RA, RB } },
 
 
 { "dcbf",    X(31,86), XRT_MASK,       PPC,            { RA, RB } },
 

-{ "lbzx",    X(31,87), X_MASK,         COM,            { RT, RA, RB } },
+{ "lbzx",    X(31,87), X_MASK,         COM,            { RT, RA0, RB } },

 
 { "dcbfe",   X(31,94), XRT_MASK,       BOOKE64,        { RA, RB } },
 
 
 { "dcbfe",   X(31,94), XRT_MASK,       BOOKE64,        { RA, RB } },
 

-{ "lbzxe",   X(31,95), X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "lbzxe",   X(31,95), X_MASK,         BOOKE64,        { RT, RA0, RB } },

 
 { "neg",     XO(31,104,0,0), XORB_MASK,        COM,            { RT, RA } },
 { "neg.",    XO(31,104,0,1), XORB_MASK,        COM,            { RT, RA } },
 
 { "neg",     XO(31,104,0,0), XORB_MASK,        COM,            { RT, RA } },
 { "neg.",    XO(31,104,0,1), XORB_MASK,        COM,            { RT, RA } },


@@ -3301,12 +3362,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "not.",    XRC(31,124,1), X_MASK,    COM,            { RA, RS, RBS } },
 { "nor.",    XRC(31,124,1), X_MASK,    COM,            { RA, RS, RB } },
 
 { "not.",    XRC(31,124,1), X_MASK,    COM,            { RA, RS, RBS } },
 { "nor.",    XRC(31,124,1), X_MASK,    COM,            { RA, RS, RB } },
 

-{ "lwarxe",  X(31,126),        X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "lwarxe",  X(31,126),        X_MASK,         BOOKE64,        { RT, RA0, RB } },

 
 { "lbzuxe",  X(31,127),        X_MASK,         BOOKE64,        { RT, RAL, RB } },
 
 
 { "lbzuxe",  X(31,127),        X_MASK,         BOOKE64,        { RT, RAL, RB } },
 

-{ "wrtee",   X(31,131),        XRARB_MASK,     PPC403,         { RS } },
-{ "wrtee",   X(31,131),        XRARB_MASK,     BOOKE,          { RS } },
+{ "wrtee",   X(31,131),        XRARB_MASK,     PPC403 | BOOKE, { RS } },

 
 { "dcbtstls",X(31,134),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
 
 
 { "dcbtstls",X(31,134),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
 


@@ -3330,21 +3390,22 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "dcbtstlse",X(31,142),X_MASK,                PPCCHLK64,      { CT, RA, RB }},
 
 
 { "dcbtstlse",X(31,142),X_MASK,                PPCCHLK64,      { CT, RA, RB }},
 

-{ "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,     { RS }},
+{ "mtocrf",  XFXM(31,144,0,1), XFXFXM_MASK, COM,       { FXM, RS } },
+{ "mtcr",    XFXM(31,144,0xff,0), XRARB_MASK, COM,     { RS }},

 { "mtcrf",   X(31,144),        XFXFXM_MASK,    COM,            { FXM, RS } },
 
 { "mtmsr",   X(31,146),        XRARB_MASK,     COM,            { RS } },
 
 { "mtcrf",   X(31,144),        XFXFXM_MASK,    COM,            { FXM, RS } },
 
 { "mtmsr",   X(31,146),        XRARB_MASK,     COM,            { RS } },
 

-{ "stdx",    X(31,149), X_MASK,                PPC64,          { RS, RA, RB } },
+{ "stdx",    X(31,149), X_MASK,                PPC64,          { RS, RA0, RB } },

 
 

-{ "stwcx.",  XRC(31,150,1), X_MASK,    PPC,            { RS, RA, RB } },
+{ "stwcx.",  XRC(31,150,1), X_MASK,    PPC,            { RS, RA0, RB } },

 
 

-{ "stwx",    X(31,151), X_MASK,                PPCCOM,         { RS, RA, RB } },
+{ "stwx",    X(31,151), X_MASK,                PPCCOM,         { RS, RA0, RB } },

 { "stx",     X(31,151), X_MASK,                PWRCOM,         { RS, RA, RB } },
 
 { "stx",     X(31,151), X_MASK,                PWRCOM,         { RS, RA, RB } },
 

-{ "stwcxe.", XRC(31,158,1), X_MASK,    BOOKE64,        { RS, RA, RB } },
+{ "stwcxe.", XRC(31,158,1), X_MASK,    BOOKE64,        { RS, RA0, RB } },

 
 

-{ "stwxe",   X(31,159), X_MASK,                BOOKE64,        { RS, RA, RB } },
+{ "stwxe",   X(31,159), X_MASK,                BOOKE64,        { RS, RA0, RB } },

 
 { "slq",     XRC(31,152,0), X_MASK,    M601,           { RA, RS, RB } },
 { "slq.",    XRC(31,152,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "slq",     XRC(31,152,0), X_MASK,    M601,           { RA, RS, RB } },
 { "slq.",    XRC(31,152,1), X_MASK,    M601,           { RA, RS, RB } },


@@ -3352,8 +3413,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sle",     XRC(31,153,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sle.",    XRC(31,153,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "sle",     XRC(31,153,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sle.",    XRC(31,153,1), X_MASK,    M601,           { RA, RS, RB } },
 

-{ "wrteei",  X(31,163),        XE_MASK,        PPC403,         { E } },
-{ "wrteei",  X(31,163),        XE_MASK,        BOOKE,          { E } },
+{ "wrteei",  X(31,163),        XE_MASK,        PPC403 | BOOKE, { E } },

 
 { "dcbtls",  X(31,166),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
 { "dcbtlse", X(31,174),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},
 
 { "dcbtls",  X(31,166),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
 { "dcbtlse", X(31,174),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},


@@ -3363,7 +3423,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stdux",   X(31,181),        X_MASK,         PPC64,          { RS, RAS, RB } },
 
 { "stwux",   X(31,183),        X_MASK,         PPCCOM,         { RS, RAS, RB } },
 { "stdux",   X(31,181),        X_MASK,         PPC64,          { RS, RAS, RB } },
 
 { "stwux",   X(31,183),        X_MASK,         PPCCOM,         { RS, RAS, RB } },

-{ "stux",    X(31,183),        X_MASK,         PWRCOM,         { RS, RA, RB } },
+{ "stux",    X(31,183),        X_MASK,         PWRCOM,         { RS, RA0, RB } },

 
 { "sliq",    XRC(31,184,0), X_MASK,    M601,           { RA, RS, SH } },
 { "sliq.",   XRC(31,184,1), X_MASK,    M601,           { RA, RS, SH } },
 
 { "sliq",    XRC(31,184,0), X_MASK,    M601,           { RA, RS, SH } },
 { "sliq.",   XRC(31,184,1), X_MASK,    M601,           { RA, RS, SH } },


@@ -3390,9 +3450,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mtsr",    X(31,210),        XRB_MASK|(1<<20), COM32,        { SR, RS } },
 
 
 { "mtsr",    X(31,210),        XRB_MASK|(1<<20), COM32,        { SR, RS } },
 

-{ "stdcx.",  XRC(31,214,1), X_MASK,    PPC64,          { RS, RA, RB } },
+{ "stdcx.",  XRC(31,214,1), X_MASK,    PPC64,          { RS, RA0, RB } },

 
 

-{ "stbx",    X(31,215),        X_MASK,         COM,            { RS, RA, RB } },
+{ "stbx",    X(31,215),        X_MASK,         COM,            { RS, RA0, RB } },

 
 { "sllq",    XRC(31,216,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sllq.",   XRC(31,216,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "sllq",    XRC(31,216,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sllq.",   XRC(31,216,1), X_MASK,    M601,           { RA, RS, RB } },


@@ -3400,7 +3460,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sleq",    XRC(31,217,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sleq.",   XRC(31,217,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "sleq",    XRC(31,217,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sleq.",   XRC(31,217,1), X_MASK,    M601,           { RA, RS, RB } },
 

-{ "stbxe",   X(31,223),        X_MASK,         BOOKE64,        { RS, RA, RB } },
+{ "stbxe",   X(31,223),        X_MASK,         BOOKE64,        { RS, RA0, RB } },

 
 { "icblc",   X(31,230),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
 
 
 { "icblc",   X(31,230),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
 


@@ -3440,7 +3500,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtsrin",  X(31,242),        XRA_MASK,       PPC32,          { RS, RB } },
 { "mtsri",   X(31,242),        XRA_MASK,       POWER32,        { RS, RB } },
 
 { "mtsrin",  X(31,242),        XRA_MASK,       PPC32,          { RS, RB } },
 { "mtsri",   X(31,242),        XRA_MASK,       POWER32,        { RS, RB } },
 

-{ "dcbtst",  X(31,246),        XRT_MASK,       PPC,            { CT, RA, RB } },
+{ "dcbtst",  X(31,246),        X_MASK, PPC,                    { CT, RA, RB } },

 
 { "stbux",   X(31,247),        X_MASK,         COM,            { RS, RAS, RB } },
 
 
 { "stbux",   X(31,247),        X_MASK,         COM,            { RS, RAS, RB } },
 


@@ -3453,8 +3513,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfdcrx",  X(31,259),        X_MASK,         BOOKE,          { RS, RA } },
 
 
 { "mfdcrx",  X(31,259),        X_MASK,         BOOKE,          { RS, RA } },
 

-{ "icbt",    X(31,262),        XRT_MASK,       PPC403,         { RA, RB } },
-

 { "doz",     XO(31,264,0,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "doz.",    XO(31,264,0,1), XO_MASK,  M601,           { RT, RA, RB } },
 { "dozo",    XO(31,264,1,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "doz",     XO(31,264,0,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "doz.",    XO(31,264,0,1), XO_MASK,  M601,           { RT, RA, RB } },
 { "dozo",    XO(31,264,1,0), XO_MASK,  M601,           { RT, RA, RB } },


@@ -3476,19 +3534,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "lscbx",   XRC(31,277,0), X_MASK,    M601,           { RT, RA, RB } },
 { "lscbx.",  XRC(31,277,1), X_MASK,    M601,           { RT, RA, RB } },
 
 { "lscbx",   XRC(31,277,0), X_MASK,    M601,           { RT, RA, RB } },
 { "lscbx.",  XRC(31,277,1), X_MASK,    M601,           { RT, RA, RB } },
 

-{ "dcbt",    X(31,278),        XRT_MASK,       PPC,            { CT, RA, RB } },
+{ "dcbt",    X(31,278),        X_MASK, PPC,                    { CT, RA, RB } },

 
 

-{ "lhzx",    X(31,279),        X_MASK,         COM,            { RT, RA, RB } },
+{ "lhzx",    X(31,279),        X_MASK,         COM,            { RT, RA0, RB } },

 
 { "eqv",     XRC(31,284,0), X_MASK,    COM,            { RA, RS, RB } },
 { "eqv.",    XRC(31,284,1), X_MASK,    COM,            { RA, RS, RB } },
 
 { "dcbte",   X(31,286),        X_MASK,         BOOKE64,        { CT, RA, RB } },
 
 
 { "eqv",     XRC(31,284,0), X_MASK,    COM,            { RA, RS, RB } },
 { "eqv.",    XRC(31,284,1), X_MASK,    COM,            { RA, RS, RB } },
 
 { "dcbte",   X(31,286),        X_MASK,         BOOKE64,        { CT, RA, RB } },
 

-{ "lhzxe",   X(31,287),        X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "lhzxe",   X(31,287),        X_MASK,         BOOKE64,        { RT, RA0, RB } },

 
 { "tlbie",   X(31,306),        XRTLRA_MASK,    PPC,            { RB, L } },
 
 { "tlbie",   X(31,306),        XRTLRA_MASK,    PPC,            { RB, L } },

-{ "tlbi",    X(31,306),        XRT_MASK,       POWER,          { RA, RB } },
+{ "tlbi",    X(31,306),        XRT_MASK,       POWER,          { RA0, RB } },

 
 { "eciwx",   X(31,310), X_MASK,                PPC,            { RT, RA, RB } },
 
 
 { "eciwx",   X(31,310), X_MASK,                PPC,            { RT, RA, RB } },
 


@@ -3533,8 +3591,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,     { RT } },
 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,     { RT } },
 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,     { RT } },
 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,     { RT } },
 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,     { RT } },
 { "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,     { RT } },

-{ "mfdcr",    X(31,323),       X_MASK,         PPC403,         { RT, SPR } },
-{ "mfdcr",    X(31,323),       X_MASK,         BOOKE,          { RT, SPR } },
+{ "mfdcr",    X(31,323),       X_MASK, PPC403 | BOOKE, { RT, SPR } },

 
 { "div",     XO(31,331,0,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "div.",    XO(31,331,0,1), XO_MASK,  M601,           { RT, RA, RB } },
 
 { "div",     XO(31,331,0,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "div.",    XO(31,331,0,1), XO_MASK,  M601,           { RT, RA, RB } },


@@ -3548,21 +3605,24 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,     { RT } },
 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,     { RT } },
 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,  { RT } },
 { "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,     { RT } },
 { "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,     { RT } },
 { "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,  { RT } },

+{ "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,  { RT } },

 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,     { RT } },
 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,     { RT } },
 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,   { RT } },
 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,     { RT } },
 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,     { RT } },
 { "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,     { RT } },
 { "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,     { RT } },
 { "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,   { RT } },
 { "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,     { RT } },
 { "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,     { RT } },

-{ "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,  { RT } },

 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,   { RT } },
 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,     { RT } },
 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,     { RT } },
 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,     { RT } },
 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
 { "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,   { RT } },
 { "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,     { RT } },
 { "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,     { RT } },
 { "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,     { RT } },
 { "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },

+{ "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,  { RT } },

 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
 { "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
 { "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
 { "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },

+{ "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,  { RT } },

 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
 { "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },

+{ "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,  { RT } },

 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,  { RT } },
 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,  { RT } },
 { "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
 { "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,  { RT } },
 { "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,  { RT } },


@@ -3583,11 +3643,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,  { RT } },
 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,  { RT } },
 { "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,  { RT } },
 { "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
 { "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,  { RT } },

+{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, BOOKE,   { RT } },

 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,  { RT } },
 { "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,  { RT } },

+{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, BOOKE,   { RT } },

 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,  { RT } },
 { "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,  { RT } },

+{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, BOOKE,   { RT } },

 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,  { RT } },
 { "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,  { RT } },

+{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, BOOKE,   { RT } },
+{ "mftb",       X(31,371),        X_MASK,    CLASSIC,  { RT, TBR } },

 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
 { "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },

+{ "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC, { RT } },

 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
 { "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },

+{ "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC, { RT } },

 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
 { "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,    { RT, SPRG } },
 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,     { RT } },
 { "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
 { "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,    { RT, SPRG } },
 { "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,     { RT } },


@@ -3599,19 +3666,32 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,     { RT } },
 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
 { "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
 { "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,     { RT } },
 { "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,  { RT } },

 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
 { "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,  { RT } },

 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
 { "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,  { RT } },

 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
 { "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
 { "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,  { RT } },

 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
 { "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,  { RT } },

 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
 { "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,  { RT } },

 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
 { "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,  { RT } },

 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
 { "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,  { RT } },

 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
 { "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,  { RT } },

 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
 { "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,  { RT } },

 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
 { "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },

+{ "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,  { RT } },

 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
 { "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },

+{ "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,  { RT } },

 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
 { "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },

+{ "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,  { RT } },

 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
 { "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
 { "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
 { "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },


@@ -3631,6 +3711,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,  { RT } },
 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
 { "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,  { RT } },
 { "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
 { "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },

+{ "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,  { RT } },
+{ "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,  { RT } },
+{ "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,  { RT } },
+{ "mfivor35",   XSPR(31,339,531),  XSPR_MASK, PPCPMR,  { RT } },

 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
 { "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
 { "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
 { "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },


@@ -3640,10 +3724,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,  { RT } },
 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,  { RT } },
 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,  { RT } },
 { "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,  { RT } },
 { "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,  { RT } },
 { "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,  { RT } },

-{ "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,  { RT } },

 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
 { "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },

+{ "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,  { RT } },

 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
 { "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
 { "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },

+{ "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },

 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,  { RT } },
 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,  { RT } },
 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,  { RT } },
 { "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,  { RT } },
 { "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,  { RT } },
 { "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,  { RT } },


@@ -3674,12 +3759,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
 { "mfzpr",     XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
 { "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
 { "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
 { "mfzpr",     XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },

-{ "mfpid",     XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },

 { "mfccr0",    XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },
 { "mfccr0",    XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },

-{ "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,  { RT } },
-{ "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,  { RT } },
-{ "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,  { RT } },
-{ "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,  { RT } },

 { "mfmmcr0",   XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
 { "mfpmc1",    XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
 { "mfsgr",     XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },
 { "mfmmcr0",   XSPR(31,339,952),  XSPR_MASK, PPC750,   { RT } },
 { "mfpmc1",    XSPR(31,339,953),  XSPR_MASK, PPC750,   { RT } },
 { "mfsgr",     XSPR(31,339,953),  XSPR_MASK, PPC403,   { RT } },


@@ -3690,26 +3770,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfmmcr1",   XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
 { "mfsu0r",    XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
 { "mfpmc3",    XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
 { "mfmmcr1",   XSPR(31,339,956),  XSPR_MASK, PPC750,   { RT } },
 { "mfsu0r",    XSPR(31,339,956),  XSPR_MASK, PPC405,   { RT } },
 { "mfpmc3",    XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },

-{ "mfdbcr1",   XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },

 { "mfpmc4",    XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
 { "mfpmc4",    XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
 { "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },

-{ "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,  { RT } },
-{ "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,  { RT } },

 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,  { RT } },
 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,  { RT } },
 { "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,  { RT } },
 { "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,  { RT } },

-{ "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,  { RT } },
-{ "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,  { RT } },

 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,  { RT } },
 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,  { RT } },
 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,  { RT } },
 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,  { RT } },
 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,  { RT } },
 { "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,  { RT } },
 { "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,  { RT } },
 { "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,  { RT } },
 { "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,  { RT } },
 { "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,  { RT } },

-{ "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,  { RT } },
-{ "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,  { RT } },
-{ "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,  { RT } },
-{ "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,  { RT } },
-{ "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,  { RT } },
-{ "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,  { RT } },

 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,  { RT } },
 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,  { RT } },
 { "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
 { "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,  { RT } },
 { "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,  { RT } },


@@ -3723,19 +3792,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,  { RT } },
 { "mfspr",      X(31,339),        X_MASK,    COM,      { RT, SPR } },
 
 { "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,  { RT } },
 { "mfspr",      X(31,339),        X_MASK,    COM,      { RT, SPR } },
 

-{ "lwax",    X(31,341),        X_MASK,         PPC64,          { RT, RA, RB } },
+{ "lwax",    X(31,341),        X_MASK,         PPC64,          { RT, RA0, RB } },

 
 { "dst",     XDSS(31,342,0), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 { "dstt",    XDSS(31,342,1), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 
 
 { "dst",     XDSS(31,342,0), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 { "dstt",    XDSS(31,342,1), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 

-{ "lhax",    X(31,343),        X_MASK,         COM,            { RT, RA, RB } },
+{ "lhax",    X(31,343),        X_MASK,         COM,            { RT, RA0, RB } },

 
 

-{ "lhaxe",   X(31,351),        X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "lhaxe",   X(31,351),        X_MASK,         BOOKE64,        { RT, RA0, RB } },

 
 { "dstst",   XDSS(31,374,0), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 { "dststt",  XDSS(31,374,1), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 
 
 { "dstst",   XDSS(31,374,0), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 { "dststt",  XDSS(31,374,1), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 

-{ "dccci",   X(31,454),        XRT_MASK,       PPC403,         { RA, RB } },
+{ "dccci",   X(31,454),        XRT_MASK,       PPC403|PPC440,  { RA, RB } },

 
 { "abs",     XO(31,360,0,0), XORB_MASK, M601,          { RT, RA } },
 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,          { RT, RA } },
 
 { "abs",     XO(31,360,0,0), XORB_MASK, M601,          { RT, RA } },
 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,          { RT, RA } },


@@ -3749,10 +3818,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "tlbia",   X(31,370),        0xffffffff,     PPC,            { 0 } },
 
 
 { "tlbia",   X(31,370),        0xffffffff,     PPC,            { 0 } },
 

-{ "mftbl",   XSPR(31,371,268), XSPR_MASK, CLASSIC,     { RT } },
-{ "mftbu",   XSPR(31,371,269), XSPR_MASK, CLASSIC,     { RT } },
-{ "mftb",    X(31,371),        X_MASK,         CLASSIC,        { RT, TBR } },
-

 { "lwaux",   X(31,373),        X_MASK,         PPC64,          { RT, RAL, RB } },
 
 { "lhaux",   X(31,375),        X_MASK,         COM,            { RT, RAL, RB } },
 { "lwaux",   X(31,373),        X_MASK,         PPC64,          { RT, RAL, RB } },
 
 { "lhaux",   X(31,375),        X_MASK,         COM,            { RT, RAL, RB } },


@@ -3773,7 +3838,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "slbmte",  X(31,402), XRA_MASK,      PPC64,          { RS, RB } },
 
 
 { "slbmte",  X(31,402), XRA_MASK,      PPC64,          { RS, RB } },
 

-{ "sthx",    X(31,407),        X_MASK,         COM,            { RS, RA, RB } },
+{ "sthx",    X(31,407),        X_MASK,         COM,            { RS, RA0, RB } },

 
 { "lfqx",    X(31,791),        X_MASK,         POWER2,         { FRT, RA, RB } },
 
 
 { "lfqx",    X(31,791),        X_MASK,         POWER2,         { FRT, RA, RB } },
 


@@ -3789,7 +3854,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sradi",   XS(31,413,0), XS_MASK,    PPC64,          { RA, RS, SH6 } },
 { "sradi.",  XS(31,413,1), XS_MASK,    PPC64,          { RA, RS, SH6 } },
 
 { "sradi",   XS(31,413,0), XS_MASK,    PPC64,          { RA, RS, SH6 } },
 { "sradi.",  XS(31,413,1), XS_MASK,    PPC64,          { RA, RS, SH6 } },
 

-{ "sthxe",   X(31,415),        X_MASK,         BOOKE64,        { RS, RA, RB } },
+{ "sthxe",   X(31,415),        X_MASK,         BOOKE64,        { RS, RA0, RB } },

 
 { "slbie",   X(31,434),        XRTRA_MASK,     PPC64,          { RB } },
 
 
 { "slbie",   X(31,434),        XRTRA_MASK,     PPC64,          { RB } },
 


@@ -3804,42 +3869,41 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mr.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RBS } },
 { "or.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RB } },
 
 { "mr.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RBS } },
 { "or.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RB } },
 

-{ "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,     { RT } },
-{ "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,     { RT } },
-{ "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,     { RT } },
-{ "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,     { RT } },
-{ "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,     { RT } },
-{ "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,     { RT } },
-{ "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,     { RT } },
-{ "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,     { RT } },
-{ "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,     { RT } },
-{ "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,     { RT } },
-{ "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,     { RT } },
-{ "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,     { RT } },
-{ "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,     { RT } },
-{ "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,     { RT } },
-{ "mtdcr",    X(31,451),       X_MASK,         PPC403,         { SPR, RS } },
-{ "mtdcr",    X(31,451),       X_MASK,         BOOKE,          { SPR, RS } },
+{ "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,     { RS } },
+{ "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,     { RS } },
+{ "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,     { RS } },
+{ "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,     { RS } },
+{ "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,     { RS } },
+{ "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,     { RS } },
+{ "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,     { RS } },
+{ "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,     { RS } },
+{ "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,     { RS } },
+{ "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,     { RS } },
+{ "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,     { RS } },
+{ "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,     { RS } },
+{ "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,     { RS } },
+{ "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,     { RS } },
+{ "mtdcr",    X(31,451),       X_MASK, PPC403 | BOOKE, { SPR, RS } },

 
 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,       { RT, RA } },
 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,      { RT, RA } },
 
 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,       { RT, RA } },
 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,      { RT, RA } },


@@ -3872,61 +3936,73 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,      { RS } },
 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,      { RS } },
 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
 { "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,      { RS } },
 { "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,      { RS } },
 { "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },

+{ "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,   { RS } },

 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
 { "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
 { "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
 { "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
 { "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },

+{ "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,   { RS } },

 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
 { "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },

+{ "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,   { RS } },

 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
 { "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },

-{ "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,   { RT } },
-{ "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,   { RT } },
-{ "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,   { RT } },
-{ "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,   { RT } },
-{ "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,   { RT } },
-{ "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,   { RT } },
-{ "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,   { RT } },
-{ "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,   { RT } },
-{ "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,   { RT } },
+{ "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,   { RS } },
+{ "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,   { RS } },
+{ "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,   { RS } },
+{ "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,   { RS } },
+{ "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,   { RS } },
+{ "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,   { RS } },
+{ "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,   { RS } },
+{ "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,   { RS } },
+{ "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,   { RS } },

 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
 { "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,      { SPRG, RS } },
 { "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
 { "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,      { SPRG, RS } },

-{ "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,      { RT } },
-{ "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,      { RT } },
-{ "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,      { RT } },
-{ "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,      { RT } },
-{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405,   { RT } },
-{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, BOOKE,     { RS } },
-{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405,   { RT } },
-{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, BOOKE,     { RS } },
-{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405,   { RT } },
-{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, BOOKE,     { RS } },
-{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405,   { RT } },
-{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,      { RS } },
+{ "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,      { RS } },
+{ "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,      { RS } },
+{ "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,      { RS } },
+{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
+{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },

 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,    { RS } },
 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,      { RS } },
 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,      { RS } },
 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,      { RS } },
 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
 { "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,    { RS } },
 { "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,      { RS } },
 { "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,      { RS } },
 { "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,      { RS } },
 { "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,   { RS } },

 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
 { "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,   { RS } },

 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
 { "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,   { RS } },

 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
 { "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
 { "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,   { RS } },

 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
 { "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,   { RS } },

 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
 { "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,   { RS } },

 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
 { "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,   { RS } },

 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
 { "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,   { RS } },

 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
 { "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,   { RS } },

 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
 { "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,   { RS } },

 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
 { "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },

+{ "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,   { RS } },

 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
 { "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },

+{ "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,   { RS } },

 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
 { "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },

+{ "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,   { RS } },

 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
 { "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
 { "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
 { "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },


@@ -3946,6 +4022,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
 { "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
 { "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
 { "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },

+{ "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,   { RS } },
+{ "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,   { RS } },
+{ "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,   { RS } },
+{ "mtivor35",  XSPR(31,467,531),  XSPR_MASK, PPCPMR,   { RS } },

 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
 { "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
 { "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
 { "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },


@@ -3953,61 +4033,45 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
 { "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
 { "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
 { "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },

-{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RT } },
-{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RT } },
-{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RT } },
-{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RT } },
-{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RT } },
-{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RT } },
-{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RT } },
-{ "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,   { RT } },
-{ "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,   { RT } },
-{ "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,   { RT } },
-{ "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,   { RT } },
-{ "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,   { RT } },
-{ "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,   { RT } },
-{ "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,   { RT } },
-{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RT } },
-{ "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,   { RT } },
-{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RT } },
-{ "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,   { RT } },
-{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RT } },
-{ "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,   { RT } },
-{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RT } },
-{ "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,   { RT } },
-{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RT } },
-{ "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,   { RT } },
-{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RT } },
-{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RT } },
-{ "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,   { RT } },
-{ "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,   { RT } },
-{ "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,   { RT } },
-{ "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,   { RT } },
-{ "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,   { RT } },
-{ "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,   { RT } },
-{ "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,   { RT } },
-{ "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,   { RT } },
-{ "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,   { RT } },
-{ "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,   { RT } },
-{ "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,   { RT } },
-{ "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,   { RT } },
-{ "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,   { RT } },
-{ "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,   { RT } },
-{ "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,   { RT } },
-{ "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,   { RT } },
-{ "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,   { RT } },
-{ "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,   { RT } },
-{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RT } },
-{ "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,   { RT } },
-{ "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,   { RT } },
-{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RT } },
-{ "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,   { RT } },
-{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RT } },
-{ "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,   { RT } },
-{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RT } },
-{ "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,   { RT } },
-{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RT } },
-{ "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,   { RT } },
+{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
+{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },
+{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RS } },
+{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RS } },
+{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RS } },
+{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RS } },
+{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RS } },
+{ "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,   { RS } },
+{ "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,   { RS } },
+{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RS } },
+{ "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,   { RS } },
+{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RS } },
+{ "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,   { RS } },
+{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RS } },
+{ "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,   { RS } },
+{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RS } },
+{ "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,   { RS } },
+{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RS } },
+{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RS } },
+{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RS } },
+{ "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,   { RS } },
+{ "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,   { RS } },
+{ "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,   { RS } },
+{ "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,   { RS } },
+{ "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,   { RS } },
+{ "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,   { RS } },
+{ "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,   { RS } },
+{ "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,   { RS } },
+{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RS } },
+{ "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,   { RS } },
+{ "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,   { RS } },
+{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RS } },
+{ "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,   { RS } },
+{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RS } },
+{ "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,   { RS } },
+{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RS } },
+{ "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,   { RS } },
+{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RS } },
+{ "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,   { RS } },

 { "mtspr",     X(31,467),        X_MASK,    COM,       { SPR, RS } },
 
 { "dcbi",    X(31,470),        XRT_MASK,       PPC,            { RA, RB } },
 { "mtspr",     X(31,467),        X_MASK,    COM,       { SPR, RS } },
 
 { "dcbi",    X(31,470),        XRT_MASK,       PPC,            { RA, RB } },


@@ -4017,7 +4081,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "dcbie",   X(31,478),        XRT_MASK,       BOOKE64,        { RA, RB } },
 
 
 { "dcbie",   X(31,478),        XRT_MASK,       BOOKE64,        { RA, RB } },
 

-{ "dcread",  X(31,486),        X_MASK,         PPC403,         { RT, RA, RB }},
+{ "dcread",  X(31,486),        X_MASK,         PPC403|PPC440,  { RT, RA, RB }},

 
 { "mtpmr",   X(31,462),        X_MASK,         PPCPMR,         { PMR, RS }},
 
 
 { "mtpmr",   X(31,462),        X_MASK,         PPCPMR,         { PMR, RS }},
 


@@ -4058,13 +4122,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "clcs",    X(31,531), XRB_MASK,      M601,           { RT, RA } },
 
 
 { "clcs",    X(31,531), XRB_MASK,      M601,           { RT, RA } },
 

-{ "lswx",    X(31,533),        X_MASK,         PPCCOM,         { RT, RA, RB } },
+{ "lswx",    X(31,533),        X_MASK,         PPCCOM,         { RT, RA0, RB } },

 { "lsx",     X(31,533),        X_MASK,         PWRCOM,         { RT, RA, RB } },
 
 { "lsx",     X(31,533),        X_MASK,         PWRCOM,         { RT, RA, RB } },
 

-{ "lwbrx",   X(31,534),        X_MASK,         PPCCOM,         { RT, RA, RB } },
+{ "lwbrx",   X(31,534),        X_MASK,         PPCCOM,         { RT, RA0, RB } },

 { "lbrx",    X(31,534),        X_MASK,         PWRCOM,         { RT, RA, RB } },
 
 { "lbrx",    X(31,534),        X_MASK,         PWRCOM,         { RT, RA, RB } },
 

-{ "lfsx",    X(31,535),        X_MASK,         COM,            { FRT, RA, RB } },
+{ "lfsx",    X(31,535),        X_MASK,         COM,            { FRT, RA0, RB } },

 
 { "srw",     XRC(31,536,0), X_MASK,    PPCCOM,         { RA, RS, RB } },
 { "sr",      XRC(31,536,0), X_MASK,    PWRCOM,         { RA, RS, RB } },
 
 { "srw",     XRC(31,536,0), X_MASK,    PPCCOM,         { RA, RS, RB } },
 { "sr",      XRC(31,536,0), X_MASK,    PWRCOM,         { RA, RS, RB } },


@@ -4080,11 +4144,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "maskir",  XRC(31,541,0), X_MASK,    M601,           { RA, RS, RB } },
 { "maskir.", XRC(31,541,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "maskir",  XRC(31,541,0), X_MASK,    M601,           { RA, RS, RB } },
 { "maskir.", XRC(31,541,1), X_MASK,    M601,           { RA, RS, RB } },
 

-{ "lwbrxe",  X(31,542),        X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "lwbrxe",  X(31,542),        X_MASK,         BOOKE64,        { RT, RA0, RB } },

 
 

-{ "lfsxe",   X(31,543),        X_MASK,         BOOKE64,        { FRT, RA, RB } },
+{ "lfsxe",   X(31,543),        X_MASK,         BOOKE64,        { FRT, RA0, RB } },

 
 { "bbelr",   X(31,550),        X_MASK,         PPCBRLK,        { 0 }},
 
 { "bbelr",   X(31,550),        X_MASK,         PPCBRLK,        { 0 }},

+

 { "tlbsync", X(31,566),        0xffffffff,     PPC,            { 0 } },
 
 { "lfsux",   X(31,567),        X_MASK,         COM,            { FRT, RAS, RB } },
 { "tlbsync", X(31,566),        0xffffffff,     PPC,            { 0 } },
 
 { "lfsux",   X(31,567),        X_MASK,         COM,            { FRT, RAS, RB } },


@@ -4093,18 +4158,18 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfsr",    X(31,595),        XRB_MASK|(1<<20), COM32,        { RT, SR } },
 
 
 { "mfsr",    X(31,595),        XRB_MASK|(1<<20), COM32,        { RT, SR } },
 

-{ "lswi",    X(31,597),        X_MASK,         PPCCOM,         { RT, RA, NB } },
-{ "lsi",     X(31,597),        X_MASK,         PWRCOM,         { RT, RA, NB } },
+{ "lswi",    X(31,597),        X_MASK,         PPCCOM,         { RT, RA0, NB } },
+{ "lsi",     X(31,597),        X_MASK,         PWRCOM,         { RT, RA0, NB } },

 
 

-{ "lwsync",  XSYNC(31,598,1), 0xffffffff, PPCONLY,     { 0 } },
+{ "lwsync",  XSYNC(31,598,1), 0xffffffff, PPC,         { 0 } },

 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,       { 0 } },
 { "msync",   X(31,598), 0xffffffff,    BOOKE,          { 0 } },
 { "sync",    X(31,598), XSYNC_MASK,    PPCCOM,         { LS } },
 { "dcs",     X(31,598), 0xffffffff,    PWRCOM,         { 0 } },
 
 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,       { 0 } },
 { "msync",   X(31,598), 0xffffffff,    BOOKE,          { 0 } },
 { "sync",    X(31,598), XSYNC_MASK,    PPCCOM,         { LS } },
 { "dcs",     X(31,598), 0xffffffff,    PWRCOM,         { 0 } },
 

-{ "lfdx",    X(31,599), X_MASK,                COM,            { FRT, RA, RB } },
+{ "lfdx",    X(31,599), X_MASK,                COM,            { FRT, RA0, RB } },

 
 

-{ "lfdxe",   X(31,607), X_MASK,                BOOKE64,        { FRT, RA, RB } },
+{ "lfdxe",   X(31,607), X_MASK,                BOOKE64,        { FRT, RA0, RB } },

 
 { "mfsri",   X(31,627), X_MASK,                PWRCOM,         { RT, RA, RB } },
 
 
 { "mfsri",   X(31,627), X_MASK,                PWRCOM,         { RT, RA, RB } },
 


@@ -4116,13 +4181,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mfsrin",  X(31,659), XRA_MASK,      PPC32,          { RT, RB } },
 
 
 { "mfsrin",  X(31,659), XRA_MASK,      PPC32,          { RT, RB } },
 

-{ "stswx",   X(31,661), X_MASK,                PPCCOM,         { RS, RA, RB } },
-{ "stsx",    X(31,661), X_MASK,                PWRCOM,         { RS, RA, RB } },
+{ "stswx",   X(31,661), X_MASK,                PPCCOM,         { RS, RA0, RB } },
+{ "stsx",    X(31,661), X_MASK,                PWRCOM,         { RS, RA0, RB } },

 
 

-{ "stwbrx",  X(31,662), X_MASK,                PPCCOM,         { RS, RA, RB } },
-{ "stbrx",   X(31,662), X_MASK,                PWRCOM,         { RS, RA, RB } },
+{ "stwbrx",  X(31,662), X_MASK,                PPCCOM,         { RS, RA0, RB } },
+{ "stbrx",   X(31,662), X_MASK,                PWRCOM,         { RS, RA0, RB } },

 
 

-{ "stfsx",   X(31,663), X_MASK,                COM,            { FRS, RA, RB } },
+{ "stfsx",   X(31,663), X_MASK,                COM,            { FRS, RA0, RB } },

 
 { "srq",     XRC(31,664,0), X_MASK,    M601,           { RA, RS, RB } },
 { "srq.",    XRC(31,664,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "srq",     XRC(31,664,0), X_MASK,    M601,           { RA, RS, RB } },
 { "srq.",    XRC(31,664,1), X_MASK,    M601,           { RA, RS, RB } },


@@ -4130,9 +4195,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sre",     XRC(31,665,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sre.",    XRC(31,665,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "sre",     XRC(31,665,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sre.",    XRC(31,665,1), X_MASK,    M601,           { RA, RS, RB } },
 

-{ "stwbrxe", X(31,670), X_MASK,                BOOKE64,        { RS, RA, RB } },
+{ "stwbrxe", X(31,670), X_MASK,                BOOKE64,        { RS, RA0, RB } },

 
 

-{ "stfsxe",  X(31,671), X_MASK,                BOOKE64,        { FRS, RA, RB } },
+{ "stfsxe",  X(31,671), X_MASK,                BOOKE64,        { FRS, RA0, RB } },

 
 { "stfsux",  X(31,695),        X_MASK,         COM,            { FRS, RAS, RB } },
 
 
 { "stfsux",  X(31,695),        X_MASK,         COM,            { FRS, RAS, RB } },
 


@@ -4141,10 +4206,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stfsuxe", X(31,703),        X_MASK,         BOOKE64,        { FRS, RAS, RB } },
 
 
 { "stfsuxe", X(31,703),        X_MASK,         BOOKE64,        { FRS, RAS, RB } },
 

-{ "stswi",   X(31,725),        X_MASK,         PPCCOM,         { RS, RA, NB } },
-{ "stsi",    X(31,725),        X_MASK,         PWRCOM,         { RS, RA, NB } },
+{ "stswi",   X(31,725),        X_MASK,         PPCCOM,         { RS, RA0, NB } },
+{ "stsi",    X(31,725),        X_MASK,         PWRCOM,         { RS, RA0, NB } },

 
 

-{ "stfdx",   X(31,727),        X_MASK,         COM,            { FRS, RA, RB } },
+{ "stfdx",   X(31,727),        X_MASK,         COM,            { FRS, RA0, RB } },

 
 { "srlq",    XRC(31,728,0), X_MASK,    M601,           { RA, RS, RB } },
 { "srlq.",   XRC(31,728,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "srlq",    XRC(31,728,0), X_MASK,    M601,           { RA, RS, RB } },
 { "srlq.",   XRC(31,728,1), X_MASK,    M601,           { RA, RS, RB } },


@@ -4152,10 +4217,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "sreq",    XRC(31,729,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sreq.",   XRC(31,729,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "sreq",    XRC(31,729,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sreq.",   XRC(31,729,1), X_MASK,    M601,           { RA, RS, RB } },
 

-{ "stfdxe",  X(31,735),        X_MASK,         BOOKE64,        { FRS, RA, RB } },
+{ "stfdxe",  X(31,735),        X_MASK,         BOOKE64,        { FRS, RA0, RB } },

 
 

-{ "dcba",    X(31,758),        XRT_MASK,       PPC405,         { RA, RB } },
-{ "dcba",    X(31,758),        XRT_MASK,       BOOKE,          { RA, RB } },
+{ "dcba",    X(31,758),        XRT_MASK,       PPC405 | BOOKE, { RA, RB } },

 
 { "stfdux",  X(31,759),        X_MASK,         COM,            { FRS, RAS, RB } },
 
 
 { "stfdux",  X(31,759),        X_MASK,         COM,            { FRS, RAS, RB } },
 


@@ -4169,7 +4233,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "tlbivax", X(31,786),        XRT_MASK,       BOOKE,          { RA, RB } },
 { "tlbivaxe",X(31,787),        XRT_MASK,       BOOKE64,        { RA, RB } },
 
 { "tlbivax", X(31,786),        XRT_MASK,       BOOKE,          { RA, RB } },
 { "tlbivaxe",X(31,787),        XRT_MASK,       BOOKE64,        { RA, RB } },
 

-{ "lhbrx",   X(31,790),        X_MASK,         COM,            { RT, RA, RB } },
+{ "lhbrx",   X(31,790),        X_MASK,         COM,            { RT, RA0, RB } },

 
 { "sraw",    XRC(31,792,0), X_MASK,    PPCCOM,         { RA, RS, RB } },
 { "sra",     XRC(31,792,0), X_MASK,    PWRCOM,         { RA, RS, RB } },
 
 { "sraw",    XRC(31,792,0), X_MASK,    PPCCOM,         { RA, RS, RB } },
 { "sra",     XRC(31,792,0), X_MASK,    PWRCOM,         { RA, RS, RB } },


@@ -4179,10 +4243,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "srad",    XRC(31,794,0), X_MASK,    PPC64,          { RA, RS, RB } },
 { "srad.",   XRC(31,794,1), X_MASK,    PPC64,          { RA, RS, RB } },
 
 { "srad",    XRC(31,794,0), X_MASK,    PPC64,          { RA, RS, RB } },
 { "srad.",   XRC(31,794,1), X_MASK,    PPC64,          { RA, RS, RB } },
 

-{ "lhbrxe",  X(31,798),        X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "lhbrxe",  X(31,798),        X_MASK,         BOOKE64,        { RT, RA0, RB } },

 
 

-{ "ldxe",    X(31,799),        X_MASK,         BOOKE64,        { RT, RA, RB } },
-{ "lduxe",   X(31,831),        X_MASK,         BOOKE64,        { RT, RA, RB } },
+{ "ldxe",    X(31,799),        X_MASK,         BOOKE64,        { RT, RA0, RB } },
+{ "lduxe",   X(31,831),        X_MASK,         BOOKE64,        { RT, RA0, RB } },

 
 { "rac",     X(31,818),        X_MASK,         PWRCOM,         { RT, RA, RB } },
 
 
 { "rac",     X(31,818),        X_MASK,         PWRCOM,         { RT, RA, RB } },
 


@@ -4199,17 +4263,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mbar",    X(31,854),        X_MASK,         BOOKE,          { MO } },
 { "eieio",   X(31,854),        0xffffffff,     PPC,            { 0 } },
 
 { "mbar",    X(31,854),        X_MASK,         BOOKE,          { MO } },
 { "eieio",   X(31,854),        0xffffffff,     PPC,            { 0 } },
 

-{ "tlbsx",   XRC(31,914,0), X_MASK,    PPC403,         { RT, RA, RB } },
-{ "tlbsx.",  XRC(31,914,1), X_MASK,    PPC403,         { RT, RA, RB } },
-

 { "tlbsx",   XRC(31,914,0), X_MASK,    BOOKE,          { RA, RB } },
 { "tlbsx",   XRC(31,914,0), X_MASK,    BOOKE,          { RA, RB } },

+{ "tlbsx",   XRC(31,914,0), X_MASK,    PPC403,         { RT, RA, RB } },

 { "tlbsx.",  XRC(31,914,1), X_MASK,    BOOKE,          { RA, RB } },
 { "tlbsx.",  XRC(31,914,1), X_MASK,    BOOKE,          { RA, RB } },

+{ "tlbsx.",  XRC(31,914,1), X_MASK,    PPC403,         { RT, RA, RB } },

 { "tlbsxe",  XRC(31,915,0), X_MASK,    BOOKE64,        { RA, RB } },
 { "tlbsxe.", XRC(31,915,1), X_MASK,    BOOKE64,        { RA, RB } },
 
 { "slbmfee", X(31,915), XRA_MASK,      PPC64,          { RT, RB } },
 
 { "tlbsxe",  XRC(31,915,0), X_MASK,    BOOKE64,        { RA, RB } },
 { "tlbsxe.", XRC(31,915,1), X_MASK,    BOOKE64,        { RA, RB } },
 
 { "slbmfee", X(31,915), XRA_MASK,      PPC64,          { RT, RB } },
 

-{ "sthbrx",  X(31,918),        X_MASK,         COM,            { RS, RA, RB } },
+{ "sthbrx",  X(31,918),        X_MASK,         COM,            { RS, RA0, RB } },

 
 { "sraq",    XRC(31,920,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sraq.",   XRC(31,920,1), X_MASK,    M601,           { RA, RS, RB } },
 
 { "sraq",    XRC(31,920,0), X_MASK,    M601,           { RA, RS, RB } },
 { "sraq.",   XRC(31,920,1), X_MASK,    M601,           { RA, RS, RB } },


@@ -4222,14 +4285,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "extsh.",  XRC(31,922,1), XRB_MASK,  PPCCOM,         { RA, RS } },
 { "exts.",   XRC(31,922,1), XRB_MASK,  PWRCOM,         { RA, RS } },
 
 { "extsh.",  XRC(31,922,1), XRB_MASK,  PPCCOM,         { RA, RS } },
 { "exts.",   XRC(31,922,1), XRB_MASK,  PWRCOM,         { RA, RS } },
 

-{ "sthbrxe", X(31,926),        X_MASK,         BOOKE64,        { RS, RA, RB } },
-
-{ "stdxe",   X(31,927), X_MASK,                BOOKE64,        { RS, RA, RB } },
+{ "sthbrxe", X(31,926),        X_MASK,         BOOKE64,        { RS, RA0, RB } },

 
 

-{ "tlbre",   X(31,946),        X_MASK,         BOOKE,          { 0 } },
+{ "stdxe",   X(31,927), X_MASK,                BOOKE64,        { RS, RA0, RB } },

 
 { "tlbrehi", XTLB(31,946,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbrelo", XTLB(31,946,1), XTLB_MASK,        PPC403,         { RT, RA } },
 
 { "tlbrehi", XTLB(31,946,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbrelo", XTLB(31,946,1), XTLB_MASK,        PPC403,         { RT, RA } },

+{ "tlbre",   X(31,946),        X_MASK,         BOOKE,          { 0 } },

 { "tlbre",   X(31,946),        X_MASK,         PPC403,         { RS, RA, SH } },
 
 { "sraiq",   XRC(31,952,0), X_MASK,    M601,           { RA, RS, SH } },
 { "tlbre",   X(31,946),        X_MASK,         PPC403,         { RS, RA, SH } },
 
 { "sraiq",   XRC(31,952,0), X_MASK,    M601,           { RA, RS, SH } },


@@ -4240,30 +4302,28 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stduxe",  X(31,959),        X_MASK,         BOOKE64,        { RS, RAS, RB } },
 
 
 { "stduxe",  X(31,959),        X_MASK,         BOOKE64,        { RS, RAS, RB } },
 

-{ "iccci",   X(31,966),        XRT_MASK,       PPC403,         { RA, RB } },
-
-{ "tlbwe",   X(31,978),        X_MASK,         BOOKE,          { 0 } },
-
-{ "tlbld",   X(31,978),        XRTRA_MASK,     PPC,            { RB } },
+{ "iccci",   X(31,966),        XRT_MASK,       PPC403|PPC440,  { RA, RB } },

 
 { "tlbwehi", XTLB(31,978,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,        PPC403,         { RT, RA } },
 
 { "tlbwehi", XTLB(31,978,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,        PPC403,         { RT, RA } },

-{ "tlbwe",   X(31,978),        X_MASK,         PPC403,         { RS, RA, SH } },
+{ "tlbwe",   X(31,978),        X_MASK,         PPC403|BOOKE,   { RSO, RAOPT, SHO } },
+{ "tlbld",   X(31,978),        XRTRA_MASK,     PPC,            { RB } },

 
 { "icbi",    X(31,982),        XRT_MASK,       PPC,            { RA, RB } },
 
 
 { "icbi",    X(31,982),        XRT_MASK,       PPC,            { RA, RB } },
 

-{ "stfiwx",  X(31,983),        X_MASK,         PPC,            { FRS, RA, RB } },
+{ "stfiwx",  X(31,983),        X_MASK,         PPC,            { FRS, RA0, RB } },

 
 { "extsw",   XRC(31,986,0), XRB_MASK,  PPC64 | BOOKE64,{ RA, RS } },
 { "extsw.",  XRC(31,986,1), XRB_MASK,  PPC64,          { RA, RS } },
 
 
 { "extsw",   XRC(31,986,0), XRB_MASK,  PPC64 | BOOKE64,{ RA, RS } },
 { "extsw.",  XRC(31,986,1), XRB_MASK,  PPC64,          { RA, RS } },
 

-{ "icread",  X(31,998),        XRT_MASK,       PPC403,         { RA, RB } },
+{ "icread",  X(31,998),        XRT_MASK,       PPC403|PPC440,  { RA, RB } },

 
 { "icbie",   X(31,990),        XRT_MASK,       BOOKE64,        { RA, RB } },
 
 { "icbie",   X(31,990),        XRT_MASK,       BOOKE64,        { RA, RB } },

-{ "stfiwxe", X(31,991),        X_MASK,         BOOKE64,        { FRS, RA, RB } },
+{ "stfiwxe", X(31,991),        X_MASK,         BOOKE64,        { FRS, RA0, RB } },

 
 { "tlbli",   X(31,1010), XRTRA_MASK,   PPC,            { RB } },
 
 
 { "tlbli",   X(31,1010), XRTRA_MASK,   PPC,            { RB } },
 

+{ "dcbzl",   XOPL(31,1014,1), XRT_MASK,POWER4,            { RA, RB } },

 { "dcbz",    X(31,1014), XRT_MASK,     PPC,            { RA, RB } },
 { "dclz",    X(31,1014), XRT_MASK,     PPC,            { RA, RB } },
 
 { "dcbz",    X(31,1014), XRT_MASK,     PPC,            { RA, RB } },
 { "dclz",    X(31,1014), XRT_MASK,     PPC,            { RA, RB } },
 


@@ -4282,84 +4342,86 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stvx",    X(31, 231), X_MASK,       PPCVEC,         { VS, RA, RB } },
 { "stvxl",   X(31, 487), X_MASK,       PPCVEC,         { VS, RA, RB } },
 
 { "stvx",    X(31, 231), X_MASK,       PPCVEC,         { VS, RA, RB } },
 { "stvxl",   X(31, 487), X_MASK,       PPCVEC,         { VS, RA, RB } },
 

-{ "lwz",     OP(32),   OP_MASK,        PPCCOM,         { RT, D, RA } },
-{ "l",      OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },
+{ "lwz",     OP(32),   OP_MASK,        PPCCOM,         { RT, D, RA0 } },
+{ "l",      OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },

 
 { "lwzu",    OP(33),   OP_MASK,        PPCCOM,         { RT, D, RAL } },
 
 { "lwzu",    OP(33),   OP_MASK,        PPCCOM,         { RT, D, RAL } },

-{ "lu",      OP(33),   OP_MASK,        PWRCOM,         { RT, D, RA } },
+{ "lu",      OP(33),   OP_MASK,        PWRCOM,         { RT, D, RA0 } },

 
 

-{ "lbz",     OP(34),   OP_MASK,        COM,            { RT, D, RA } },
+{ "lbz",     OP(34),   OP_MASK,        COM,            { RT, D, RA0 } },

 
 { "lbzu",    OP(35),   OP_MASK,        COM,            { RT, D, RAL } },
 
 
 { "lbzu",    OP(35),   OP_MASK,        COM,            { RT, D, RAL } },
 

-{ "stw",     OP(36),   OP_MASK,        PPCCOM,         { RS, D, RA } },
-{ "st",      OP(36),   OP_MASK,        PWRCOM,         { RS, D, RA } },
+{ "stw",     OP(36),   OP_MASK,        PPCCOM,         { RS, D, RA0 } },
+{ "st",      OP(36),   OP_MASK,        PWRCOM,         { RS, D, RA0 } },

 
 { "stwu",    OP(37),   OP_MASK,        PPCCOM,         { RS, D, RAS } },
 
 { "stwu",    OP(37),   OP_MASK,        PPCCOM,         { RS, D, RAS } },

-{ "stu",     OP(37),   OP_MASK,        PWRCOM,         { RS, D, RA } },
+{ "stu",     OP(37),   OP_MASK,        PWRCOM,         { RS, D, RA0 } },

 
 

-{ "stb",     OP(38),   OP_MASK,        COM,            { RS, D, RA } },
+{ "stb",     OP(38),   OP_MASK,        COM,            { RS, D, RA0 } },

 
 { "stbu",    OP(39),   OP_MASK,        COM,            { RS, D, RAS } },
 
 
 { "stbu",    OP(39),   OP_MASK,        COM,            { RS, D, RAS } },
 

-{ "lhz",     OP(40),   OP_MASK,        COM,            { RT, D, RA } },
+{ "lhz",     OP(40),   OP_MASK,        COM,            { RT, D, RA0 } },

 
 { "lhzu",    OP(41),   OP_MASK,        COM,            { RT, D, RAL } },
 
 
 { "lhzu",    OP(41),   OP_MASK,        COM,            { RT, D, RAL } },
 

-{ "lha",     OP(42),   OP_MASK,        COM,            { RT, D, RA } },
+{ "lha",     OP(42),   OP_MASK,        COM,            { RT, D, RA0 } },

 
 { "lhau",    OP(43),   OP_MASK,        COM,            { RT, D, RAL } },
 
 
 { "lhau",    OP(43),   OP_MASK,        COM,            { RT, D, RAL } },
 

-{ "sth",     OP(44),   OP_MASK,        COM,            { RS, D, RA } },
+{ "sth",     OP(44),   OP_MASK,        COM,            { RS, D, RA0 } },

 
 { "sthu",    OP(45),   OP_MASK,        COM,            { RS, D, RAS } },
 
 { "lmw",     OP(46),   OP_MASK,        PPCCOM,         { RT, D, RAM } },
 
 { "sthu",    OP(45),   OP_MASK,        COM,            { RS, D, RAS } },
 
 { "lmw",     OP(46),   OP_MASK,        PPCCOM,         { RT, D, RAM } },

-{ "lm",      OP(46),   OP_MASK,        PWRCOM,         { RT, D, RA } },
+{ "lm",      OP(46),   OP_MASK,        PWRCOM,         { RT, D, RA0 } },

 
 

-{ "stmw",    OP(47),   OP_MASK,        PPCCOM,         { RS, D, RA } },
-{ "stm",     OP(47),   OP_MASK,        PWRCOM,         { RS, D, RA } },
+{ "stmw",    OP(47),   OP_MASK,        PPCCOM,         { RS, D, RA0 } },
+{ "stm",     OP(47),   OP_MASK,        PWRCOM,         { RS, D, RA0 } },

 
 

-{ "lfs",     OP(48),   OP_MASK,        COM,            { FRT, D, RA } },
+{ "lfs",     OP(48),   OP_MASK,        COM,            { FRT, D, RA0 } },

 
 { "lfsu",    OP(49),   OP_MASK,        COM,            { FRT, D, RAS } },
 
 
 { "lfsu",    OP(49),   OP_MASK,        COM,            { FRT, D, RAS } },
 

-{ "lfd",     OP(50),   OP_MASK,        COM,            { FRT, D, RA } },
+{ "lfd",     OP(50),   OP_MASK,        COM,            { FRT, D, RA0 } },

 
 { "lfdu",    OP(51),   OP_MASK,        COM,            { FRT, D, RAS } },
 
 
 { "lfdu",    OP(51),   OP_MASK,        COM,            { FRT, D, RAS } },
 

-{ "stfs",    OP(52),   OP_MASK,        COM,            { FRS, D, RA } },
+{ "stfs",    OP(52),   OP_MASK,        COM,            { FRS, D, RA0 } },

 
 { "stfsu",   OP(53),   OP_MASK,        COM,            { FRS, D, RAS } },
 
 
 { "stfsu",   OP(53),   OP_MASK,        COM,            { FRS, D, RAS } },
 

-{ "stfd",    OP(54),   OP_MASK,        COM,            { FRS, D, RA } },
+{ "stfd",    OP(54),   OP_MASK,        COM,            { FRS, D, RA0 } },

 
 { "stfdu",   OP(55),   OP_MASK,        COM,            { FRS, D, RAS } },
 
 
 { "stfdu",   OP(55),   OP_MASK,        COM,            { FRS, D, RAS } },
 

-{ "lfq",     OP(56),   OP_MASK,        POWER2,         { FRT, D, RA } },
+{ "lq",      OP(56),   OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },

 
 

-{ "lfqu",    OP(57),   OP_MASK,        POWER2,         { FRT, D, RA } },
+{ "lfq",     OP(56),   OP_MASK,        POWER2,         { FRT, D, RA0 } },

 
 

-{ "lbze",    DEO(58,0), DE_MASK,       BOOKE64,        { RT, DE, RA } },
+{ "lfqu",    OP(57),   OP_MASK,        POWER2,         { FRT, D, RA0 } },
+
+{ "lbze",    DEO(58,0), DE_MASK,       BOOKE64,        { RT, DE, RA0 } },

 { "lbzue",   DEO(58,1), DE_MASK,       BOOKE64,        { RT, DE, RAL } },
 { "lbzue",   DEO(58,1), DE_MASK,       BOOKE64,        { RT, DE, RAL } },

-{ "lhze",    DEO(58,2), DE_MASK,       BOOKE64,        { RT, DE, RA } },
+{ "lhze",    DEO(58,2), DE_MASK,       BOOKE64,        { RT, DE, RA0 } },

 { "lhzue",   DEO(58,3), DE_MASK,       BOOKE64,        { RT, DE, RAL } },
 { "lhzue",   DEO(58,3), DE_MASK,       BOOKE64,        { RT, DE, RAL } },

-{ "lhae",    DEO(58,4), DE_MASK,       BOOKE64,        { RT, DE, RA } },
+{ "lhae",    DEO(58,4), DE_MASK,       BOOKE64,        { RT, DE, RA0 } },

 { "lhaue",   DEO(58,5), DE_MASK,       BOOKE64,        { RT, DE, RAL } },
 { "lhaue",   DEO(58,5), DE_MASK,       BOOKE64,        { RT, DE, RAL } },

-{ "lwze",    DEO(58,6), DE_MASK,       BOOKE64,        { RT, DE, RA } },
+{ "lwze",    DEO(58,6), DE_MASK,       BOOKE64,        { RT, DE, RA0 } },

 { "lwzue",   DEO(58,7), DE_MASK,       BOOKE64,        { RT, DE, RAL } },
 { "lwzue",   DEO(58,7), DE_MASK,       BOOKE64,        { RT, DE, RAL } },

-{ "stbe",    DEO(58,8), DE_MASK,       BOOKE64,        { RS, DE, RA } },
+{ "stbe",    DEO(58,8), DE_MASK,       BOOKE64,        { RS, DE, RA0 } },

 { "stbue",   DEO(58,9), DE_MASK,       BOOKE64,        { RS, DE, RAS } },
 { "stbue",   DEO(58,9), DE_MASK,       BOOKE64,        { RS, DE, RAS } },

-{ "sthe",    DEO(58,10), DE_MASK,      BOOKE64,        { RS, DE, RA } },
+{ "sthe",    DEO(58,10), DE_MASK,      BOOKE64,        { RS, DE, RA0 } },

 { "sthue",   DEO(58,11), DE_MASK,      BOOKE64,        { RS, DE, RAS } },
 { "sthue",   DEO(58,11), DE_MASK,      BOOKE64,        { RS, DE, RAS } },

-{ "stwe",    DEO(58,14), DE_MASK,      BOOKE64,        { RS, DE, RA } },
+{ "stwe",    DEO(58,14), DE_MASK,      BOOKE64,        { RS, DE, RA0 } },

 { "stwue",   DEO(58,15), DE_MASK,      BOOKE64,        { RS, DE, RAS } },
 
 { "stwue",   DEO(58,15), DE_MASK,      BOOKE64,        { RS, DE, RAS } },
 

-{ "ld",      DSO(58,0),        DS_MASK,        PPC64,          { RT, DS, RA } },
+{ "ld",      DSO(58,0),        DS_MASK,        PPC64,          { RT, DS, RA0 } },

 
 { "ldu",     DSO(58,1), DS_MASK,       PPC64,          { RT, DS, RAL } },
 
 
 { "ldu",     DSO(58,1), DS_MASK,       PPC64,          { RT, DS, RAL } },
 

-{ "lwa",     DSO(58,2), DS_MASK,       PPC64,          { RT, DS, RA } },
+{ "lwa",     DSO(58,2), DS_MASK,       PPC64,          { RT, DS, RA0 } },

 
 { "fdivs",   A(59,18,0), AFRC_MASK,    PPC,            { FRT, FRA, FRB } },
 { "fdivs.",  A(59,18,1), AFRC_MASK,    PPC,            { FRT, FRA, FRB } },
 
 { "fdivs",   A(59,18,0), AFRC_MASK,    PPC,            { FRT, FRA, FRB } },
 { "fdivs.",  A(59,18,1), AFRC_MASK,    PPC,            { FRT, FRA, FRB } },


@@ -4395,23 +4457,25 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stfqu",   OP(61),   OP_MASK,        POWER2,         { FRS, D, RA } },
 
 
 { "stfqu",   OP(61),   OP_MASK,        POWER2,         { FRS, D, RA } },
 

-{ "lde",     DEO(62,0), DE_MASK,       BOOKE64,        { RT, DES, RA } },
-{ "ldue",    DEO(62,1), DE_MASK,       BOOKE64,        { RT, DES, RA } },
-{ "lfse",    DEO(62,4), DE_MASK,       BOOKE64,        { FRT, DES, RA } },
+{ "lde",     DEO(62,0), DE_MASK,       BOOKE64,        { RT, DES, RA0 } },
+{ "ldue",    DEO(62,1), DE_MASK,       BOOKE64,        { RT, DES, RA0 } },
+{ "lfse",    DEO(62,4), DE_MASK,       BOOKE64,        { FRT, DES, RA0 } },

 { "lfsue",   DEO(62,5), DE_MASK,       BOOKE64,        { FRT, DES, RAS } },
 { "lfsue",   DEO(62,5), DE_MASK,       BOOKE64,        { FRT, DES, RAS } },

-{ "lfde",    DEO(62,6), DE_MASK,       BOOKE64,        { FRT, DES, RA } },
+{ "lfde",    DEO(62,6), DE_MASK,       BOOKE64,        { FRT, DES, RA0 } },

 { "lfdue",   DEO(62,7), DE_MASK,       BOOKE64,        { FRT, DES, RAS } },
 { "lfdue",   DEO(62,7), DE_MASK,       BOOKE64,        { FRT, DES, RAS } },

-{ "stde",    DEO(62,8), DE_MASK,       BOOKE64,        { RS, DES, RA } },
+{ "stde",    DEO(62,8), DE_MASK,       BOOKE64,        { RS, DES, RA0 } },

 { "stdue",   DEO(62,9), DE_MASK,       BOOKE64,        { RS, DES, RAS } },
 { "stdue",   DEO(62,9), DE_MASK,       BOOKE64,        { RS, DES, RAS } },

-{ "stfse",   DEO(62,12), DE_MASK,      BOOKE64,        { FRS, DES, RA } },
+{ "stfse",   DEO(62,12), DE_MASK,      BOOKE64,        { FRS, DES, RA0 } },

 { "stfsue",  DEO(62,13), DE_MASK,      BOOKE64,        { FRS, DES, RAS } },
 { "stfsue",  DEO(62,13), DE_MASK,      BOOKE64,        { FRS, DES, RAS } },

-{ "stfde",   DEO(62,14), DE_MASK,      BOOKE64,        { FRS, DES, RA } },
+{ "stfde",   DEO(62,14), DE_MASK,      BOOKE64,        { FRS, DES, RA0 } },

 { "stfdue",  DEO(62,15), DE_MASK,      BOOKE64,        { FRS, DES, RAS } },
 
 { "stfdue",  DEO(62,15), DE_MASK,      BOOKE64,        { FRS, DES, RAS } },
 

-{ "std",     DSO(62,0),        DS_MASK,        PPC64,          { RS, DS, RA } },
+{ "std",     DSO(62,0),        DS_MASK,        PPC64,          { RS, DS, RA0 } },

 
 { "stdu",    DSO(62,1),        DS_MASK,        PPC64,          { RS, DS, RAS } },
 
 
 { "stdu",    DSO(62,1),        DS_MASK,        PPC64,          { RS, DS, RAS } },
 

+{ "stq",     DSO(62,2),        DS_MASK,        POWER4,         { RSQ, DS, RA0 } },
+

 { "fcmpu",   X(63,0),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
 
 { "frsp",    XRC(63,12,0), XRA_MASK,   COM,            { FRT, FRB } },
 { "fcmpu",   X(63,0),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
 
 { "frsp",    XRC(63,12,0), XRA_MASK,   COM,            { FRT, FRB } },