* ppc-opc.c: Remove PARAMS from prototypes.

[deliverable/binutils-gdb.git] / opcodes / ppc-opc.c

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 3579dd249f7fbb8d6bf954719c08069c7f744c2e..c2a3864a3096de69eee1a1f51f21dc33490edfe2 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1,24 +1,24 @@
 /* ppc-opc.c -- PowerPC opcode list
 /* ppc-opc.c -- PowerPC opcode list

-   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003

    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 

-This file is part of GDB, GAS, and the GNU binutils.
+   This file is part of GDB, GAS, and the GNU binutils.

 
 

-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-2, or (at your option) any later version.
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either version
+   2, or (at your option) any later version.

 
 

-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GDB, GAS, and the GNU binutils are distributed in the hope that they
+   will be useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.

 
 

-You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this file; see the file COPYING.  If not, write to the Free
+   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA.  */

 
 #include <stdio.h>
 #include "sysdep.h"
 
 #include <stdio.h>
 #include "sysdep.h"


@@ -38,90 +38,61 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 \f
 /* Local insertion and extraction functions.  */
 
 \f
 /* Local insertion and extraction functions.  */
 

-static unsigned long insert_bat
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bat
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bba
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bba
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bd
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bd
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bdm
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bdm
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_bdp
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bdp
-  PARAMS ((unsigned long, int, int *));
-static int valid_bo
-  PARAMS ((long, int));
-static unsigned long insert_bo
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_bo
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_boe
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_boe
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ds
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_ds
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_de
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_de
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_des
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_des
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_li
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_li
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_mbe
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_mbe
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_mb6
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_mb6
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_nb
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_nb
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_nsi
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_nsi
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_ral
-  PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_ram
-  PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_ras
-  PARAMS ((unsigned long, long, int, const char **));
-static unsigned long insert_rbs
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_rbs
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_sh6
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_sh6
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_spr
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_spr
-  PARAMS ((unsigned long, int, int *));
-static unsigned long insert_tbr
-  PARAMS ((unsigned long, long, int, const char **));
-static long extract_tbr
-  PARAMS ((unsigned long, int, int *));
+static unsigned long insert_bat (unsigned long, long, int, const char **);
+static long extract_bat (unsigned long, int, int *);
+static unsigned long insert_bba (unsigned long, long, int, const char **);
+static long extract_bba (unsigned long, int, int *);
+static unsigned long insert_bd (unsigned long, long, int, const char **);
+static long extract_bd (unsigned long, int, int *);
+static unsigned long insert_bdm (unsigned long, long, int, const char **);
+static long extract_bdm (unsigned long, int, int *);
+static unsigned long insert_bdp (unsigned long, long, int, const char **);
+static long extract_bdp (unsigned long, int, int *);
+static int valid_bo (long, int);
+static unsigned long insert_bo (unsigned long, long, int, const char **);
+static long extract_bo (unsigned long, int, int *);
+static unsigned long insert_boe (unsigned long, long, int, const char **);
+static long extract_boe (unsigned long, int, int *);
+static unsigned long insert_dq (unsigned long, long, int, const char **);
+static long extract_dq (unsigned long, int, int *);
+static unsigned long insert_ds (unsigned long, long, int, const char **);
+static long extract_ds (unsigned long, int, int *);
+static unsigned long insert_de (unsigned long, long, int, const char **);
+static long extract_de (unsigned long, int, int *);
+static unsigned long insert_des (unsigned long, long, int, const char **);
+static long extract_des (unsigned long, int, int *);
+static unsigned long insert_fxm (unsigned long, long, int, const char **);
+static long extract_fxm (unsigned long, int, int *);
+static unsigned long insert_li (unsigned long, long, int, const char **);
+static long extract_li (unsigned long, int, int *);
+static unsigned long insert_mbe (unsigned long, long, int, const char **);
+static long extract_mbe (unsigned long, int, int *);
+static unsigned long insert_mb6 (unsigned long, long, int, const char **);
+static long extract_mb6 (unsigned long, int, int *);
+static unsigned long insert_nb (unsigned long, long, int, const char **);
+static long extract_nb (unsigned long, int, int *);
+static unsigned long insert_nsi (unsigned long, long, int, const char **);
+static long extract_nsi (unsigned long, int, int *);
+static unsigned long insert_ral (unsigned long, long, int, const char **);
+static unsigned long insert_ram (unsigned long, long, int, const char **);
+static unsigned long insert_raq (unsigned long, long, int, const char **);
+static unsigned long insert_ras (unsigned long, long, int, const char **);
+static unsigned long insert_rbs (unsigned long, long, int, const char **);
+static long extract_rbs (unsigned long, int, int *);
+static unsigned long insert_rsq (unsigned long, long, int, const char **);
+static unsigned long insert_rtq (unsigned long, long, int, const char **);
+static unsigned long insert_sh6 (unsigned long, long, int, const char **);
+static long extract_sh6 (unsigned long, int, int *);
+static unsigned long insert_spr (unsigned long, long, int, const char **);
+static long extract_spr (unsigned long, int, int *);
+static unsigned long insert_tbr (unsigned long, long, int, const char **);
+static long extract_tbr (unsigned long, int, int *);
+static unsigned long insert_ev2 (unsigned long, long, int, const char **);
+static long extract_ev2 (unsigned long, int, int *);
+static unsigned long insert_ev4 (unsigned long, long, int, const char **);
+static long extract_ev4 (unsigned long, int, int *);
+static unsigned long insert_ev8 (unsigned long, long, int, const char **);
+static long extract_ev8 (unsigned long, int, int *);

 \f
 /* The operands table.
 
 \f
 /* The operands table.
 


@@ -235,8 +206,20 @@ const struct powerpc_operand powerpc_operands[] =
 #define CR BT + 1
   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 
 #define CR BT + 1
   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 

+  /* The CRB field in an X form instruction.  */
+#define CRB CR + 1
+  { 5, 6, 0, 0, 0 },
+
+  /* The CRFD field in an X form instruction.  */
+#define CRFD CRB + 1
+  { 3, 23, 0, 0, PPC_OPERAND_CR },
+
+  /* The CRFS field in an X form instruction.  */
+#define CRFS CRFD + 1
+  { 3, 0, 0, 0, PPC_OPERAND_CR },
+

   /* The CT field in an X form instruction.  */
   /* The CT field in an X form instruction.  */

-#define CT CR + 1
+#define CT CRFS + 1

   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 
   /* The D field in a D form instruction.  This is a displacement off
   { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 
   /* The D field in a D form instruction.  This is a displacement off


@@ -255,9 +238,15 @@ const struct powerpc_operand powerpc_operands[] =
 #define DES DE + 1
   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 
 #define DES DE + 1
   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 

+  /* The DQ field in a DQ form instruction.  This is like D, but the
+     lower four bits are forced to zero. */
+#define DQ DES + 1
+  { 16, 0, insert_dq, extract_dq,
+      PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
+

   /* The DS field in a DS form instruction.  This is like D, but the
      lower two bits are forced to zero.  */
   /* The DS field in a DS form instruction.  This is like D, but the
      lower two bits are forced to zero.  */

-#define DS DES + 1
+#define DS DQ + 1

   { 16, 0, insert_ds, extract_ds,
       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 
   { 16, 0, insert_ds, extract_ds,
       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
 


@@ -301,10 +290,14 @@ const struct powerpc_operand powerpc_operands[] =
   /* The FXM field in an XFX instruction.  */
 #define FXM FRS + 1
 #define FXM_MASK (0xff << 12)
   /* The FXM field in an XFX instruction.  */
 #define FXM FRS + 1
 #define FXM_MASK (0xff << 12)

-  { 8, 12, 0, 0, 0 },
+  { 8, 12, insert_fxm, extract_fxm, 0 },
+
+  /* Power4 version for mfcr.  */
+#define FXM4 FXM + 1
+  { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },

 
   /* The L field in a D or X form instruction.  */
 
   /* The L field in a D or X form instruction.  */

-#define L FXM + 1
+#define L FXM4 + 1

   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 
   /* The LEV field in a POWER SC form instruction.  */
   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
 
   /* The LEV field in a POWER SC form instruction.  */


@@ -365,15 +358,20 @@ const struct powerpc_operand powerpc_operands[] =
   { 16, 0, insert_nsi, extract_nsi,
       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 
   { 16, 0, insert_nsi, extract_nsi,
       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 

-  /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
+  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */

 #define RA NSI + 1
 #define RA_MASK (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 
 #define RA NSI + 1
 #define RA_MASK (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_GPR },
 

+  /* The RA field in the DQ form lq instruction, which has special 
+     value restrictions.  */
+#define RAQ RA + 1
+  { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
+

   /* The RA field in a D or X form instruction which is an updating
      load, which means that the RA field may not be zero and may not
      equal the RT field.  */
   /* The RA field in a D or X form instruction which is an updating
      load, which means that the RA field may not be zero and may not
      equal the RT field.  */

-#define RAL RA + 1
+#define RAL RAQ + 1

   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 
   /* The RA field in an lmw instruction, which has special value
   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
 
   /* The RA field in an lmw instruction, which has special value


@@ -406,8 +404,18 @@ const struct powerpc_operand powerpc_operands[] =
 #define RT_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 
 #define RT_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_GPR },
 

+  /* The RS field of the DS form stq instruction, which has special 
+     value restrictions.  */
+#define RSQ RS + 1
+  { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
+
+  /* The RT field of the DQ form lq instruction, which has special
+     value restrictions.  */
+#define RTQ RSQ + 1
+  { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
+

   /* The SH field in an X or M form instruction.  */
   /* The SH field in an X or M form instruction.  */

-#define SH RS + 1
+#define SH RTQ + 1

 #define SH_MASK (0x1f << 11)
   { 5, 11, 0, 0, 0 },
 
 #define SH_MASK (0x1f << 11)
   { 5, 11, 0, 0, 0 },
 


@@ -428,6 +436,7 @@ const struct powerpc_operand powerpc_operands[] =
   /* The SPR field in an XFX form instruction.  This is flipped--the
      lower 5 bits are stored in the upper 5 and vice- versa.  */
 #define SPR SISIGNOPT + 1
   /* The SPR field in an XFX form instruction.  This is flipped--the
      lower 5 bits are stored in the upper 5 and vice- versa.  */
 #define SPR SISIGNOPT + 1

+#define PMR SPR

 #define SPR_MASK (0x3ff << 11)
   { 10, 11, insert_spr, extract_spr, 0 },
 
 #define SPR_MASK (0x3ff << 11)
   { 10, 11, insert_spr, extract_spr, 0 },
 


@@ -472,41 +481,57 @@ const struct powerpc_operand powerpc_operands[] =
 #define UI U + 1
   { 16, 0, 0, 0, 0 },
 
 #define UI U + 1
   { 16, 0, 0, 0, 0 },
 

-  /* The VA field in a VA, VX or VXR form instruction. */
+  /* The VA field in a VA, VX or VXR form instruction.  */

 #define VA UI + 1
 #define VA_MASK        (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_VR },
 
 #define VA UI + 1
 #define VA_MASK        (0x1f << 16)
   { 5, 16, 0, 0, PPC_OPERAND_VR },
 

-  /* The VB field in a VA, VX or VXR form instruction. */
+  /* The VB field in a VA, VX or VXR form instruction.  */

 #define VB VA + 1
 #define VB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_VR },
 
 #define VB VA + 1
 #define VB_MASK (0x1f << 11)
   { 5, 11, 0, 0, PPC_OPERAND_VR },
 

-  /* The VC field in a VA form instruction. */
+  /* The VC field in a VA form instruction.  */

 #define VC VB + 1
 #define VC_MASK (0x1f << 6)
   { 5, 6, 0, 0, PPC_OPERAND_VR },
 
 #define VC VB + 1
 #define VC_MASK (0x1f << 6)
   { 5, 6, 0, 0, PPC_OPERAND_VR },
 

-  /* The VD or VS field in a VA, VX, VXR or X form instruction. */
+  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */

 #define VD VC + 1
 #define VS VD
 #define VD_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_VR },
 
 #define VD VC + 1
 #define VS VD
 #define VD_MASK (0x1f << 21)
   { 5, 21, 0, 0, PPC_OPERAND_VR },
 

-  /* The SIMM field in a VX form instruction. */
+  /* The SIMM field in a VX form instruction.  */

 #define SIMM VD + 1
   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 
 #define SIMM VD + 1
   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 

-  /* The UIMM field in a VX form instruction. */
+  /* The UIMM field in a VX form instruction.  */

 #define UIMM SIMM + 1
   { 5, 16, 0, 0, 0 },
 
 #define UIMM SIMM + 1
   { 5, 16, 0, 0, 0 },
 

-  /* The SHB field in a VA form instruction. */
+  /* The SHB field in a VA form instruction.  */

 #define SHB UIMM + 1
   { 4, 6, 0, 0, 0 },
 
 #define SHB UIMM + 1
   { 4, 6, 0, 0, 0 },
 

+  /* The other UIMM field in a EVX form instruction.  */
+#define EVUIMM SHB + 1
+  { 5, 11, 0, 0, 0 },
+
+  /* The other UIMM field in a half word EVX form instruction.  */
+#define EVUIMM_2 EVUIMM + 1
+  { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
+
+  /* The other UIMM field in a word EVX form instruction.  */
+#define EVUIMM_4 EVUIMM_2 + 1
+  { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
+
+  /* The other UIMM field in a double EVX form instruction.  */
+#define EVUIMM_8 EVUIMM_4 + 1
+  { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
+

   /* The WS field.  */
   /* The WS field.  */

-#define WS SHB + 1
+#define WS EVUIMM_8 + 1

 #define WS_MASK (0x7 << 11)
   { 3, 11, 0, 0, 0 },
 
 #define WS_MASK (0x7 << 11)
   { 3, 11, 0, 0, 0 },
 


@@ -829,6 +854,101 @@ extract_boe (insn, dialect, invalid)
   return value & 0x1e;
 }
 
   return value & 0x1e;
 }
 

+  /* The DQ field in a DQ form instruction.  This is like D, but the
+     lower four bits are forced to zero. */
+
+/*ARGSUSED*/
+static unsigned long
+insert_dq (insn, value, dialect, errmsg)
+     unsigned long insn;
+     long value;
+     int dialect ATTRIBUTE_UNUSED;
+     const char ** errmsg ATTRIBUTE_UNUSED;
+{
+  if ((value & 0xf) != 0 && errmsg != NULL)
+    *errmsg = _("offset not a multiple of 16");
+  return insn | (value & 0xfff0);
+}
+
+/*ARGSUSED*/
+static long
+extract_dq (insn, dialect, invalid)
+     unsigned long insn;
+     int dialect ATTRIBUTE_UNUSED;
+     int *invalid ATTRIBUTE_UNUSED;
+{
+  return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
+}
+
+static unsigned long
+insert_ev2 (insn, value, dialect, errmsg)
+     unsigned long insn;
+     long value;
+     int dialect ATTRIBUTE_UNUSED;
+     const char ** errmsg ATTRIBUTE_UNUSED;
+{
+  if ((value & 1) != 0 && errmsg != NULL)
+    *errmsg = _("offset not a multiple of 2");
+  if ((value > 62) != 0 && errmsg != NULL)
+    *errmsg = _("offset greater than 62");
+  return insn | ((value & 0x3e) << 10);
+}
+
+static long
+extract_ev2 (insn, dialect, invalid)
+     unsigned long insn;
+     int dialect ATTRIBUTE_UNUSED;
+     int * invalid ATTRIBUTE_UNUSED;
+{
+  return (insn >> 10) & 0x3e;
+}
+
+static unsigned long
+insert_ev4 (insn, value, dialect, errmsg)
+     unsigned long insn;
+     long value;
+     int dialect ATTRIBUTE_UNUSED;
+     const char ** errmsg ATTRIBUTE_UNUSED;
+{
+  if ((value & 3) != 0 && errmsg != NULL)
+    *errmsg = _("offset not a multiple of 4");
+  if ((value > 124) != 0 && errmsg != NULL)
+    *errmsg = _("offset greater than 124");
+  return insn | ((value & 0x7c) << 9);
+}
+
+static long
+extract_ev4 (insn, dialect, invalid)
+     unsigned long insn;
+     int dialect ATTRIBUTE_UNUSED;
+     int * invalid ATTRIBUTE_UNUSED;
+{
+  return (insn >> 9) & 0x7c;
+}
+
+static unsigned long
+insert_ev8 (insn, value, dialect, errmsg)
+     unsigned long insn;
+     long value;
+     int dialect ATTRIBUTE_UNUSED;
+     const char ** errmsg ATTRIBUTE_UNUSED;
+{
+  if ((value & 7) != 0 && errmsg != NULL)
+    *errmsg = _("offset not a multiple of 8");
+  if ((value > 248) != 0 && errmsg != NULL)
+    *errmsg = _("offset greater than 248");
+  return insn | ((value & 0xf8) << 8);
+}
+
+static long
+extract_ev8 (insn, dialect, invalid)
+     unsigned long insn;
+     int dialect ATTRIBUTE_UNUSED;
+     int * invalid ATTRIBUTE_UNUSED;
+{
+  return (insn >> 8) & 0xf8;
+}
+

 /* The DS field in a DS form instruction.  This is like D, but the
    lower two bits are forced to zero.  */
 
 /* The DS field in a DS form instruction.  This is like D, but the
    lower two bits are forced to zero.  */
 


@@ -907,6 +1027,64 @@ extract_des (insn, dialect, invalid)
   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 }
 
   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
 }
 

+static unsigned long insert_fxm (unsigned long insn,
+                                long value,
+                                int dialect,
+                                const char **errmsg)
+{
+  /* If the optional field on mfcr is missing that means we want to use
+     the old form of the instruction that moves the whole cr.  In that
+     case we'll have VALUE zero.  There doesn't seem to be a way to
+     distinguish this from the case where someone writes mfcr %r3,0.  */
+  if (value == 0)
+    ;
+
+  /* If only one bit of the FXM field is set, we can use the new form
+     of the instruction, which is faster.  */
+  else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
+    insn |= 1 << 20;
+
+  /* Any other value on mfcr is an error.  */
+  else if ((insn & (0x3ff << 1)) == 19 << 1)
+    {
+      if (errmsg != NULL)
+       *errmsg = _("ignoring invalid mfcr mask");
+      value = 0;
+    }
+
+  return insn | ((value & 0xff) << 12);
+}
+
+static long extract_fxm (unsigned long insn, int dialect, int *invalid)
+{
+  long mask = (insn >> 12) & 0xff;
+
+  /* Is this a Power4 insn?  */
+  if ((insn & (1 << 20)) != 0)
+    {
+      if ((dialect & PPC_OPCODE_POWER4) == 0)
+       {
+         if (invalid != NULL)
+           *invalid = 1;
+       }
+      else
+       {
+         /* Exactly one bit of MASK should be set.  */
+         if ((mask == 0 || (mask & -mask) != mask) && invalid != NULL)
+           *invalid = 1;
+       }
+    }
+
+  /* Check that non-power4 form of mfcr has a zero MASK.  */
+  else if ((insn & (0x3ff << 1)) == 19 << 1)
+    {
+      if (mask != 0 && invalid != NULL)
+       *invalid = 1;
+    }
+
+  return mask;
+}
+

 /* The LI field in an I form instruction.  The lower two bits are
    forced to zero.  */
 
 /* The LI field in an I form instruction.  The lower two bits are
    forced to zero.  */
 


@@ -1143,6 +1321,24 @@ insert_ram (insn, value, dialect, errmsg)
   return insn | ((value & 0x1f) << 16);
 }
 
   return insn | ((value & 0x1f) << 16);
 }
 

+  /* The RA field in the DQ form lq instruction, which has special 
+     value restrictions.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_raq (insn, value, dialect, errmsg)
+     unsigned long insn;
+     long value;
+     int dialect ATTRIBUTE_UNUSED;
+     const char **errmsg;
+{
+  long rtvalue = (insn & RT_MASK) >> 21;
+
+  if (value == rtvalue && errmsg != NULL)
+    *errmsg = _("source and target register operands must be different");
+  return insn | ((value & 0x1f) << 16);
+}
+

 /* The RA field in a D or X form instruction which is an updating
    store or an updating floating point load, which means that the RA
    field may not be zero.  */
 /* The RA field in a D or X form instruction which is an updating
    store or an updating floating point load, which means that the RA
    field may not be zero.  */


@@ -1188,6 +1384,38 @@ extract_rbs (insn, dialect, invalid)
   return 0;
 }
 
   return 0;
 }
 

+  /* The RT field of the DQ form lq instruction, which has special
+     value restrictions.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rtq (insn, value, dialect, errmsg)
+     unsigned long insn;
+     long value;
+     int dialect ATTRIBUTE_UNUSED;
+     const char **errmsg;
+{
+  if ((value & 1) != 0 && errmsg != NULL)
+    *errmsg = _("target register operand must be even");
+  return insn | ((value & 0x1f) << 21);
+}
+
+  /* The RS field of the DS form stq instruction, which has special 
+     value restrictions.  */
+
+/*ARGSUSED*/
+static unsigned long
+insert_rsq (insn, value, dialect, errmsg)
+     unsigned long insn;
+     long value ATTRIBUTE_UNUSED;
+     int dialect ATTRIBUTE_UNUSED;
+     const char **errmsg;
+{
+  if ((value & 1) != 0 && errmsg != NULL)
+    *errmsg = _("source register operand must be even");
+  return insn | ((value & 0x1f) << 21);
+}
+

 /* The SH field in an MD form instruction.  This is split.  */
 
 /*ARGSUSED*/
 /* The SH field in an MD form instruction.  This is split.  */
 
 /*ARGSUSED*/


@@ -1332,6 +1560,14 @@ extract_tbr (insn, dialect, invalid)
 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
 
 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
 

+/* An Context form instruction.  */
+#define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
+#define CTX_MASK       CTX(0x3f, 0x7)
+
+/* An User Context form instruction.  */
+#define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
+#define UCTX_MASK      UCTX(0x3f, 0x1f)
+

 /* The main opcode mask with the RA field clear.  */
 #define DRA_MASK (OP_MASK | RA_MASK)
 
 /* The main opcode mask with the RA field clear.  */
 #define DRA_MASK (OP_MASK | RA_MASK)
 


@@ -1343,6 +1579,10 @@ extract_tbr (insn, dialect, invalid)
 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
 #define DE_MASK DEO (0x3e, 0xf)
 
 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
 #define DE_MASK DEO (0x3e, 0xf)
 

+/* An EVSEL form instruction.  */
+#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
+#define EVSEL_MASK EVSEL(0x3f, 0xff)
+

 /* An M form instruction.  */
 #define M(op, rc) (OP (op) | ((rc) & 1))
 #define M_MASK M (0x3f, 1)
 /* An M form instruction.  */
 #define M(op, rc) (OP (op) | ((rc) & 1))
 #define M_MASK M (0x3f, 1)


@@ -1377,22 +1617,22 @@ extract_tbr (insn, dialect, invalid)
 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
 
 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
 

-/* An VX form instruction. */
+/* An VX form instruction.  */

 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
 
 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
 

-/* The mask for an VX form instruction. */
+/* The mask for an VX form instruction.  */

 #define VX_MASK        VX(0x3f, 0x7ff)
 
 #define VX_MASK        VX(0x3f, 0x7ff)
 

-/* An VA form instruction. */
+/* An VA form instruction.  */

 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
 
 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
 

-/* The mask for an VA form instruction. */
+/* The mask for an VA form instruction.  */

 #define VXA_MASK VXA(0x3f, 0x3f)
 
 #define VXA_MASK VXA(0x3f, 0x3f)
 

-/* An VXR form instruction. */
+/* An VXR form instruction.  */

 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
 
 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
 

-/* The mask for a VXR form instruction. */
+/* The mask for a VXR form instruction.  */

 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
 
 /* An X form instruction.  */
 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
 
 /* An X form instruction.  */


@@ -1416,7 +1656,7 @@ extract_tbr (insn, dialect, invalid)
 /* An X_MASK with the RA and RB fields fixed.  */
 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 
 /* An X_MASK with the RA and RB fields fixed.  */
 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 

-/* An XRARB_MASK, but with the L bit clear. */
+/* An XRARB_MASK, but with the L bit clear.  */

 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
 
 /* An X_MASK with the RT and RA fields fixed.  */
 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
 
 /* An X_MASK with the RT and RA fields fixed.  */


@@ -1457,6 +1697,10 @@ extract_tbr (insn, dialect, invalid)
 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
 
 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
 

+/* An X form isel instruction.  */
+#define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
+#define XISEL_MASK      XISEL(0x3f, 0x1f)
+

 /* An XL form instruction with the LK field set to 0.  */
 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
 
 /* An XL form instruction with the LK field set to 0.  */
 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
 


@@ -1506,7 +1750,7 @@ extract_tbr (insn, dialect, invalid)
 #define XS_MASK XS (0x3f, 0x1ff, 1)
 
 /* A mask for the FXM version of an XFX form instruction.  */
 #define XS_MASK XS (0x3f, 0x1ff, 1)
 
 /* A mask for the FXM version of an XFX form instruction.  */

-#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11))
+#define XFXFXM_MASK (X_MASK | (1 << 11))

 
 /* An XFX form instruction with the FXM field filled in.  */
 #define XFXM(op, xop, fxm) \
 
 /* An XFX form instruction with the FXM field filled in.  */
 #define XFXM(op, xop, fxm) \


@@ -1528,6 +1772,10 @@ extract_tbr (insn, dialect, invalid)
 /* An X form instruction with everything filled in except the E field.  */
 #define XE_MASK (0xffff7fff)
 
 /* An X form instruction with everything filled in except the E field.  */
 #define XE_MASK (0xffff7fff)
 

+/* An X form user context instruction.  */
+#define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
+#define XUC_MASK      XUC(0x3f, 0x1f)
+

 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF (0x0)
 #define BODNZFP        (0x1)
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF (0x0)
 #define BODNZFP        (0x1)


@@ -1606,9 +1854,18 @@ extract_tbr (insn, dialect, invalid)
 #define        M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
 #define        MFDEC1  PPC_OPCODE_POWER
 #define        M601    PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
 #define        MFDEC1  PPC_OPCODE_POWER

-#define        MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601
+#define        MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE

 #define BOOKE  PPC_OPCODE_BOOKE
 #define BOOKE64        PPC_OPCODE_BOOKE64
 #define BOOKE  PPC_OPCODE_BOOKE
 #define BOOKE64        PPC_OPCODE_BOOKE64

+#define CLASSIC        PPC_OPCODE_CLASSIC
+#define PPCSPE PPC_OPCODE_SPE
+#define PPCISEL        PPC_OPCODE_ISEL
+#define PPCEFS PPC_OPCODE_EFS
+#define PPCBRLK        PPC_OPCODE_BRLOCK
+#define PPCPMR PPC_OPCODE_PMR
+#define PPCCHLK        PPC_OPCODE_CACHELCK
+#define PPCCHLK64      PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
+#define PPCRFMCI       PPC_OPCODE_RFMCI

 \f
 /* The opcode table.
 
 \f
 /* The opcode table.
 


@@ -1629,6 +1886,7 @@ extract_tbr (insn, dialect, invalid)
    sorted by major opcode.  */
 
 const struct powerpc_opcode powerpc_opcodes[] = {
    sorted by major opcode.  */
 
 const struct powerpc_opcode powerpc_opcodes[] = {

+{ "attn",    X(0,256), X_MASK,         POWER4,         { 0 } },

 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK, PPC64,          { RA, SI } },
 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK, PPC64,          { RA, SI } },
 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,  PPC64,          { RA, SI } },
 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK, PPC64,          { RA, SI } },
 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK, PPC64,          { RA, SI } },
 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,  PPC64,          { RA, SI } },


@@ -1918,6 +2176,254 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "vupklsh",   VX(4,  718), VX_MASK,   PPCVEC,         { VD, VB } },
 { "vxor",      VX(4, 1220), VX_MASK,   PPCVEC,         { VD, VA, VB } },
 
 { "vupklsh",   VX(4,  718), VX_MASK,   PPCVEC,         { VD, VB } },
 { "vxor",      VX(4, 1220), VX_MASK,   PPCVEC,         { VD, VA, VB } },
 

+{ "evaddw",    VX(4, 512), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evaddiw",   VX(4, 514), VX_MASK,    PPCSPE,         { RS, RB, UIMM } },
+{ "evsubfw",   VX(4, 516), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evsubw",    VX(4, 516), VX_MASK,    PPCSPE,         { RS, RB, RA } },
+{ "evsubifw",  VX(4, 518), VX_MASK,    PPCSPE,         { RS, UIMM, RB } },
+{ "evsubiw",   VX(4, 518), VX_MASK,    PPCSPE,         { RS, RB, UIMM } },
+{ "evabs",     VX(4, 520), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evneg",     VX(4, 521), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evextsb",   VX(4, 522), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evextsh",   VX(4, 523), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evrndw",    VX(4, 524), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evcntlzw",  VX(4, 525), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evcntlsw",  VX(4, 526), VX_MASK,    PPCSPE,         { RS, RA } },
+
+{ "brinc",     VX(4, 527), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evand",     VX(4, 529), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evandc",    VX(4, 530), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmr",      VX(4, 535), VX_MASK,    PPCSPE,         { RS, RA, BBA } },
+{ "evor",      VX(4, 535), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evorc",     VX(4, 539), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evxor",     VX(4, 534), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "eveqv",     VX(4, 537), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evnand",    VX(4, 542), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evnot",     VX(4, 536), VX_MASK,    PPCSPE,         { RS, RA, BBA } },
+{ "evnor",     VX(4, 536), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evrlw",     VX(4, 552), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evrlwi",    VX(4, 554), VX_MASK,    PPCSPE,         { RS, RA, EVUIMM } },
+{ "evslw",     VX(4, 548), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evslwi",    VX(4, 550), VX_MASK,    PPCSPE,         { RS, RA, EVUIMM } },
+{ "evsrws",    VX(4, 545), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evsrwu",    VX(4, 544), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evsrwis",   VX(4, 547), VX_MASK,    PPCSPE,         { RS, RA, EVUIMM } },
+{ "evsrwiu",   VX(4, 546), VX_MASK,    PPCSPE,         { RS, RA, EVUIMM } },
+{ "evsplati",  VX(4, 553), VX_MASK,    PPCSPE,         { RS, SIMM } },
+{ "evsplatfi", VX(4, 555), VX_MASK,    PPCSPE,         { RS, SIMM } },
+{ "evmergehi", VX(4, 556), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmergelo", VX(4, 557), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmergehilo",VX(4,558), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evmergelohi",VX(4,559), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evcmpgts",  VX(4, 561), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evcmpgtu",  VX(4, 560), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evcmplts",  VX(4, 563), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evcmpltu",  VX(4, 562), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evcmpeq",   VX(4, 564), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evsel",     EVSEL(4,79),EVSEL_MASK, PPCSPE,         { RS, RA, RB, CRFS } },
+
+{ "evldd",     VX(4, 769), VX_MASK,    PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evlddx",    VX(4, 768), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evldw",     VX(4, 771), VX_MASK,    PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evldwx",    VX(4, 770), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evldh",     VX(4, 773), VX_MASK,    PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evldhx",    VX(4, 772), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evlwhe",    VX(4, 785), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwhex",   VX(4, 784), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evlwhou",   VX(4, 789), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwhoux",  VX(4, 788), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evlwhos",   VX(4, 791), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwhosx",  VX(4, 790), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evlwwsplat",VX(4, 793), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwwsplatx",VX(4, 792), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evlwhsplat",VX(4, 797), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evlwhsplatx",VX(4, 796), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evlhhesplat",VX(4, 777), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
+{ "evlhhesplatx",VX(4, 776), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evlhhousplat",VX(4, 781), VX_MASK,  PPCSPE,         { RS, EVUIMM_2, RA } },
+{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE,         { RS, RA, RB } },
+{ "evlhhossplat",VX(4, 783), VX_MASK,  PPCSPE,         { RS, EVUIMM_2, RA } },
+{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE,         { RS, RA, RB } },
+
+{ "evstdd",    VX(4, 801), VX_MASK,    PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evstddx",   VX(4, 800), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evstdw",    VX(4, 803), VX_MASK,    PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evstdwx",   VX(4, 802), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evstdh",    VX(4, 805), VX_MASK,    PPCSPE,         { RS, EVUIMM_8, RA } },
+{ "evstdhx",   VX(4, 804), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evstwwe",   VX(4, 825), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evstwwex",  VX(4, 824), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evstwwo",   VX(4, 829), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evstwwox",  VX(4, 828), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evstwhe",   VX(4, 817), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evstwhex",  VX(4, 816), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evstwho",   VX(4, 821), VX_MASK,    PPCSPE,         { RS, EVUIMM_4, RA } },
+{ "evstwhox",  VX(4, 820), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+
+{ "evfsabs",   VX(4, 644), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evfsnabs",  VX(4, 645), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evfsneg",   VX(4, 646), VX_MASK,    PPCSPE,         { RS, RA } },
+{ "evfsadd",   VX(4, 640), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evfssub",   VX(4, 641), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evfsmul",   VX(4, 648), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evfsdiv",   VX(4, 649), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evfscmpgt", VX(4, 652), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evfscmplt", VX(4, 653), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evfscmpeq", VX(4, 654), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evfststgt", VX(4, 668), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evfststlt", VX(4, 669), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evfststeq", VX(4, 670), VX_MASK,    PPCSPE,         { CRFD, RA, RB } },
+{ "evfscfui",  VX(4, 656), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfsctuiz", VX(4, 664), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfscfsi",  VX(4, 657), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfscfuf",  VX(4, 658), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfscfsf",  VX(4, 659), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfsctui",  VX(4, 660), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfsctsi",  VX(4, 661), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfsctsiz", VX(4, 666), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfsctuf",  VX(4, 662), VX_MASK,    PPCSPE,         { RS, RB } },
+{ "evfsctsf",  VX(4, 663), VX_MASK,    PPCSPE,         { RS, RB } },
+
+{ "efsabs",   VX(4, 708), VX_MASK,     PPCEFS,         { RS, RA } },
+{ "efsnabs",  VX(4, 709), VX_MASK,     PPCEFS,         { RS, RA } },
+{ "efsneg",   VX(4, 710), VX_MASK,     PPCEFS,         { RS, RA } },
+{ "efsadd",   VX(4, 704), VX_MASK,     PPCEFS,         { RS, RA, RB } },
+{ "efssub",   VX(4, 705), VX_MASK,     PPCEFS,         { RS, RA, RB } },
+{ "efsmul",   VX(4, 712), VX_MASK,     PPCEFS,         { RS, RA, RB } },
+{ "efsdiv",   VX(4, 713), VX_MASK,     PPCEFS,         { RS, RA, RB } },
+{ "efscmpgt", VX(4, 716), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efscmplt", VX(4, 717), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efscmpeq", VX(4, 718), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efststgt", VX(4, 732), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efststlt", VX(4, 733), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efststeq", VX(4, 734), VX_MASK,     PPCEFS,         { CRFD, RA, RB } },
+{ "efscfui",  VX(4, 720), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efsctuiz", VX(4, 728), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efscfsi",  VX(4, 721), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efscfuf",  VX(4, 722), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efscfsf",  VX(4, 723), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efsctui",  VX(4, 724), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efsctsi",  VX(4, 725), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efsctsiz", VX(4, 730), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efsctuf",  VX(4, 726), VX_MASK,     PPCEFS,         { RS, RB } },
+{ "efsctsf",  VX(4, 727), VX_MASK,     PPCEFS,         { RS, RB } },
+
+{ "evmhossf",  VX(4, 1031), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhossfa", VX(4, 1063), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhosmf",  VX(4, 1039), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhosmfa", VX(4, 1071), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhosmi",  VX(4, 1037), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhosmia", VX(4, 1069), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhoumi",  VX(4, 1036), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhoumia", VX(4, 1068), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhessf",  VX(4, 1027), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhessfa", VX(4, 1059), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhesmf",  VX(4, 1035), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhesmfa", VX(4, 1067), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhesmi",  VX(4, 1033), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmhesmia", VX(4, 1065), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmheumi",  VX(4, 1032), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmheumia", VX(4, 1064), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmhossfaaw",VX(4, 1287), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhossiaaw",VX(4, 1285), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhosmfaaw",VX(4, 1295), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhosmiaaw",VX(4, 1293), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhousiaaw",VX(4, 1284), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhoumiaaw",VX(4, 1292), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhessfaaw",VX(4, 1283), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhessiaaw",VX(4, 1281), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhesmfaaw",VX(4, 1291), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhesmiaaw",VX(4, 1289), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmheusiaaw",VX(4, 1280), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmheumiaaw",VX(4, 1288), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+
+{ "evmhossfanw",VX(4, 1415), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhossianw",VX(4, 1413), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhosmfanw",VX(4, 1423), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhosmianw",VX(4, 1421), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhousianw",VX(4, 1412), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhoumianw",VX(4, 1420), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhessfanw",VX(4, 1411), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhessianw",VX(4, 1409), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhesmfanw",VX(4, 1419), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhesmianw",VX(4, 1417), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmheusianw",VX(4, 1408), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmheumianw",VX(4, 1416), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+
+{ "evmhogsmfaa",VX(4, 1327), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhogsmiaa",VX(4, 1325), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhogumiaa",VX(4, 1324), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhegsmfaa",VX(4, 1323), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhegsmiaa",VX(4, 1321), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhegumiaa",VX(4, 1320), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+
+{ "evmhogsmfan",VX(4, 1455), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhogsmian",VX(4, 1453), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhogumian",VX(4, 1452), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhegsmfan",VX(4, 1451), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhegsmian",VX(4, 1449), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmhegumian",VX(4, 1448), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+
+{ "evmwhssf",  VX(4, 1095), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwhssfa", VX(4, 1127), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwhsmf",  VX(4, 1103), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwhsmfa", VX(4, 1135), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwhsmi",  VX(4, 1101), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwhsmia", VX(4, 1133), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwhumi",  VX(4, 1100), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwhumia", VX(4, 1132), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmwlumi",  VX(4, 1096), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwlumia", VX(4, 1128), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmwlssiaaw",VX(4, 1345), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmwlsmiaaw",VX(4, 1353), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmwlusiaaw",VX(4, 1344), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmwlumiaaw",VX(4, 1352), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+
+{ "evmwlssianw",VX(4, 1473), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmwlsmianw",VX(4, 1481), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmwlusianw",VX(4, 1472), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+{ "evmwlumianw",VX(4, 1480), VX_MASK,  PPCSPE,         { RS, RA, RB } },
+
+{ "evmwssf",   VX(4, 1107), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwssfa",  VX(4, 1139), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwsmf",   VX(4, 1115), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwsmfa",  VX(4, 1147), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwsmi",   VX(4, 1113), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwsmia",  VX(4, 1145), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwumi",   VX(4, 1112), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwumia",  VX(4, 1144), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmwssfaa", VX(4, 1363), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwsmfaa", VX(4, 1371), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwsmiaa", VX(4, 1369), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwumiaa", VX(4, 1368), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evmwssfan", VX(4, 1491), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwsmfan", VX(4, 1499), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwsmian", VX(4, 1497), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+{ "evmwumian", VX(4, 1496), VX_MASK,   PPCSPE,         { RS, RA, RB } },
+
+{ "evaddssiaaw",VX(4, 1217), VX_MASK,  PPCSPE,         { RS, RA } },
+{ "evaddsmiaaw",VX(4, 1225), VX_MASK,  PPCSPE,         { RS, RA } },
+{ "evaddusiaaw",VX(4, 1216), VX_MASK,  PPCSPE,         { RS, RA } },
+{ "evaddumiaaw",VX(4, 1224), VX_MASK,  PPCSPE,         { RS, RA } },
+
+{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE,         { RS, RA } },
+{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE,         { RS, RA } },
+{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE,         { RS, RA } },
+{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE,         { RS, RA } },
+
+{ "evmra",    VX(4, 1220), VX_MASK,    PPCSPE,         { RS, RA } },
+
+{ "evdivws",  VX(4, 1222), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+{ "evdivwu",  VX(4, 1223), VX_MASK,    PPCSPE,         { RS, RA, RB } },
+

 { "mulli",   OP(7),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
 { "muli",    OP(7),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
 
 { "mulli",   OP(7),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
 { "muli",    OP(7),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
 


@@ -1962,34 +2468,34 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "cau",     OP(15),   OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
 { "subis",   OP(15),   OP_MASK,        PPCCOM,         { RT, RA, NSI } },
 
 { "cau",     OP(15),   OP_MASK,        PWRCOM,         { RT,RA,SISIGNOPT } },
 { "subis",   OP(15),   OP_MASK,        PPCCOM,         { RT, RA, NSI } },
 

-{ "bdnz-",   BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,  { BDM } },
-{ "bdnz+",   BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,  { BDP } },
-{ "bdnz",    BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM,  { BD } },
-{ "bdn",     BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM,  { BD } },
-{ "bdnzl-",  BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,  { BDM } },
-{ "bdnzl+",  BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,  { BDP } },
-{ "bdnzl",   BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM,  { BD } },
-{ "bdnl",    BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM,  { BD } },
-{ "bdnza-",  BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,  { BDMA } },
-{ "bdnza+",  BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,  { BDPA } },
-{ "bdnza",   BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM,  { BDA } },
-{ "bdna",    BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM,  { BDA } },
-{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,  { BDMA } },
-{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,  { BDPA } },
-{ "bdnzla",  BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM,  { BDA } },
-{ "bdnla",   BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM,  { BDA } },
-{ "bdz-",    BBO(16,BODZ,0,0),  BBOATBI_MASK, PPCCOM,  { BDM } },
-{ "bdz+",    BBO(16,BODZ,0,0),  BBOATBI_MASK, PPCCOM,  { BDP } },
-{ "bdz",     BBO(16,BODZ,0,0),  BBOATBI_MASK, COM,     { BD } },
-{ "bdzl-",   BBO(16,BODZ,0,1),  BBOATBI_MASK, PPCCOM,  { BDM } },
-{ "bdzl+",   BBO(16,BODZ,0,1),  BBOATBI_MASK, PPCCOM,  { BDP } },
-{ "bdzl",    BBO(16,BODZ,0,1),  BBOATBI_MASK, COM,     { BD } },
-{ "bdza-",   BBO(16,BODZ,1,0),  BBOATBI_MASK, PPCCOM,  { BDMA } },
-{ "bdza+",   BBO(16,BODZ,1,0),  BBOATBI_MASK, PPCCOM,  { BDPA } },
-{ "bdza",    BBO(16,BODZ,1,0),  BBOATBI_MASK, COM,     { BDA } },
-{ "bdzla-",  BBO(16,BODZ,1,1),  BBOATBI_MASK, PPCCOM,  { BDMA } },
-{ "bdzla+",  BBO(16,BODZ,1,1),  BBOATBI_MASK, PPCCOM,  { BDPA } },
-{ "bdzla",   BBO(16,BODZ,1,1),  BBOATBI_MASK, COM,     { BDA } },
+{ "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BDM } },
+{ "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BDP } },
+{ "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BD } },
+{ "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,     { BD } },
+{ "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BDM } },
+{ "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BDP } },
+{ "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BD } },
+{ "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,     { BD } },
+{ "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDMA } },
+{ "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDPA } },
+{ "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDA } },
+{ "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,     { BDA } },
+{ "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDMA } },
+{ "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDPA } },
+{ "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDA } },
+{ "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,     { BDA } },
+{ "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,     { BDM } },
+{ "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,     { BDP } },
+{ "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,                { BD } },
+{ "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,     { BDM } },
+{ "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,     { BDP } },
+{ "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,                { BD } },
+{ "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,     { BDMA } },
+{ "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,     { BDPA } },
+{ "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,                { BDA } },
+{ "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,     { BDMA } },
+{ "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,     { BDPA } },
+{ "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,                { BDA } },

 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,                { CR, BD } },
 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,                { CR, BD } },


@@ -2238,7 +2744,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "ba",      B(18,1,0),        B_MASK,         COM,            { LIA } },
 { "bla",     B(18,1,1),        B_MASK,         COM,            { LIA } },
 
 { "ba",      B(18,1,0),        B_MASK,         COM,            { LIA } },
 { "bla",     B(18,1,1),        B_MASK,         COM,            { LIA } },
 

-{ "mcrf",    XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
+{ "mcrf",    XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },

 
 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,  { 0 } },
 
 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,  { 0 } },


@@ -2467,6 +2973,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "crnot",   XL(19,33), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
 { "crnor",   XL(19,33),        XL_MASK,        COM,            { BT, BA, BB } },
 
 { "crnot",   XL(19,33), XL_MASK,       PPCCOM,         { BT, BA, BBA } },
 { "crnor",   XL(19,33),        XL_MASK,        COM,            { BT, BA, BB } },

+{ "rfmci",    X(19,38), 0xffffffff,    PPCRFMCI,       { 0 } },

 
 { "rfi",     XL(19,50),        0xffffffff,     COM,            { 0 } },
 { "rfci",    XL(19,51),        0xffffffff,     PPC403,         { 0 } },
 
 { "rfi",     XL(19,50),        0xffffffff,     COM,            { 0 } },
 { "rfci",    XL(19,51),        0xffffffff,     PPC403,         { 0 } },


@@ -2785,7 +3292,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mulhwu",  XO(31,11,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
 { "mulhwu.", XO(31,11,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
 
 { "mulhwu",  XO(31,11,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
 { "mulhwu.", XO(31,11,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
 

-{ "mfcr",    X(31,19), XRARB_MASK,     COM,            { RT } },
+{ "isellt",  X(31,15),      X_MASK,    PPCISEL,        { RT, RA, RB } },
+{ "iselgt",  X(31,47),      X_MASK,    PPCISEL,        { RT, RA, RB } },
+{ "iseleq",  X(31,79),      X_MASK,    PPCISEL,        { RT, RA, RB } },
+{ "isel",    XISEL(31,15),  XISEL_MASK,        PPCISEL,        { RT, RA, RB, CRB } },
+
+{ "mfcr",    X(31,19), XRARB_MASK,     NOPOWER4,       { RT } },
+{ "mfcr",    X(31,19), XFXFXM_MASK,    POWER4,         { RT, FXM4 } },

 
 { "lwarx",   X(31,20), X_MASK,         PPC,            { RT, RA, RB } },
 
 
 { "lwarx",   X(31,20), X_MASK,         PPC,            { RT, RA, RB } },
 


@@ -2914,6 +3427,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "wrtee",   X(31,131),        XRARB_MASK,     PPC403,         { RS } },
 { "wrtee",   X(31,131),        XRARB_MASK,     BOOKE,          { RS } },
 
 { "wrtee",   X(31,131),        XRARB_MASK,     PPC403,         { RS } },
 { "wrtee",   X(31,131),        XRARB_MASK,     BOOKE,          { RS } },
 

+{ "dcbtstls",X(31,134),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+

 { "subfe",   XO(31,136,0,0), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "sfe",     XO(31,136,0,0), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 { "subfe.",  XO(31,136,0,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "subfe",   XO(31,136,0,0), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "sfe",     XO(31,136,0,0), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 { "subfe.",  XO(31,136,0,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },


@@ -2932,7 +3447,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "addeo.",  XO(31,138,1,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "aeo.",    XO(31,138,1,1), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 
 { "addeo.",  XO(31,138,1,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "aeo.",    XO(31,138,1,1), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 

-{ "mtcr",    XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM,     { RS }},
+{ "dcbtstlse",X(31,142),X_MASK,                PPCCHLK64,      { CT, RA, RB }},
+
+{ "mtcr",    XFXM(31,144,0xff), XRARB_MASK, COM,       { RS }},

 { "mtcrf",   X(31,144),        XFXFXM_MASK,    COM,            { FXM, RS } },
 
 { "mtmsr",   X(31,146),        XRARB_MASK,     COM,            { RS } },
 { "mtcrf",   X(31,144),        XFXFXM_MASK,    COM,            { FXM, RS } },
 
 { "mtmsr",   X(31,146),        XRARB_MASK,     COM,            { RS } },


@@ -2957,6 +3474,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "wrteei",  X(31,163),        XE_MASK,        PPC403,         { E } },
 { "wrteei",  X(31,163),        XE_MASK,        BOOKE,          { E } },
 
 { "wrteei",  X(31,163),        XE_MASK,        PPC403,         { E } },
 { "wrteei",  X(31,163),        XE_MASK,        BOOKE,          { E } },
 

+{ "dcbtls",  X(31,166),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+{ "dcbtlse", X(31,174),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},
+

 { "mtmsrd",  X(31,178),        XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
 
 { "stdux",   X(31,181),        X_MASK,         PPC64,          { RS, RAS, RB } },
 { "mtmsrd",  X(31,178),        XRLARB_MASK,    PPC64,          { RS, MTMSRD_L } },
 
 { "stdux",   X(31,181),        X_MASK,         PPC64,          { RS, RAS, RB } },


@@ -3001,6 +3521,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stbxe",   X(31,223),        X_MASK,         BOOKE64,        { RS, RA, RB } },
 
 
 { "stbxe",   X(31,223),        X_MASK,         BOOKE64,        { RS, RA, RB } },
 

+{ "icblc",   X(31,230),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+

 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,                { RT, RA } },
 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,                { RT, RA } },
 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,                { RT, RA } },
 { "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,                { RT, RA } },
 { "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,                { RT, RA } },
 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,                { RT, RA } },


@@ -3033,6 +3555,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mullwo.", XO(31,235,1,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "mulso.",  XO(31,235,1,1), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 
 { "mullwo.", XO(31,235,1,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "mulso.",  XO(31,235,1,1), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 

+{ "icblce",  X(31,238),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},

 { "mtsrin",  X(31,242),        XRA_MASK,       PPC32,          { RS, RB } },
 { "mtsri",   X(31,242),        XRA_MASK,       POWER32,        { RS, RB } },
 
 { "mtsrin",  X(31,242),        XRA_MASK,       PPC32,          { RS, RB } },
 { "mtsri",   X(31,242),        XRA_MASK,       POWER32,        { RS, RB } },
 


@@ -3065,6 +3588,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "addo.",   XO(31,266,1,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "caxo.",   XO(31,266,1,1), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 
 { "addo.",   XO(31,266,1,1), XO_MASK,  PPCCOM,         { RT, RA, RB } },
 { "caxo.",   XO(31,266,1,1), XO_MASK,  PWRCOM,         { RT, RA, RB } },
 

+{ "tlbiel",  X(31,274), XRTRA_MASK,    POWER4,         { RB } },
+

 { "mfapidi", X(31,275), X_MASK,                BOOKE,          { RT, RA } },
 
 { "lscbx",   XRC(31,277,0), X_MASK,    M601,           { RT, RA, RB } },
 { "mfapidi", X(31,275), X_MASK,                BOOKE,          { RT, RA } },
 
 { "lscbx",   XRC(31,277,0), X_MASK,    M601,           { RT, RA, RB } },


@@ -3093,19 +3618,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lhzuxe",  X(31,319),        X_MASK,         BOOKE64,        { RT, RAL, RB } },
 
 
 { "lhzuxe",  X(31,319),        X_MASK,         BOOKE64,        { RT, RAL, RB } },
 

-{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403,       { RT } },
-{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403,       { RT } },
-{ "mfbr0",   XSPR(31,323,128), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr1",   XSPR(31,323,129), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr2",   XSPR(31,323,130), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr3",   XSPR(31,323,131), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr4",   XSPR(31,323,132), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr5",   XSPR(31,323,133), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr6",   XSPR(31,323,134), XSPR_MASK, PPC403,      { RT } },
-{ "mfbr7",   XSPR(31,323,135), XSPR_MASK, PPC403,      { RT } },
-{ "mfbear",  XSPR(31,323,144), XSPR_MASK, PPC403,      { RT } },
-{ "mfbesr",  XSPR(31,323,145), XSPR_MASK, PPC403,      { RT } },
-{ "mfiocr",  XSPR(31,323,160), XSPR_MASK, PPC403,      { RT } },
+{ "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,     { RT } },
+{ "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,     { RT } },
+{ "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,     { RT } },
+{ "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,     { RT } },
+{ "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,     { RT } },
+{ "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,     { RT } },
+{ "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,     { RT } },

 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,     { RT } },
 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,     { RT } },
 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,     { RT } },
 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,     { RT } },
 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,     { RT } },
 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,     { RT } },


@@ -3126,102 +3651,150 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,     { RT } },
 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,     { RT } },
 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,     { RT } },
 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,     { RT } },
 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,     { RT } },
 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,     { RT } },

-{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403,      { RT } },
-{ "mfdcr",   X(31,323),        X_MASK,         PPC403,         { RT, SPR } },
-{ "mfdcr",   X(31,323),        X_MASK,         BOOKE,          { RT, SPR } },
+{ "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,     { RT } },
+{ "mfdcr",    X(31,323),       X_MASK,         PPC403,         { RT, SPR } },
+{ "mfdcr",    X(31,323),       X_MASK,         BOOKE,          { RT, SPR } },

 
 { "div",     XO(31,331,0,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "div.",    XO(31,331,0,1), XO_MASK,  M601,           { RT, RA, RB } },
 { "divo",    XO(31,331,1,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "divo.",   XO(31,331,1,1), XO_MASK,  M601,           { RT, RA, RB } },
 
 
 { "div",     XO(31,331,0,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "div.",    XO(31,331,0,1), XO_MASK,  M601,           { RT, RA, RB } },
 { "divo",    XO(31,331,1,0), XO_MASK,  M601,           { RT, RA, RB } },
 { "divo.",   XO(31,331,1,1), XO_MASK,  M601,           { RT, RA, RB } },
 

-{ "mfmq",     XSPR(31,339,0),   XSPR_MASK, M601,       { RT } },
-{ "mfxer",    XSPR(31,339,1),   XSPR_MASK, COM,                { RT } },
-{ "mfrtcu",   XSPR(31,339,4),   XSPR_MASK, COM,                { RT } },
-{ "mfrtcl",   XSPR(31,339,5),   XSPR_MASK, COM,                { RT } },
-{ "mfdec",    XSPR(31,339,6),   XSPR_MASK, MFDEC1,     { RT } },
-{ "mflr",     XSPR(31,339,8),   XSPR_MASK, COM,                { RT } },
-{ "mfctr",    XSPR(31,339,9),   XSPR_MASK, COM,                { RT } },
-{ "mftid",    XSPR(31,339,17),  XSPR_MASK, POWER,      { RT } },
-{ "mfdsisr",  XSPR(31,339,18),  XSPR_MASK, COM,                { RT } },
-{ "mfdar",    XSPR(31,339,19),  XSPR_MASK, COM,                { RT } },
-{ "mfdec",    XSPR(31,339,22),  XSPR_MASK, MFDEC2,     { RT } },
-{ "mfsdr0",   XSPR(31,339,24),  XSPR_MASK, POWER,      { RT } },
-{ "mfsdr1",   XSPR(31,339,25),  XSPR_MASK, COM,                { RT } },
-{ "mfsrr0",   XSPR(31,339,26),  XSPR_MASK, COM,                { RT } },
-{ "mfsrr1",   XSPR(31,339,27),  XSPR_MASK, COM,                { RT } },
-{ "mfcmpa",   XSPR(31,339,144), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpb",   XSPR(31,339,145), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpc",   XSPR(31,339,146), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpd",   XSPR(31,339,147), XSPR_MASK, PPC860,     { RT } },
-{ "mficr",    XSPR(31,339,148), XSPR_MASK, PPC860,     { RT } },
-{ "mfder",    XSPR(31,339,149), XSPR_MASK, PPC860,     { RT } },
-{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860,     { RT } },
-{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpe",   XSPR(31,339,152), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpf",   XSPR(31,339,153), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmpg",   XSPR(31,339,154), XSPR_MASK, PPC860,     { RT } },
-{ "mfcmph",   XSPR(31,339,155), XSPR_MASK, PPC860,     { RT } },
-{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860,     { RT } },
-{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860,     { RT } },
-{ "mfictrl",  XSPR(31,339,158), XSPR_MASK, PPC860,     { RT } },
-{ "mfbar",    XSPR(31,339,159), XSPR_MASK, PPC860,     { RT } },
-{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC,     { RT } },
-{ "mfsprg4",  XSPR(31,339,260), XSPR_MASK, PPC405,     { RT } },
-{ "mfsprg5",  XSPR(31,339,261), XSPR_MASK, PPC405,     { RT } },
-{ "mfsprg6",  XSPR(31,339,262), XSPR_MASK, PPC405,     { RT } },
-{ "mfsprg7",  XSPR(31,339,263), XSPR_MASK, PPC405,     { RT } },
-{ "mfsprg",   XSPR(31,339,272), XSPRG_MASK, PPC,       { RT, SPRG } },
-{ "mfsprg0",  XSPR(31,339,272), XSPR_MASK, PPC,                { RT } },
-{ "mfsprg1",  XSPR(31,339,273), XSPR_MASK, PPC,                { RT } },
-{ "mfsprg2",  XSPR(31,339,274), XSPR_MASK, PPC,                { RT } },
-{ "mfsprg3",  XSPR(31,339,275), XSPR_MASK, PPC,                { RT } },
-{ "mfasr",    XSPR(31,339,280), XSPR_MASK, PPC64,      { RT } },
-{ "mfear",    XSPR(31,339,282), XSPR_MASK, PPC,                { RT } },
-{ "mfpvr",    XSPR(31,339,287), XSPR_MASK, PPC,                { RT } },
-{ "mfibatu",  XSPR(31,339,528), XSPRBAT_MASK, PPC,     { RT, SPRBAT } },
-{ "mfibatl",  XSPR(31,339,529), XSPRBAT_MASK, PPC,     { RT, SPRBAT } },
-{ "mfdbatu",  XSPR(31,339,536), XSPRBAT_MASK, PPC,     { RT, SPRBAT } },
-{ "mfdbatl",  XSPR(31,339,537), XSPRBAT_MASK, PPC,     { RT, SPRBAT } },
-{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860,     { RT } },
-{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860,     { RT } },
-{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860,     { RT } },
-{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860,     { RT } },
-{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860,     { RT } },
-{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860,     { RT } },
-{ "mfdpdr",   XSPR(31,339,630), XSPR_MASK, PPC860,     { RT } },
-{ "mfdpir",   XSPR(31,339,631), XSPR_MASK, PPC860,     { RT } },
-{ "mfimmr",   XSPR(31,339,638), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_ap",  XSPR(31,339,786), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860,     { RT } },
-{ "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_ap",  XSPR(31,339,794), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860,     { RT } },
-{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860,     { RT } },
-{ "mfm_tw",   XSPR(31,339,799), XSPR_MASK, PPC860,     { RT } },
-{ "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860,    { RT } },
-{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860,   { RT } },
-{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860,   { RT } },
-{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860,   { RT } },
-{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860,   { RT } },
-{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860,   { RT } },
-{ "mfzpr",     XSPR(31,339,944), XSPR_MASK, PPC403,    { RT } },
-{ "mfpid",     XSPR(31,339,945), XSPR_MASK, PPC403,    { RT } },
-{ "mfccr0",    XSPR(31,339,947), XSPR_MASK, PPC405,    { RT } },
-{ "mficdbdr",  XSPR(31,339,979), XSPR_MASK, PPC403,    { RT } },
-{ "mfummcr0",  XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
-{ "mfupmc1",   XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
-{ "mfupmc2",   XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
-{ "mfusia",    XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
-{ "mfummcr1",  XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
-{ "mfupmc3",   XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
-{ "mfupmc4",   XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
+{ "mfpmr",   X(31,334),        X_MASK,         PPCPMR,         { RT, PMR }},
+
+{ "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,    { RT } },
+{ "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,     { RT } },
+{ "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,     { RT } },
+{ "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,     { RT } },
+{ "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,  { RT } },
+{ "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,     { RT } },
+{ "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,     { RT } },
+{ "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,   { RT } },
+{ "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,     { RT } },
+{ "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,     { RT } },
+{ "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,  { RT } },
+{ "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,   { RT } },
+{ "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,     { RT } },
+{ "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,     { RT } },
+{ "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,     { RT } },
+{ "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
+{ "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,  { RT } },
+{ "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,  { RT } },
+{ "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,  { RT } },
+{ "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,  { RT } },
+{ "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,  { RT } },
+{ "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,  { RT } },
+{ "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,  { RT } },
+{ "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,  { RT } },
+{ "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,  { RT } },
+{ "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405,  { RT } },
+{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405,  { RT } },
+{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405,  { RT } },
+{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405,  { RT } },
+{ "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfsprg",     XSPR(31,339,272),  XSPRG_MASK, PPC,    { RT, SPRG } },
+{ "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,     { RT } },
+{ "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,     { RT } },
+{ "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,     { RT } },
+{ "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,     { RT } },
+{ "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,   { RT } },
+{ "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,     { RT } },
+{ "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,     { RT } },
+{ "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
+{ "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
+{ "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,  { RT } },
+{ "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
+{ "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
+{ "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
+{ "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
+{ "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
+{ "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,  { RT, SPRBAT } },
+{ "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,  { RT } },
+{ "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,  { RT } },
+{ "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,  { RT } },
+{ "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,  { RT } },
+{ "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,  { RT } },
+{ "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
+{ "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,  { RT } },
+{ "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,  { RT } },
+{ "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,  { RT } },
+{ "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,  { RT } },
+{ "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,  { RT } },
+{ "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,  { RT } },
+{ "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
+{ "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
+{ "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
+{ "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
+{ "mfzpr",     XSPR(31,339,944),  XSPR_MASK, PPC403,   { RT } },
+{ "mfpid",     XSPR(31,339,945),  XSPR_MASK, PPC403,   { RT } },
+{ "mfccr0",    XSPR(31,339,947),  XSPR_MASK, PPC405,   { RT } },

 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,  { RT } },
 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,  { RT } },
 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,  { RT } },
 { "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,  { RT } },
 { "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,  { RT } },
 { "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,  { RT } },


@@ -3238,35 +3811,36 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mfpmc3",    XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
 { "mfdbcr1",   XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
 { "mfpmc4",    XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },
 { "mfpmc3",    XSPR(31,339,957),  XSPR_MASK, PPC750,   { RT } },
 { "mfdbcr1",   XSPR(31,339,957),  XSPR_MASK, PPC405,   { RT } },
 { "mfpmc4",    XSPR(31,339,958),  XSPR_MASK, PPC750,   { RT } },

-{ "mfesr",   XSPR(31,339,980), XSPR_MASK, PPC403,      { RT } },
-{ "mfdear",  XSPR(31,339,981), XSPR_MASK, PPC403,      { RT } },
-{ "mfevpr",  XSPR(31,339,982), XSPR_MASK, PPC403,      { RT } },
-{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403,      { RT } },
-{ "mftsr",   XSPR(31,339,984), XSPR_MASK, PPC403,      { RT } },
-{ "mftcr",   XSPR(31,339,986), XSPR_MASK, PPC403,      { RT } },
-{ "mfpit",   XSPR(31,339,987), XSPR_MASK, PPC403,      { RT } },
-{ "mftbhi",  XSPR(31,339,988), XSPR_MASK, PPC403,      { RT } },
-{ "mftblo",  XSPR(31,339,989), XSPR_MASK, PPC403,      { RT } },
-{ "mfsrr2",  XSPR(31,339,990), XSPR_MASK, PPC403,      { RT } },
-{ "mfsrr3",  XSPR(31,339,991), XSPR_MASK, PPC403,      { RT } },
-{ "mfdbsr",  XSPR(31,339,1008), XSPR_MASK, PPC403,     { RT } },
-{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405,     { RT } },
-{ "mfiac1",  XSPR(31,339,1012), XSPR_MASK, PPC403,     { RT } },
-{ "mfiac2",  XSPR(31,339,1013), XSPR_MASK, PPC403,     { RT } },
-{ "mfdac1",  XSPR(31,339,1014), XSPR_MASK, PPC403,     { RT } },
-{ "mfdac2",  XSPR(31,339,1015), XSPR_MASK, PPC403,     { RT } },
-{ "mfdccr",  XSPR(31,339,1018), XSPR_MASK, PPC403,     { RT } },
-{ "mficcr",  XSPR(31,339,1019), XSPR_MASK, PPC403,     { RT } },
-{ "mfpbl1",  XSPR(31,339,1020), XSPR_MASK, PPC403,     { RT } },
-{ "mfpbu1",  XSPR(31,339,1021), XSPR_MASK, PPC403,     { RT } },
-{ "mfpbl2",  XSPR(31,339,1022), XSPR_MASK, PPC403,     { RT } },
-{ "mfpbu2",  XSPR(31,339,1023), XSPR_MASK, PPC403,     { RT } },
-{ "mfl2cr",    XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
-{ "mfictc",    XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
-{ "mfthrm1",   XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
-{ "mfthrm2",   XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
-{ "mfthrm3",   XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
-{ "mfspr",   X(31,339),        X_MASK,         COM,            { RT, SPR } },
+{ "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
+{ "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,  { RT } },
+{ "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,  { RT } },
+{ "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,  { RT } },
+{ "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,  { RT } },
+{ "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,  { RT } },
+{ "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,  { RT } },
+{ "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,  { RT } },
+{ "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,  { RT } },
+{ "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,  { RT } },
+{ "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,  { RT } },
+{ "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,  { RT } },
+{ "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,  { RT } },
+{ "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,  { RT } },
+{ "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,  { RT } },
+{ "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,  { RT } },
+{ "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,  { RT } },
+{ "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,  { RT } },
+{ "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
+{ "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,  { RT } },
+{ "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,  { RT } },
+{ "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,  { RT } },
+{ "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,  { RT } },
+{ "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,  { RT } },
+{ "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
+{ "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,  { RT } },
+{ "mfspr",      X(31,339),        X_MASK,    COM,      { RT, SPR } },

 
 { "lwax",    X(31,341),        X_MASK,         PPC64,          { RT, RA, RB } },
 
 
 { "lwax",    X(31,341),        X_MASK,         PPC64,          { RT, RA, RB } },
 


@@ -3294,9 +3868,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "tlbia",   X(31,370),        0xffffffff,     PPC,            { 0 } },
 
 
 { "tlbia",   X(31,370),        0xffffffff,     PPC,            { 0 } },
 

-{ "mftbl",   XSPR(31,371,268), XSPR_MASK, PPC,         { RT } },
-{ "mftbu",   XSPR(31,371,269), XSPR_MASK, PPC,         { RT } },
-{ "mftb",    X(31,371),        X_MASK,         PPC,            { RT, TBR } },
+{ "mftbl",   XSPR(31,371,268), XSPR_MASK, CLASSIC,     { RT } },
+{ "mftbu",   XSPR(31,371,269), XSPR_MASK, CLASSIC,     { RT } },
+{ "mftb",    X(31,371),        X_MASK,         CLASSIC,        { RT, TBR } },

 
 { "lwaux",   X(31,373),        X_MASK,         PPC64,          { RT, RAL, RB } },
 
 
 { "lwaux",   X(31,373),        X_MASK,         PPC64,          { RT, RAL, RB } },
 


@@ -3306,12 +3880,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mtdcrx",  X(31,387),        X_MASK,         BOOKE,          { RA, RS } },
 
 
 { "mtdcrx",  X(31,387),        X_MASK,         BOOKE,          { RA, RS } },
 

+{ "dcblc",   X(31,390),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+

 { "subfe64", XO(31,392,0,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 { "subfe64o",XO(31,392,1,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 
 { "adde64",  XO(31,394,0,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 { "adde64o", XO(31,394,1,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 
 { "subfe64", XO(31,392,0,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 { "subfe64o",XO(31,392,1,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 
 { "adde64",  XO(31,394,0,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 { "adde64o", XO(31,394,1,0), XO_MASK,  BOOKE64,        { RT, RA, RB } },
 

+{ "dcblce",  X(31,398),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},
+

 { "slbmte",  X(31,402), XRA_MASK,      PPC64,          { RS, RB } },
 
 { "sthx",    X(31,407),        X_MASK,         COM,            { RS, RA, RB } },
 { "slbmte",  X(31,402), XRA_MASK,      PPC64,          { RS, RB } },
 
 { "sthx",    X(31,407),        X_MASK,         COM,            { RS, RA, RB } },


@@ -3345,19 +3923,19 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mr.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RBS } },
 { "or.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RB } },
 
 { "mr.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RBS } },
 { "or.",     XRC(31,444,1), X_MASK,    COM,            { RA, RS, RB } },
 

-{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403,       { RT } },
-{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403,       { RT } },
-{ "mtbr0",   XSPR(31,451,128), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr1",   XSPR(31,451,129), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr2",   XSPR(31,451,130), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr3",   XSPR(31,451,131), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr4",   XSPR(31,451,132), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr5",   XSPR(31,451,133), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr6",   XSPR(31,451,134), XSPR_MASK, PPC403,      { RT } },
-{ "mtbr7",   XSPR(31,451,135), XSPR_MASK, PPC403,      { RT } },
-{ "mtbear",  XSPR(31,451,144), XSPR_MASK, PPC403,      { RT } },
-{ "mtbesr",  XSPR(31,451,145), XSPR_MASK, PPC403,      { RT } },
-{ "mtiocr",  XSPR(31,451,160), XSPR_MASK, PPC403,      { RT } },
+{ "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,     { RT } },
+{ "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,     { RT } },
+{ "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,     { RT } },
+{ "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,     { RT } },
+{ "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,     { RT } },
+{ "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,     { RT } },
+{ "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,     { RT } },

 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,     { RT } },
 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,     { RT } },
 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,     { RT } },
 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,     { RT } },
 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,     { RT } },
 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,     { RT } },


@@ -3378,9 +3956,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,     { RT } },
 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,     { RT } },
 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,     { RT } },
 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,     { RT } },
 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,     { RT } },
 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,     { RT } },

-{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403,      { RT } },
-{ "mtdcr",   X(31,451),        X_MASK,         PPC403,         { SPR, RS } },
-{ "mtdcr",   X(31,451),        X_MASK,         BOOKE,          { SPR, RS } },
+{ "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,     { RT } },
+{ "mtdcr",    X(31,451),       X_MASK,         PPC403,         { SPR, RS } },
+{ "mtdcr",    X(31,451),       X_MASK,         BOOKE,          { SPR, RS } },

 
 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,       { RT, RA } },
 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,      { RT, RA } },
 
 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,       { RT, RA } },
 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,      { RT, RA } },


@@ -3398,110 +3976,158 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "divwuo",  XO(31,459,1,0), XO_MASK,  PPC,            { RT, RA, RB } },
 { "divwuo.", XO(31,459,1,1), XO_MASK,  PPC,            { RT, RA, RB } },
 
 { "divwuo",  XO(31,459,1,0), XO_MASK,  PPC,            { RT, RA, RB } },
 { "divwuo.", XO(31,459,1,1), XO_MASK,  PPC,            { RT, RA, RB } },
 

-{ "mtmq",    XSPR(31,467,0),   XSPR_MASK,    M601,     { RS } },
-{ "mtxer",   XSPR(31,467,1),   XSPR_MASK,    COM,      { RS } },
-{ "mtlr",    XSPR(31,467,8),   XSPR_MASK,    COM,      { RS } },
-{ "mtctr",   XSPR(31,467,9),   XSPR_MASK,    COM,      { RS } },
-{ "mttid",   XSPR(31,467,17),  XSPR_MASK,    POWER,    { RS } },
-{ "mtdsisr", XSPR(31,467,18),  XSPR_MASK,    COM,      { RS } },
-{ "mtdar",   XSPR(31,467,19),  XSPR_MASK,    COM,      { RS } },
-{ "mtrtcu",  XSPR(31,467,20),  XSPR_MASK,    COM,      { RS } },
-{ "mtrtcl",  XSPR(31,467,21),  XSPR_MASK,    COM,      { RS } },
-{ "mtdec",   XSPR(31,467,22),  XSPR_MASK,    COM,      { RS } },
-{ "mtsdr0",  XSPR(31,467,24),  XSPR_MASK,    POWER,    { RS } },
-{ "mtsdr1",  XSPR(31,467,25),  XSPR_MASK,    COM,      { RS } },
-{ "mtsrr0",  XSPR(31,467,26),  XSPR_MASK,    COM,      { RS } },
-{ "mtsrr1",  XSPR(31,467,27),  XSPR_MASK,    COM,      { RS } },
-{ "mtcmpa",   XSPR(31,467,144), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpb",   XSPR(31,467,145), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpc",   XSPR(31,467,146), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpd",   XSPR(31,467,147), XSPR_MASK, PPC860,     { RT } },
-{ "mticr",    XSPR(31,467,148), XSPR_MASK, PPC860,     { RT } },
-{ "mtder",    XSPR(31,467,149), XSPR_MASK, PPC860,     { RT } },
-{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860,     { RT } },
-{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpe",   XSPR(31,467,152), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpf",   XSPR(31,467,153), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmpg",   XSPR(31,467,154), XSPR_MASK, PPC860,     { RT } },
-{ "mtcmph",   XSPR(31,467,155), XSPR_MASK, PPC860,     { RT } },
-{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860,     { RT } },
-{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860,     { RT } },
-{ "mtictrl",  XSPR(31,467,158), XSPR_MASK, PPC860,     { RT } },
-{ "mtbar",    XSPR(31,467,159), XSPR_MASK, PPC860,     { RT } },
-{ "mtvrsave",XSPR(31,467,256), XSPR_MASK,    PPCVEC,   { RT } },
-{ "mtsprg",  XSPR(31,467,272), XSPRG_MASK,   PPC,      { SPRG, RS } },
-{ "mtsprg0", XSPR(31,467,272), XSPR_MASK,    PPC,      { RT } },
-{ "mtsprg1", XSPR(31,467,273), XSPR_MASK,    PPC,      { RT } },
-{ "mtsprg2", XSPR(31,467,274), XSPR_MASK,    PPC,      { RT } },
-{ "mtsprg3", XSPR(31,467,275), XSPR_MASK,    PPC,      { RT } },
-{ "mtsprg4", XSPR(31,467,276), XSPR_MASK,    PPC405,   { RT } },
-{ "mtsprg5", XSPR(31,467,277), XSPR_MASK,    PPC405,   { RT } },
-{ "mtsprg6", XSPR(31,467,278), XSPR_MASK,    PPC405,   { RT } },
-{ "mtsprg7", XSPR(31,467,279), XSPR_MASK,    PPC405,   { RT } },
-{ "mtasr",   XSPR(31,467,280), XSPR_MASK,    PPC64,    { RS } },
-{ "mtear",   XSPR(31,467,282), XSPR_MASK,    PPC,      { RS } },
-{ "mttbl",   XSPR(31,467,284), XSPR_MASK,    PPC,      { RS } },
-{ "mttbu",   XSPR(31,467,285), XSPR_MASK,    PPC,      { RS } },
-{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC,      { SPRBAT, RS } },
-{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC,      { SPRBAT, RS } },
-{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC,      { SPRBAT, RS } },
-{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC,      { SPRBAT, RS } },
-{ "mtzpr",   XSPR(31,467,944), XSPR_MASK, PPC403,      { RT } },
-{ "mtpid",   XSPR(31,467,945), XSPR_MASK, PPC403,      { RT } },
-{ "mtccr0",  XSPR(31,467,947), XSPR_MASK, PPC405,      { RT } },
-{ "mtiac3",  XSPR(31,467,948), XSPR_MASK, PPC405,      { RT } },
-{ "mtiac4",  XSPR(31,467,949), XSPR_MASK, PPC405,      { RT } },
-{ "mtdvc1",  XSPR(31,467,950), XSPR_MASK, PPC405,      { RT } },
-{ "mtdvc2",  XSPR(31,467,951), XSPR_MASK, PPC405,      { RT } },
-{ "mtsgr",   XSPR(31,467,953), XSPR_MASK, PPC403,      { RT } },
-{ "mtdcwr",  XSPR(31,467,954), XSPR_MASK, PPC403,      { RT } },
-{ "mtsler",  XSPR(31,467,955), XSPR_MASK, PPC405,      { RT } },
-{ "mtsu0r",  XSPR(31,467,956), XSPR_MASK, PPC405,      { RT } },
-{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405,      { RT } },
-{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403,      { RT } },
-{ "mtesr",   XSPR(31,467,980), XSPR_MASK, PPC403,      { RT } },
-{ "mtdear",  XSPR(31,467,981), XSPR_MASK, PPC403,      { RT } },
-{ "mtevpr",  XSPR(31,467,982), XSPR_MASK, PPC403,      { RT } },
-{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403,      { RT } },
-{ "mttsr",   XSPR(31,467,984), XSPR_MASK, PPC403,      { RT } },
-{ "mttcr",   XSPR(31,467,986), XSPR_MASK, PPC403,      { RT } },
-{ "mtpit",   XSPR(31,467,987), XSPR_MASK, PPC403,      { RT } },
-{ "mttbhi",  XSPR(31,467,988), XSPR_MASK, PPC403,      { RT } },
-{ "mttblo",  XSPR(31,467,989), XSPR_MASK, PPC403,      { RT } },
-{ "mtsrr2",  XSPR(31,467,990), XSPR_MASK, PPC403,      { RT } },
-{ "mtsrr3",  XSPR(31,467,991), XSPR_MASK, PPC403,      { RT } },
-{ "mtdbsr",  XSPR(31,467,1008), XSPR_MASK, PPC403,     { RT } },
-{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405,     { RT } },
-{ "mtiac1",  XSPR(31,467,1012), XSPR_MASK, PPC403,     { RT } },
-{ "mtiac2",  XSPR(31,467,1013), XSPR_MASK, PPC403,     { RT } },
-{ "mtdac1",  XSPR(31,467,1014), XSPR_MASK, PPC403,     { RT } },
-{ "mtdac2",  XSPR(31,467,1015), XSPR_MASK, PPC403,     { RT } },
-{ "mtdccr",  XSPR(31,467,1018), XSPR_MASK, PPC403,     { RT } },
-{ "mticcr",  XSPR(31,467,1019), XSPR_MASK, PPC403,     { RT } },
-{ "mtpbl1",  XSPR(31,467,1020), XSPR_MASK, PPC403,     { RT } },
-{ "mtpbu1",  XSPR(31,467,1021), XSPR_MASK, PPC403,     { RT } },
-{ "mtpbl2",  XSPR(31,467,1022), XSPR_MASK, PPC403,     { RT } },
-{ "mtpbu2",  XSPR(31,467,1023), XSPR_MASK, PPC403,     { RT } },
-{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,   { RT } },
-{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,   { RT } },
-{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,   { RT } },
-{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,   { RT } },
-{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,   { RT } },
-{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,   { RT } },
-{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,   { RT } },
-{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,   { RT } },
-{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,   { RT } },
-{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,   { RT } },
-{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,   { RT } },
-{ "mtspr",   X(31,467),               X_MASK,       COM,       { SPR, RS } },
+{ "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,     { RS } },
+{ "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,      { RS } },
+{ "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,      { RS } },
+{ "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,      { RS } },
+{ "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,    { RS } },
+{ "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,      { RS } },
+{ "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,      { RS } },
+{ "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,      { RS } },
+{ "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,      { RS } },
+{ "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,      { RS } },
+{ "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,    { RS } },
+{ "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,      { RS } },
+{ "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,      { RS } },
+{ "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,      { RS } },
+{ "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
+{ "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,   { RT } },
+{ "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,   { RT } },
+{ "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,   { RT } },
+{ "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,   { RT } },
+{ "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,   { RT } },
+{ "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,   { RT } },
+{ "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,   { RT } },
+{ "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,   { RT } },
+{ "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,   { RT } },
+{ "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg",    XSPR(31,467,272),  XSPRG_MASK,PPC,      { SPRG, RS } },
+{ "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,      { RT } },
+{ "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,      { RT } },
+{ "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,      { RT } },
+{ "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,      { RT } },
+{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,    { RS } },
+{ "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,      { RS } },
+{ "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,      { RS } },
+{ "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,      { RS } },
+{ "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
+{ "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
+{ "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
+{ "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
+{ "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
+{ "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
+{ "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
+{ "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
+{ "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
+{ "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,   { SPRBAT, RS } },
+{ "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
+{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RT } },
+{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RT } },
+{ "mtupmc2",   XSPR(31,467,938),  XSPR_MASK, PPC750,    { RT } },
+{ "mtusia",    XSPR(31,467,939),  XSPR_MASK, PPC750,    { RT } },
+{ "mtummcr1",  XSPR(31,467,940),  XSPR_MASK, PPC750,    { RT } },
+{ "mtupmc3",   XSPR(31,467,941),  XSPR_MASK, PPC750,    { RT } },
+{ "mtupmc4",   XSPR(31,467,942),  XSPR_MASK, PPC750,    { RT } },
+{ "mtzpr",     XSPR(31,467,944),  XSPR_MASK, PPC403,   { RT } },
+{ "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,   { RT } },
+{ "mtccr0",    XSPR(31,467,947),  XSPR_MASK, PPC405,   { RT } },
+{ "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,   { RT } },
+{ "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,   { RT } },
+{ "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,   { RT } },
+{ "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,   { RT } },
+{ "mtmmcr0",   XSPR(31,467,952),  XSPR_MASK, PPC750,    { RT } },
+{ "mtsgr",     XSPR(31,467,953),  XSPR_MASK, PPC403,   { RT } },
+{ "mtpmc1",    XSPR(31,467,953),  XSPR_MASK, PPC750,    { RT } },
+{ "mtdcwr",    XSPR(31,467,954),  XSPR_MASK, PPC403,   { RT } },
+{ "mtpmc2",    XSPR(31,467,954),  XSPR_MASK, PPC750,    { RT } },
+{ "mtsler",    XSPR(31,467,955),  XSPR_MASK, PPC405,   { RT } },
+{ "mtsia",     XSPR(31,467,955),  XSPR_MASK, PPC750,    { RT } },
+{ "mtsu0r",    XSPR(31,467,956),  XSPR_MASK, PPC405,   { RT } },
+{ "mtmmcr1",   XSPR(31,467,956),  XSPR_MASK, PPC750,    { RT } },
+{ "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,   { RT } },
+{ "mtpmc3",    XSPR(31,467,957),  XSPR_MASK, PPC750,    { RT } },
+{ "mtpmc4",    XSPR(31,467,958),  XSPR_MASK, PPC750,    { RT } },
+{ "mticdbdr",  XSPR(31,467,979),  XSPR_MASK, PPC403,   { RT } },
+{ "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,   { RT } },
+{ "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,   { RT } },
+{ "mtevpr",    XSPR(31,467,982),  XSPR_MASK, PPC403,   { RT } },
+{ "mtcdbcr",   XSPR(31,467,983),  XSPR_MASK, PPC403,   { RT } },
+{ "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,   { RT } },
+{ "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,   { RT } },
+{ "mtpit",     XSPR(31,467,987),  XSPR_MASK, PPC403,   { RT } },
+{ "mttbhi",    XSPR(31,467,988),  XSPR_MASK, PPC403,   { RT } },
+{ "mttblo",    XSPR(31,467,989),  XSPR_MASK, PPC403,   { RT } },
+{ "mtsrr2",    XSPR(31,467,990),  XSPR_MASK, PPC403,   { RT } },
+{ "mtsrr3",    XSPR(31,467,991),  XSPR_MASK, PPC403,   { RT } },
+{ "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,   { RT } },
+{ "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,   { RT } },
+{ "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,   { RT } },
+{ "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,   { RT } },
+{ "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,   { RT } },
+{ "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,   { RT } },
+{ "mtl2cr",    XSPR(31,467,1017), XSPR_MASK, PPC750,    { RT } },
+{ "mtdccr",    XSPR(31,467,1018), XSPR_MASK, PPC403,   { RT } },
+{ "mticcr",    XSPR(31,467,1019), XSPR_MASK, PPC403,   { RT } },
+{ "mtictc",    XSPR(31,467,1019), XSPR_MASK, PPC750,    { RT } },
+{ "mtpbl1",    XSPR(31,467,1020), XSPR_MASK, PPC403,   { RT } },
+{ "mtthrm1",   XSPR(31,467,1020), XSPR_MASK, PPC750,    { RT } },
+{ "mtpbu1",    XSPR(31,467,1021), XSPR_MASK, PPC403,   { RT } },
+{ "mtthrm2",   XSPR(31,467,1021), XSPR_MASK, PPC750,    { RT } },
+{ "mtpbl2",    XSPR(31,467,1022), XSPR_MASK, PPC403,   { RT } },
+{ "mtthrm3",   XSPR(31,467,1022), XSPR_MASK, PPC750,    { RT } },
+{ "mtpbu2",    XSPR(31,467,1023), XSPR_MASK, PPC403,   { RT } },
+{ "mtspr",     X(31,467),        X_MASK,    COM,       { SPR, RS } },

 
 { "dcbi",    X(31,470),        XRT_MASK,       PPC,            { RA, RB } },
 
 
 { "dcbi",    X(31,470),        XRT_MASK,       PPC,            { RA, RB } },
 


@@ -3512,6 +4138,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "dcread",  X(31,486),        X_MASK,         PPC403,         { RT, RA, RB }},
 
 
 { "dcread",  X(31,486),        X_MASK,         PPC403,         { RT, RA, RB }},
 

+{ "mtpmr",   X(31,462),        X_MASK,         PPCPMR,         { PMR, RS }},
+
+{ "icbtls",  X(31,486),        X_MASK,         PPCCHLK,        { CT, RA, RB }},
+

 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,          { RT, RA } },
 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,       { RT, RA } },
 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,          { RT, RA } },
 { "nabs",    XO(31,488,0,0), XORB_MASK, M601,          { RT, RA } },
 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64,       { RT, RA } },
 { "nabs.",   XO(31,488,0,1), XORB_MASK, M601,          { RT, RA } },


@@ -3532,6 +4162,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "divwo",   XO(31,491,1,0), XO_MASK,  PPC,            { RT, RA, RB } },
 { "divwo.",  XO(31,491,1,1), XO_MASK,  PPC,            { RT, RA, RB } },
 
 { "divwo",   XO(31,491,1,0), XO_MASK,  PPC,            { RT, RA, RB } },
 { "divwo.",  XO(31,491,1,1), XO_MASK,  PPC,            { RT, RA, RB } },
 

+{ "icbtlse", X(31,494),        X_MASK,         PPCCHLK64,      { CT, RA, RB }},
+

 { "slbia",   X(31,498),        0xffffffff,     PPC64,          { 0 } },
 
 { "cli",     X(31,502), XRB_MASK,      POWER,          { RT, RA } },
 { "slbia",   X(31,498),        0xffffffff,     PPC64,          { 0 } },
 
 { "cli",     X(31,502), XRB_MASK,      POWER,          { RT, RA } },


@@ -3540,7 +4172,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "mcrxr",   X(31,512),        XRARB_MASK|(3<<21), COM,        { BF } },
 
 
 { "mcrxr",   X(31,512),        XRARB_MASK|(3<<21), COM,        { BF } },
 

-{ "mcrxr64", X(31,544),        XRARB_MASK|(3<<21), BOOKE,      { BF } },
+{ "bblels",  X(31,518),        X_MASK,         PPCBRLK,        { 0 }},
+{ "mcrxr64", X(31,544),        XRARB_MASK|(3<<21), BOOKE64,    { BF } },

 
 { "clcs",    X(31,531), XRB_MASK,      M601,           { RT, RA } },
 
 
 { "clcs",    X(31,531), XRB_MASK,      M601,           { RT, RA } },
 


@@ -3570,6 +4203,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lfsxe",   X(31,543),        X_MASK,         BOOKE64,        { FRT, RA, RB } },
 
 
 { "lfsxe",   X(31,543),        X_MASK,         BOOKE64,        { FRT, RA, RB } },
 

+{ "bbelr",   X(31,550),        X_MASK,         PPCBRLK,        { 0 }},

 { "tlbsync", X(31,566),        0xffffffff,     PPC,            { 0 } },
 
 { "lfsux",   X(31,567),        X_MASK,         COM,            { FRT, RAS, RB } },
 { "tlbsync", X(31,566),        0xffffffff,     PPC,            { 0 } },
 
 { "lfsux",   X(31,567),        X_MASK,         COM,            { FRT, RAS, RB } },


@@ -3583,9 +4217,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPCONLY,     { 0 } },
 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,       { 0 } },
 
 { "lwsync",  XSYNC(31,598,1), 0xffffffff, PPCONLY,     { 0 } },
 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64,       { 0 } },

+{ "msync",   X(31,598), 0xffffffff,    BOOKE,          { 0 } },

 { "sync",    X(31,598), XSYNC_MASK,    PPCCOM,         { LS } },
 { "dcs",     X(31,598), 0xffffffff,    PWRCOM,         { 0 } },
 { "sync",    X(31,598), XSYNC_MASK,    PPCCOM,         { LS } },
 { "dcs",     X(31,598), 0xffffffff,    PWRCOM,         { 0 } },

-{ "msync",   X(31,598), 0xf80007fe,    BOOKE,          { 0 } },

 
 { "lfdx",    X(31,599), X_MASK,                COM,            { FRT, RA, RB } },
 
 
 { "lfdx",    X(31,599), X_MASK,                COM,            { FRT, RA, RB } },
 


@@ -3652,7 +4286,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "stfduxe", X(31,767),        X_MASK,         BOOKE64,        { FRS, RAS, RB } },
 
 { "tlbivax", X(31,786),        XRT_MASK,       BOOKE,          { RA, RB } },
 { "stfduxe", X(31,767),        X_MASK,         BOOKE64,        { FRS, RAS, RB } },
 
 { "tlbivax", X(31,786),        XRT_MASK,       BOOKE,          { RA, RB } },

-{ "tlbivaxe",X(31,787),        XRT_MASK,       BOOKE,          { RA, RB } },
+{ "tlbivaxe",X(31,787),        XRT_MASK,       BOOKE64,        { RA, RB } },

 
 { "lhbrx",   X(31,790),        X_MASK,         COM,            { RT, RA, RB } },
 
 
 { "lhbrx",   X(31,790),        X_MASK,         COM,            { RT, RA, RB } },
 


@@ -3681,14 +4315,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "slbmfev", X(31,851), XRA_MASK,      PPC64,          { RT, RB } },
 
 
 { "slbmfev", X(31,851), XRA_MASK,      PPC64,          { RT, RB } },
 

+{ "mbar",    X(31,854),        X_MASK,         BOOKE,          { MO } },

 { "eieio",   X(31,854),        0xffffffff,     PPC,            { 0 } },
 { "eieio",   X(31,854),        0xffffffff,     PPC,            { 0 } },

-{ "mbar",    X(31,854),        0xffffffff,     BOOKE,          { MO } },

 
 { "tlbsx",   XRC(31,914,0), X_MASK,    PPC403,         { RT, RA, RB } },
 { "tlbsx.",  XRC(31,914,1), X_MASK,    PPC403,         { RT, RA, RB } },
 
 { "tlbsx",   XRC(31,914,0), X_MASK,    BOOKE,          { RA, RB } },
 
 { "tlbsx",   XRC(31,914,0), X_MASK,    PPC403,         { RT, RA, RB } },
 { "tlbsx.",  XRC(31,914,1), X_MASK,    PPC403,         { RT, RA, RB } },
 
 { "tlbsx",   XRC(31,914,0), X_MASK,    BOOKE,          { RA, RB } },

-{ "tlbsxe",  XRC(31,915,0), X_MASK,    BOOKE,          { RA, RB } },
+{ "tlbsx.",  XRC(31,914,1), X_MASK,    BOOKE,          { RA, RB } },
+{ "tlbsxe",  XRC(31,915,0), X_MASK,    BOOKE64,        { RA, RB } },
+{ "tlbsxe.", XRC(31,915,1), X_MASK,    BOOKE64,        { RA, RB } },

 
 { "slbmfee", X(31,915), XRA_MASK,      PPC64,          { RT, RB } },
 
 
 { "slbmfee", X(31,915), XRA_MASK,      PPC64,          { RT, RB } },
 


@@ -3709,10 +4345,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stdxe",   X(31,927), X_MASK,                BOOKE64,        { RS, RA, RB } },
 
 
 { "stdxe",   X(31,927), X_MASK,                BOOKE64,        { RS, RA, RB } },
 

-{ "tlbre",   X(31,946),        X_MASK,         BOOKE,          { RT, RA, WS } },
+{ "tlbre",   X(31,946),        X_MASK,         BOOKE,          { 0 } },

 
 { "tlbrehi", XTLB(31,946,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbrelo", XTLB(31,946,1), XTLB_MASK,        PPC403,         { RT, RA } },
 
 { "tlbrehi", XTLB(31,946,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbrelo", XTLB(31,946,1), XTLB_MASK,        PPC403,         { RT, RA } },

+{ "tlbre",   X(31,946),        X_MASK,         PPC403,         { RS, RA, SH } },

 
 { "sraiq",   XRC(31,952,0), X_MASK,    M601,           { RA, RS, SH } },
 { "sraiq.",  XRC(31,952,1), X_MASK,    M601,           { RA, RS, SH } },
 
 { "sraiq",   XRC(31,952,0), X_MASK,    M601,           { RA, RS, SH } },
 { "sraiq.",  XRC(31,952,1), X_MASK,    M601,           { RA, RS, SH } },


@@ -3724,20 +4361,20 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "iccci",   X(31,966),        XRT_MASK,       PPC403,         { RA, RB } },
 
 
 { "iccci",   X(31,966),        XRT_MASK,       PPC403,         { RA, RB } },
 

+{ "tlbwe",   X(31,978),        X_MASK,         BOOKE,          { 0 } },
+

 { "tlbld",   X(31,978),        XRTRA_MASK,     PPC,            { RB } },
 
 { "tlbwehi", XTLB(31,978,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbwe",   X(31,978),        X_MASK,         PPC403,         { RS, RA, SH } },
 
 { "tlbld",   X(31,978),        XRTRA_MASK,     PPC,            { RB } },
 
 { "tlbwehi", XTLB(31,978,0), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,        PPC403,         { RT, RA } },
 { "tlbwe",   X(31,978),        X_MASK,         PPC403,         { RS, RA, SH } },
 

-{ "tlbwe",   X(31,978),        X_MASK,         BOOKE,          { RT, RA, WS } },
-

 { "icbi",    X(31,982),        XRT_MASK,       PPC,            { RA, RB } },
 
 { "stfiwx",  X(31,983),        X_MASK,         PPC,            { FRS, RA, RB } },
 
 { "icbi",    X(31,982),        XRT_MASK,       PPC,            { RA, RB } },
 
 { "stfiwx",  X(31,983),        X_MASK,         PPC,            { FRS, RA, RB } },
 

-{ "extsw",   XRC(31,986,0), XRB_MASK,  PPC,            { RA, RS } },
-{ "extsw.",  XRC(31,986,1), XRB_MASK,  PPC,            { RA, RS } },
+{ "extsw",   XRC(31,986,0), XRB_MASK,  PPC64 | BOOKE64,{ RA, RS } },
+{ "extsw.",  XRC(31,986,1), XRB_MASK,  PPC64,          { RA, RS } },

 
 { "icread",  X(31,998),        XRT_MASK,       PPC403,         { RA, RB } },
 
 
 { "icread",  X(31,998),        XRT_MASK,       PPC403,         { RA, RB } },
 


@@ -3818,6 +4455,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stfdu",   OP(55),   OP_MASK,        COM,            { FRS, D, RAS } },
 
 
 { "stfdu",   OP(55),   OP_MASK,        COM,            { FRS, D, RAS } },
 

+{ "lq",      OP(56),   OP_MASK,        POWER4,         { RTQ, DQ, RAQ } },
+

 { "lfq",     OP(56),   OP_MASK,        POWER2,         { FRT, D, RA } },
 
 { "lfqu",    OP(57),   OP_MASK,        POWER2,         { FRT, D, RA } },
 { "lfq",     OP(56),   OP_MASK,        POWER2,         { FRT, D, RA } },
 
 { "lfqu",    OP(57),   OP_MASK,        POWER2,         { FRT, D, RA } },


@@ -3894,6 +4533,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stdu",    DSO(62,1),        DS_MASK,        PPC64,          { RS, DS, RAS } },
 
 
 { "stdu",    DSO(62,1),        DS_MASK,        PPC64,          { RS, DS, RAS } },
 

+{ "stq",     DSO(62,2),        DS_MASK,        POWER4,         { RSQ, DS, RA } },
+

 { "fcmpu",   X(63,0),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
 
 { "frsp",    XRC(63,12,0), XRA_MASK,   COM,            { FRT, FRB } },
 { "fcmpu",   X(63,0),  X_MASK|(3<<21), COM,            { BF, FRA, FRB } },
 
 { "frsp",    XRC(63,12,0), XRA_MASK,   COM,            { FRT, FRB } },


@@ -4035,8 +4676,8 @@ const struct powerpc_macro powerpc_macros[] = {
 
 { "extlwi",  4,   PPCCOM,      "rlwinm %0,%1,%3,0,(%2)-1" },
 { "extlwi.", 4,   PPCCOM,      "rlwinm. %0,%1,%3,0,(%2)-1" },
 
 { "extlwi",  4,   PPCCOM,      "rlwinm %0,%1,%3,0,(%2)-1" },
 { "extlwi.", 4,   PPCCOM,      "rlwinm. %0,%1,%3,0,(%2)-1" },

-{ "extrwi",  4,   PPCCOM,      "rlwinm %0,%1,(%2)+(%3),32-(%2),31" },
-{ "extrwi.", 4,   PPCCOM,      "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" },
+{ "extrwi",  4,   PPCCOM,      "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
+{ "extrwi.", 4,   PPCCOM,      "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },

 { "inslwi",  4,   PPCCOM,      "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
 { "inslwi.", 4,   PPCCOM,      "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
 { "insrwi",  4,   PPCCOM,      "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
 { "inslwi",  4,   PPCCOM,      "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
 { "inslwi.", 4,   PPCCOM,      "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
 { "insrwi",  4,   PPCCOM,      "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },


@@ -4055,7 +4696,6 @@ const struct powerpc_macro powerpc_macros[] = {
 { "clrrwi.", 3,   PPCCOM,      "rlwinm. %0,%1,0,0,31-(%2)" },
 { "clrlslwi",4,   PPCCOM,      "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
 { "clrlslwi.",4,  PPCCOM,      "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
 { "clrrwi.", 3,   PPCCOM,      "rlwinm. %0,%1,0,0,31-(%2)" },
 { "clrlslwi",4,   PPCCOM,      "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
 { "clrlslwi.",4,  PPCCOM,      "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },

-

 };
 
 const int powerpc_num_macros =
 };
 
 const int powerpc_num_macros =