- oper = opcode.op + *s - '0';
- if (do_bang)
- PC ('!');
-
- if (do_es)
- {
- if (oper->use_es && indirect_type (oper->type))
- PR (PS, "es:");
- }
-
- else if (do_cond)
- {
- PR (PS, "%s", condition_names[oper->condition]);
- }
-
- else
- switch (oper->type)
+ oper = *s == '0' ? &opcode.op[0] : &opcode.op[1];
+ if (do_es)
+ {
+ if (oper->use_es && indirect_type (oper->type))
+ PR (PS, "es:");
+ }
+
+ if (do_bang)
+ {
+ /* If we are going to display SP by name, we must omit the bang. */
+ if ((oper->type == RL78_Operand_Indirect
+ || oper->type == RL78_Operand_BitIndirect)
+ && oper->reg == RL78_Reg_None
+ && do_sfr
+ && ((oper->addend == 0xffff8 && opcode.size == RL78_Word)
+ || (oper->addend == 0x0fff8 && do_es && opcode.size == RL78_Word)))
+ ;
+ else
+ PC ('!');
+ }
+
+ if (do_cond)
+ {
+ PR (PS, "%s", condition_names[oper->condition]);
+ break;
+ }
+
+ switch (oper->type)
+ {
+ case RL78_Operand_Immediate:
+ if (do_addr)
+ dis->print_address_func (oper->addend, dis);
+ else if (do_hex
+ || oper->addend > 999
+ || oper->addend < -999)
+ PR (PS, "%#x", oper->addend);
+ else
+ PR (PS, "%d", oper->addend);
+ break;
+
+ case RL78_Operand_Register:
+ PR (PS, "%s", register_names[oper->reg]);
+ break;
+
+ case RL78_Operand_Bit:
+ PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
+ break;
+
+ case RL78_Operand_Indirect:
+ case RL78_Operand_BitIndirect:
+ switch (oper->reg)