-e700000000f3 va VRR_VVV0U "vector add" z13 zarch
-e700000000f3 vab VRR_VVV "vector add byte" z13 zarch
-e700000010f3 vah VRR_VVV "vector add halfword" z13 zarch
-e700000020f3 vaf VRR_VVV "vector add word" z13 zarch
-e700000030f3 vag VRR_VVV "vector add double word" z13 zarch
-e700000040f3 vaq VRR_VVV "vector add quad word" z13 zarch
-e700000000f1 vacc VRR_VVV0U "vector add compute carry" z13 zarch
-e700000000f1 vaccb VRR_VVV "vector add compute carry byte" z13 zarch
-e700000010f1 vacch VRR_VVV "vector add compute carry halfword" z13 zarch
-e700000020f1 vaccf VRR_VVV "vector add compute carry word" z13 zarch
-e700000030f1 vaccg VRR_VVV "vector add compute carry doubleword" z13 zarch
-e700000040f1 vaccq VRR_VVV "vector add compute carry quadword" z13 zarch
-e700000000bb vac VRR_VVVU0V "vector add with carry" z13 zarch
-e700040000bb vacq VRR_VVV0V "vector add with carry quadword" z13 zarch
-e700000000b9 vaccc VRR_VVVU0V "vector add with carry compute carry" z13 zarch
-e700040000b9 vacccq VRR_VVV0V "vector add with carry compute carry quadword" z13 zarch
-e70000000068 vn VRR_VVV "vector and" z13 zarch
-e70000000069 vnc VRR_VVV "vector and with complement" z13 zarch
-e700000000f2 vavg VRR_VVV0U "vector average" z13 zarch
-e700000000f2 vavgb VRR_VVV "vector average byte" z13 zarch
-e700000010f2 vavgh VRR_VVV "vector average half word" z13 zarch
-e700000020f2 vavgf VRR_VVV "vector average word" z13 zarch
-e700000030f2 vavgg VRR_VVV "vector average double word" z13 zarch
-e700000000f0 vavgl VRR_VVV0U "vector average logical" z13 zarch
-e700000000f0 vavglb VRR_VVV "vector average logical byte" z13 zarch
-e700000010f0 vavglh VRR_VVV "vector average logical half word" z13 zarch
-e700000020f0 vavglf VRR_VVV "vector average logical word" z13 zarch
-e700000030f0 vavglg VRR_VVV "vector average logical double word" z13 zarch
-e70000000066 vcksm VRR_VVV "vector checksum" z13 zarch
-e700000000db vec VRR_VV0U "vector element compare" z13 zarch
-e700000000db vecb VRR_VV "vector element compare byte" z13 zarch
-e700000010db vech VRR_VV "vector element compare half word" z13 zarch
-e700000020db vecf VRR_VV "vector element compare word" z13 zarch
-e700000030db vecg VRR_VV "vector element compare double word" z13 zarch
-e700000000d9 vecl VRR_VV0U "vector element compare logical" z13 zarch
-e700000000d9 veclb VRR_VV "vector element compare logical byte" z13 zarch
-e700000010d9 veclh VRR_VV "vector element compare logical half word" z13 zarch
-e700000020d9 veclf VRR_VV "vector element compare logical word" z13 zarch
-e700000030d9 veclg VRR_VV "vector element compare logical double word" z13 zarch
-e700000000f8 vceq VRR_VVV0U0U "vector compare equal" z13 zarch
-e700000000f8 vceqb VRR_VVV "vector compare equal byte" z13 zarch
-e700000010f8 vceqh VRR_VVV "vector compare equal half word" z13 zarch
-e700000020f8 vceqf VRR_VVV "vector compare equal word" z13 zarch
-e700000030f8 vceqg VRR_VVV "vector compare equal double word" z13 zarch
-e700001000f8 vceqbs VRR_VVV "vector compare equal byte" z13 zarch
-e700001010f8 vceqhs VRR_VVV "vector compare equal half word" z13 zarch
-e700001020f8 vceqfs VRR_VVV "vector compare equal word" z13 zarch
-e700001030f8 vceqgs VRR_VVV "vector compare equal double word" z13 zarch
-e700000000fb vch VRR_VVV0U0U "vector compare high" z13 zarch
-e700000000fb vchb VRR_VVV "vector compare high byte" z13 zarch
-e700000010fb vchh VRR_VVV "vector compare high half word" z13 zarch
-e700000020fb vchf VRR_VVV "vector compare high word" z13 zarch
-e700000030fb vchg VRR_VVV "vector compare high double word" z13 zarch
-e700001000fb vchbs VRR_VVV "vector compare high byte" z13 zarch
-e700001010fb vchhs VRR_VVV "vector compare high half word" z13 zarch
-e700001020fb vchfs VRR_VVV "vector compare high word" z13 zarch
-e700001030fb vchgs VRR_VVV "vector compare high double word" z13 zarch
-e700000000f9 vchl VRR_VVV0U0U "vector compare high logical" z13 zarch
-e700000000f9 vchlb VRR_VVV "vector compare high logical byte" z13 zarch
-e700000010f9 vchlh VRR_VVV "vector compare high logical half word" z13 zarch
-e700000020f9 vchlf VRR_VVV "vector compare high logical word" z13 zarch
-e700000030f9 vchlg VRR_VVV "vector compare high logical double word" z13 zarch
-e700001000f9 vchlbs VRR_VVV "vector compare high logical byte" z13 zarch
-e700001010f9 vchlhs VRR_VVV "vector compare high logical half word" z13 zarch
-e700001020f9 vchlfs VRR_VVV "vector compare high logical word" z13 zarch
-e700001030f9 vchlgs VRR_VVV "vector compare high logical double word" z13 zarch
-e70000000053 vclz VRR_VV0U "vector count leading zeros" z13 zarch
-e70000000053 vclzb VRR_VV "vector count leading zeros byte" z13 zarch
-e70000001053 vclzh VRR_VV "vector count leading zeros halfword" z13 zarch
-e70000002053 vclzf VRR_VV "vector count leading zeros word" z13 zarch
-e70000003053 vclzg VRR_VV "vector count leading zeros doubleword" z13 zarch
-e70000000052 vctz VRR_VV0U "vector count trailing zeros" z13 zarch
-e70000000052 vctzb VRR_VV "vector count trailing zeros byte" z13 zarch
-e70000001052 vctzh VRR_VV "vector count trailing zeros halfword" z13 zarch
-e70000002052 vctzf VRR_VV "vector count trailing zeros word" z13 zarch
-e70000003052 vctzg VRR_VV "vector count trailing zeros doubleword" z13 zarch
-e7000000006d vx VRR_VVV "vector exclusive or" z13 zarch
-e700000000b4 vgfm VRR_VVV0U "vector galois field multiply sum" z13 zarch
-e700000000b4 vgfmb VRR_VVV "vector galois field multiply sum byte" z13 zarch
-e700000010b4 vgfmh VRR_VVV "vector galois field multiply sum halfword" z13 zarch
-e700000020b4 vgfmf VRR_VVV "vector galois field multiply sum word" z13 zarch
-e700000030b4 vgfmg VRR_VVV "vector galois field multiply sum doubleword" z13 zarch
-e700000000bc vgfma VRR_VVVU0V "vector galois field multiply sum and accumulate" z13 zarch
-e700000000bc vgfmab VRR_VVV0V "vector galois field multiply sum and accumulate byte" z13 zarch
-e700010000bc vgfmah VRR_VVV0V "vector galois field multiply sum and accumulate halfword" z13 zarch
-e700020000bc vgfmaf VRR_VVV0V "vector galois field multiply sum and accumulate word" z13 zarch
-e700030000bc vgfmag VRR_VVV0V "vector galois field multiply sum and accumulate doubleword" z13 zarch
-e700000000de vlc VRR_VV0U "vector load complement" z13 zarch
-e700000000de vlcb VRR_VV "vector load complement byte" z13 zarch
-e700000010de vlch VRR_VV "vector load complement halfword" z13 zarch
-e700000020de vlcf VRR_VV "vector load complement word" z13 zarch
-e700000030de vlcg VRR_VV "vector load complement doubleword" z13 zarch
-e700000000df vlp VRR_VV0U "vector load positive" z13 zarch
-e700000000df vlpb VRR_VV "vector load positive byte" z13 zarch
-e700000010df vlph VRR_VV "vector load positive halfword" z13 zarch
-e700000020df vlpf VRR_VV "vector load positive word" z13 zarch
-e700000030df vlpg VRR_VV "vector load positive doubleword" z13 zarch
-e700000000ff vmx VRR_VVV0U "vector maximum" z13 zarch
-e700000000ff vmxb VRR_VVV "vector maximum byte" z13 zarch
-e700000010ff vmxh VRR_VVV "vector maximum halfword" z13 zarch
-e700000020ff vmxf VRR_VVV "vector maximum word" z13 zarch
-e700000030ff vmxg VRR_VVV "vector maximum doubleword" z13 zarch
-e700000000fd vmxl VRR_VVV0U "vector maximum logical" z13 zarch
-e700000000fd vmxlb VRR_VVV "vector maximum logical byte" z13 zarch
-e700000010fd vmxlh VRR_VVV "vector maximum logical halfword" z13 zarch
-e700000020fd vmxlf VRR_VVV "vector maximum logical word" z13 zarch
-e700000030fd vmxlg VRR_VVV "vector maximum logical doubleword" z13 zarch
-e700000000fe vmn VRR_VVV0U "vector minimum" z13 zarch
-e700000000fe vmnb VRR_VVV "vector minimum byte" z13 zarch
-e700000010fe vmnh VRR_VVV "vector minimum halfword" z13 zarch
-e700000020fe vmnf VRR_VVV "vector minimum word" z13 zarch
-e700000030fe vmng VRR_VVV "vector minimum doubleword" z13 zarch
-e700000000fc vmnl VRR_VVV0U "vector minimum logical" z13 zarch
-e700000000fc vmnlb VRR_VVV "vector minimum logical byte" z13 zarch
-e700000010fc vmnlh VRR_VVV "vector minimum logical halfword" z13 zarch
-e700000020fc vmnlf VRR_VVV "vector minimum logical word" z13 zarch
-e700000030fc vmnlg VRR_VVV "vector minimum logical doubleword" z13 zarch
-e700000000aa vmal VRR_VVVU0V "vector multiply and add low" z13 zarch
-e700000000aa vmalb VRR_VVV0V "vector multiply and add low byte" z13 zarch
-e700010000aa vmalhw VRR_VVV0V "vector multiply and add low halfword" z13 zarch
-e700020000aa vmalf VRR_VVV0V "vector multiply and add low word" z13 zarch
-e700000000ab vmah VRR_VVVU0V "vector multiply and add high" z13 zarch
-e700000000ab vmahb VRR_VVV0V "vector multiply and add high byte" z13 zarch
-e700010000ab vmahh VRR_VVV0V "vector multiply and add high halfword" z13 zarch
-e700020000ab vmahf VRR_VVV0V "vector multiply and add high word" z13 zarch
-e700000000a9 vmalh VRR_VVVU0V "vector multiply and add logical high" z13 zarch
-e700000000a9 vmalhb VRR_VVV0V "vector multiply and add logical high byte" z13 zarch
-e700010000a9 vmalhh VRR_VVV0V "vector multiply and add logical high halfword" z13 zarch
-e700020000a9 vmalhf VRR_VVV0V "vector multiply and add logical high word" z13 zarch
-e700000000ae vmae VRR_VVVU0V "vector multiply and add even" z13 zarch
-e700000000ae vmaeb VRR_VVV0V "vector multiply and add even byte" z13 zarch
-e700010000ae vmaeh VRR_VVV0V "vector multiply and add even halfword" z13 zarch
-e700020000ae vmaef VRR_VVV0V "vector multiply and add even word" z13 zarch
-e700000000ac vmale VRR_VVVU0V "vector multiply and add logical even" z13 zarch
-e700000000ac vmaleb VRR_VVV0V "vector multiply and add logical even byte" z13 zarch
-e700010000ac vmaleh VRR_VVV0V "vector multiply and add logical even halfword" z13 zarch
-e700020000ac vmalef VRR_VVV0V "vector multiply and add logical even word" z13 zarch
-e700000000af vmao VRR_VVVU0V "vector multiply and add odd" z13 zarch
-e700000000af vmaob VRR_VVV0V "vector multiply and add odd byte" z13 zarch
-e700010000af vmaoh VRR_VVV0V "vector multiply and add odd halfword" z13 zarch
-e700020000af vmaof VRR_VVV0V "vector multiply and add odd word" z13 zarch
-e700000000ad vmalo VRR_VVVU0V "vector multiply and add logical odd" z13 zarch
-e700000000ad vmalob VRR_VVV0V "vector multiply and add logical odd byte" z13 zarch
-e700010000ad vmaloh VRR_VVV0V "vector multiply and add logical odd halfword" z13 zarch
-e700020000ad vmalof VRR_VVV0V "vector multiply and add logical odd word" z13 zarch
-e700000000a3 vmh VRR_VVV0U "vector multiply high" z13 zarch
-e700000000a3 vmhb VRR_VVV "vector multiply high byte" z13 zarch
-e700000010a3 vmhh VRR_VVV "vector multiply high halfword" z13 zarch
-e700000020a3 vmhf VRR_VVV "vector multiply high word" z13 zarch
-e700000000a1 vmlh VRR_VVV0U "vector multiply logical high" z13 zarch
-e700000000a1 vmlhb VRR_VVV "vector multiply logical high byte" z13 zarch
-e700000010a1 vmlhh VRR_VVV "vector multiply logical high halfword" z13 zarch
-e700000020a1 vmlhf VRR_VVV "vector multiply logical high word" z13 zarch
-e700000000a2 vml VRR_VVV0U "vector multiply low" z13 zarch
-e700000000a2 vmlb VRR_VVV "vector multiply low byte" z13 zarch
-e700000010a2 vmlhw VRR_VVV "vector multiply low halfword" z13 zarch
-e700000020a2 vmlf VRR_VVV "vector multiply low word" z13 zarch
-e700000000a6 vme VRR_VVV0U "vector multiply even" z13 zarch
-e700000000a6 vmeb VRR_VVV "vector multiply even byte" z13 zarch
-e700000010a6 vmeh VRR_VVV "vector multiply even halfword" z13 zarch
-e700000020a6 vmef VRR_VVV "vector multiply even word" z13 zarch
-e700000000a4 vmle VRR_VVV0U "vector multiply logical even" z13 zarch
-e700000000a4 vmleb VRR_VVV "vector multiply logical even byte" z13 zarch
-e700000010a4 vmleh VRR_VVV "vector multiply logical even halfword" z13 zarch
-e700000020a4 vmlef VRR_VVV "vector multiply logical even word" z13 zarch
-e700000000a7 vmo VRR_VVV0U "vector multiply odd" z13 zarch
-e700000000a7 vmob VRR_VVV "vector multiply odd byte" z13 zarch
-e700000010a7 vmoh VRR_VVV "vector multiply odd halfword" z13 zarch
-e700000020a7 vmof VRR_VVV "vector multiply odd word" z13 zarch
-e700000000a5 vmlo VRR_VVV0U "vector multiply logical odd" z13 zarch
-e700000000a5 vmlob VRR_VVV "vector multiply logical odd byte" z13 zarch
-e700000010a5 vmloh VRR_VVV "vector multiply logical odd halfword" z13 zarch
-e700000020a5 vmlof VRR_VVV "vector multiply logical odd word" z13 zarch
-e7000000006b vno VRR_VVV "vector nor" z13 zarch
-e7000000006b vnot VRR_VVV2 "vector not" z13 zarch
-e7000000006a vo VRR_VVV "vector or" z13 zarch
-e70000000050 vpopct VRR_VV0U "vector population count" z13 zarch
-e70000000073 verllv VRR_VVV0U "vector element rotate left logical reg" z13 zarch
-e70000000073 verllvb VRR_VVV "vector element rotate left logical reg byte" z13 zarch
-e70000001073 verllvh VRR_VVV "vector element rotate left logical reg halfword" z13 zarch
-e70000002073 verllvf VRR_VVV "vector element rotate left logical reg word" z13 zarch
-e70000003073 verllvg VRR_VVV "vector element rotate left logical reg doubleword" z13 zarch
-e70000000033 verll VRS_VVRDU "vector element rotate left logical mem" z13 zarch
-e70000000033 verllb VRS_VVRD "vector element rotate left logical mem byte" z13 zarch
-e70000001033 verllh VRS_VVRD "vector element rotate left logical mem halfword" z13 zarch
-e70000002033 verllf VRS_VVRD "vector element rotate left logical mem word" z13 zarch
-e70000003033 verllg VRS_VVRD "vector element rotate left logical mem doubleword" z13 zarch
-e70000000072 verim VRI_VVV0UU "vector element rotate and insert under mask" z13 zarch
-e70000000072 verimb VRI_VVV0U "vector element rotate and insert under mask byte" z13 zarch
-e70000001072 verimh VRI_VVV0U "vector element rotate and insert under mask halfword" z13 zarch
-e70000002072 verimf VRI_VVV0U "vector element rotate and insert under mask word" z13 zarch
-e70000003072 verimg VRI_VVV0U "vector element rotate and insert under mask doubleword" z13 zarch
-e70000000070 veslv VRR_VVV0U "vector element shift left reg" z13 zarch
-e70000000070 veslvb VRR_VVV "vector element shift left reg byte" z13 zarch
-e70000001070 veslvh VRR_VVV "vector element shift left reg halfword" z13 zarch
-e70000002070 veslvf VRR_VVV "vector element shift left reg word" z13 zarch
-e70000003070 veslvg VRR_VVV "vector element shift left reg doubleword" z13 zarch
-e70000000030 vesl VRS_VVRDU "vector element shift left mem" z13 zarch
-e70000000030 veslb VRS_VVRD "vector element shift left mem byte" z13 zarch
-e70000001030 veslh VRS_VVRD "vector element shift left mem halfword" z13 zarch
-e70000002030 veslf VRS_VVRD "vector element shift left mem word" z13 zarch
-e70000003030 veslg VRS_VVRD "vector element shift left mem doubleword" z13 zarch
-e7000000007a vesrav VRR_VVV0U "vector element shift right arithmetic reg" z13 zarch
-e7000000007a vesravb VRR_VVV "vector element shift right arithmetic reg byte" z13 zarch
-e7000000107a vesravh VRR_VVV "vector element shift right arithmetic reg halfword" z13 zarch
-e7000000207a vesravf VRR_VVV "vector element shift right arithmetic reg word" z13 zarch
-e7000000307a vesravg VRR_VVV "vector element shift right arithmetic reg doubleword" z13 zarch
-e7000000003a vesra VRS_VVRDU "vector element shift right arithmetic mem" z13 zarch
-e7000000003a vesrab VRS_VVRD "vector element shift right arithmetic mem byte" z13 zarch
-e7000000103a vesrah VRS_VVRD "vector element shift right arithmetic mem halfword" z13 zarch
-e7000000203a vesraf VRS_VVRD "vector element shift right arithmetic mem word" z13 zarch
-e7000000303a vesrag VRS_VVRD "vector element shift right arithmetic mem doubleword" z13 zarch
-e70000000078 vesrlv VRR_VVV0U "vector element shift right logical reg" z13 zarch
-e70000000078 vesrlvb VRR_VVV "vector element shift right logical reg byte" z13 zarch
-e70000001078 vesrlvh VRR_VVV "vector element shift right logical reg halfword" z13 zarch
-e70000002078 vesrlvf VRR_VVV "vector element shift right logical reg word" z13 zarch
-e70000003078 vesrlvg VRR_VVV "vector element shift right logical reg doubleword" z13 zarch
-e70000000038 vesrl VRS_VVRDU "vector element shift right logical mem" z13 zarch
-e70000000038 vesrlb VRS_VVRD "vector element shift right logical mem byte" z13 zarch
-e70000001038 vesrlh VRS_VVRD "vector element shift right logical mem halfword" z13 zarch
-e70000002038 vesrlf VRS_VVRD "vector element shift right logical mem word" z13 zarch
-e70000003038 vesrlg VRS_VVRD "vector element shift right logical mem doubleword" z13 zarch
-e70000000074 vsl VRR_VVV "vector shift left" z13 zarch
-e70000000075 vslb VRR_VVV "vector shift left by byte" z13 zarch
-e70000000077 vsldb VRI_VVV0U "vector shift left double by byte" z13 zarch
-e7000000007e vsra VRR_VVV "vector shift right arithmetic" z13 zarch
-e7000000007f vsrab VRR_VVV "vector shift right arithmetic by byte" z13 zarch
-e7000000007c vsrl VRR_VVV "vector shift right logical" z13 zarch
-e7000000007d vsrlb VRR_VVV "vector shift right logical by byte" z13 zarch
-e700000000f7 vs VRR_VVV0U "vector subtract" z13 zarch
-e700000000f7 vsb VRR_VVV "vector subtract byte" z13 zarch
-e700000010f7 vsh VRR_VVV "vector subtract halfword" z13 zarch
-e700000020f7 vsf VRR_VVV "vector subtract word" z13 zarch
-e700000030f7 vsg VRR_VVV "vector subtract doubleword" z13 zarch
-e700000040f7 vsq VRR_VVV "vector subtract quadword" z13 zarch
-e700000000f5 vscbi VRR_VVV0U "vector subtract compute borrow indication" z13 zarch
-e700000000f5 vscbib VRR_VVV "vector subtract compute borrow indication byte" z13 zarch
-e700000010f5 vscbih VRR_VVV "vector subtract compute borrow indication halfword" z13 zarch
-e700000020f5 vscbif VRR_VVV "vector subtract compute borrow indication word" z13 zarch
-e700000030f5 vscbig VRR_VVV "vector subtract compute borrow indication doubleword" z13 zarch
-e700000040f5 vscbiq VRR_VVV "vector subtract compute borrow indication quadword" z13 zarch
-e700000000bf vsbi VRR_VVVU0V "vector subtract with borrow indication" z13 zarch
-e700040000bf vsbiq VRR_VVV0V "vector subtract with borrow indication quadword" z13 zarch
-e700000000bd vsbcbi VRR_VVVU0V "vector subtract with borrow compute borrow indication" z13 zarch
-e700040000bd vsbcbiq VRR_VVV0V "vector subtract with borrow compute borrow indication quadword" z13 zarch
-e70000000065 vsumg VRR_VVV0U "vector sum across doubleword" z13 zarch
-e70000001065 vsumgh VRR_VVV "vector sum across doubleword - halfword" z13 zarch
-e70000002065 vsumgf VRR_VVV "vector sum across doubleword - word" z13 zarch
-e70000000067 vsumq VRR_VVV0U "vector sum across quadword" z13 zarch
-e70000002067 vsumqf VRR_VVV "vector sum across quadword - word elements" z13 zarch
-e70000003067 vsumqg VRR_VVV "vector sum across quadword - doubleword elements" z13 zarch
-e70000000064 vsum VRR_VVV0U "vector sum across word" z13 zarch
-e70000000064 vsumb VRR_VVV "vector sum across word - byte elements" z13 zarch
-e70000001064 vsumh VRR_VVV "vector sum across word - halfword elements" z13 zarch
-e700000000d8 vtm VRR_VV "vector test under mask" z13 zarch
+e700000000f3 va VRR_VVV0U "vector add" z13 zarch vx
+e700000000f3 vab VRR_VVV "vector add byte" z13 zarch vx
+e700000010f3 vah VRR_VVV "vector add halfword" z13 zarch vx
+e700000020f3 vaf VRR_VVV "vector add word" z13 zarch vx
+e700000030f3 vag VRR_VVV "vector add double word" z13 zarch vx
+e700000040f3 vaq VRR_VVV "vector add quad word" z13 zarch vx
+e700000000f1 vacc VRR_VVV0U "vector add compute carry" z13 zarch vx
+e700000000f1 vaccb VRR_VVV "vector add compute carry byte" z13 zarch vx
+e700000010f1 vacch VRR_VVV "vector add compute carry halfword" z13 zarch vx
+e700000020f1 vaccf VRR_VVV "vector add compute carry word" z13 zarch vx
+e700000030f1 vaccg VRR_VVV "vector add compute carry doubleword" z13 zarch vx
+e700000040f1 vaccq VRR_VVV "vector add compute carry quadword" z13 zarch vx
+e700000000bb vac VRR_VVVU0V "vector add with carry" z13 zarch vx
+e700040000bb vacq VRR_VVV0V "vector add with carry quadword" z13 zarch vx
+e700000000b9 vaccc VRR_VVVU0V "vector add with carry compute carry" z13 zarch vx
+e700040000b9 vacccq VRR_VVV0V "vector add with carry compute carry quadword" z13 zarch vx
+e70000000068 vn VRR_VVV "vector and" z13 zarch vx
+e70000000069 vnc VRR_VVV "vector and with complement" z13 zarch vx
+e700000000f2 vavg VRR_VVV0U "vector average" z13 zarch vx
+e700000000f2 vavgb VRR_VVV "vector average byte" z13 zarch vx
+e700000010f2 vavgh VRR_VVV "vector average half word" z13 zarch vx
+e700000020f2 vavgf VRR_VVV "vector average word" z13 zarch vx
+e700000030f2 vavgg VRR_VVV "vector average double word" z13 zarch vx
+e700000000f0 vavgl VRR_VVV0U "vector average logical" z13 zarch vx
+e700000000f0 vavglb VRR_VVV "vector average logical byte" z13 zarch vx
+e700000010f0 vavglh VRR_VVV "vector average logical half word" z13 zarch vx
+e700000020f0 vavglf VRR_VVV "vector average logical word" z13 zarch vx
+e700000030f0 vavglg VRR_VVV "vector average logical double word" z13 zarch vx
+e70000000066 vcksm VRR_VVV "vector checksum" z13 zarch vx
+e700000000db vec VRR_VV0U "vector element compare" z13 zarch vx
+e700000000db vecb VRR_VV "vector element compare byte" z13 zarch vx
+e700000010db vech VRR_VV "vector element compare half word" z13 zarch vx
+e700000020db vecf VRR_VV "vector element compare word" z13 zarch vx
+e700000030db vecg VRR_VV "vector element compare double word" z13 zarch vx
+e700000000d9 vecl VRR_VV0U "vector element compare logical" z13 zarch vx
+e700000000d9 veclb VRR_VV "vector element compare logical byte" z13 zarch vx
+e700000010d9 veclh VRR_VV "vector element compare logical half word" z13 zarch vx
+e700000020d9 veclf VRR_VV "vector element compare logical word" z13 zarch vx
+e700000030d9 veclg VRR_VV "vector element compare logical double word" z13 zarch vx
+e700000000f8 vceq VRR_VVV0U0U "vector compare equal" z13 zarch vx
+e700000000f8 vceqb VRR_VVV "vector compare equal byte" z13 zarch vx
+e700000010f8 vceqh VRR_VVV "vector compare equal half word" z13 zarch vx
+e700000020f8 vceqf VRR_VVV "vector compare equal word" z13 zarch vx
+e700000030f8 vceqg VRR_VVV "vector compare equal double word" z13 zarch vx
+e700001000f8 vceqbs VRR_VVV "vector compare equal byte" z13 zarch vx
+e700001010f8 vceqhs VRR_VVV "vector compare equal half word" z13 zarch vx
+e700001020f8 vceqfs VRR_VVV "vector compare equal word" z13 zarch vx
+e700001030f8 vceqgs VRR_VVV "vector compare equal double word" z13 zarch vx
+e700000000fb vch VRR_VVV0U0U "vector compare high" z13 zarch vx
+e700000000fb vchb VRR_VVV "vector compare high byte" z13 zarch vx
+e700000010fb vchh VRR_VVV "vector compare high half word" z13 zarch vx
+e700000020fb vchf VRR_VVV "vector compare high word" z13 zarch vx
+e700000030fb vchg VRR_VVV "vector compare high double word" z13 zarch vx
+e700001000fb vchbs VRR_VVV "vector compare high byte" z13 zarch vx
+e700001010fb vchhs VRR_VVV "vector compare high half word" z13 zarch vx
+e700001020fb vchfs VRR_VVV "vector compare high word" z13 zarch vx
+e700001030fb vchgs VRR_VVV "vector compare high double word" z13 zarch vx
+e700000000f9 vchl VRR_VVV0U0U "vector compare high logical" z13 zarch vx
+e700000000f9 vchlb VRR_VVV "vector compare high logical byte" z13 zarch vx
+e700000010f9 vchlh VRR_VVV "vector compare high logical half word" z13 zarch vx
+e700000020f9 vchlf VRR_VVV "vector compare high logical word" z13 zarch vx
+e700000030f9 vchlg VRR_VVV "vector compare high logical double word" z13 zarch vx
+e700001000f9 vchlbs VRR_VVV "vector compare high logical byte" z13 zarch vx
+e700001010f9 vchlhs VRR_VVV "vector compare high logical half word" z13 zarch vx
+e700001020f9 vchlfs VRR_VVV "vector compare high logical word" z13 zarch vx
+e700001030f9 vchlgs VRR_VVV "vector compare high logical double word" z13 zarch vx
+e70000000053 vclz VRR_VV0U "vector count leading zeros" z13 zarch vx
+e70000000053 vclzb VRR_VV "vector count leading zeros byte" z13 zarch vx
+e70000001053 vclzh VRR_VV "vector count leading zeros halfword" z13 zarch vx
+e70000002053 vclzf VRR_VV "vector count leading zeros word" z13 zarch vx
+e70000003053 vclzg VRR_VV "vector count leading zeros doubleword" z13 zarch vx
+e70000000052 vctz VRR_VV0U "vector count trailing zeros" z13 zarch vx
+e70000000052 vctzb VRR_VV "vector count trailing zeros byte" z13 zarch vx
+e70000001052 vctzh VRR_VV "vector count trailing zeros halfword" z13 zarch vx
+e70000002052 vctzf VRR_VV "vector count trailing zeros word" z13 zarch vx
+e70000003052 vctzg VRR_VV "vector count trailing zeros doubleword" z13 zarch vx
+e7000000006d vx VRR_VVV "vector exclusive or" z13 zarch vx
+e700000000b4 vgfm VRR_VVV0U "vector galois field multiply sum" z13 zarch vx
+e700000000b4 vgfmb VRR_VVV "vector galois field multiply sum byte" z13 zarch vx
+e700000010b4 vgfmh VRR_VVV "vector galois field multiply sum halfword" z13 zarch vx
+e700000020b4 vgfmf VRR_VVV "vector galois field multiply sum word" z13 zarch vx
+e700000030b4 vgfmg VRR_VVV "vector galois field multiply sum doubleword" z13 zarch vx
+e700000000bc vgfma VRR_VVVU0V "vector galois field multiply sum and accumulate" z13 zarch vx
+e700000000bc vgfmab VRR_VVV0V "vector galois field multiply sum and accumulate byte" z13 zarch vx
+e700010000bc vgfmah VRR_VVV0V "vector galois field multiply sum and accumulate halfword" z13 zarch vx
+e700020000bc vgfmaf VRR_VVV0V "vector galois field multiply sum and accumulate word" z13 zarch vx
+e700030000bc vgfmag VRR_VVV0V "vector galois field multiply sum and accumulate doubleword" z13 zarch vx
+e700000000de vlc VRR_VV0U "vector load complement" z13 zarch vx
+e700000000de vlcb VRR_VV "vector load complement byte" z13 zarch vx
+e700000010de vlch VRR_VV "vector load complement halfword" z13 zarch vx
+e700000020de vlcf VRR_VV "vector load complement word" z13 zarch vx
+e700000030de vlcg VRR_VV "vector load complement doubleword" z13 zarch vx
+e700000000df vlp VRR_VV0U "vector load positive" z13 zarch vx
+e700000000df vlpb VRR_VV "vector load positive byte" z13 zarch vx
+e700000010df vlph VRR_VV "vector load positive halfword" z13 zarch vx
+e700000020df vlpf VRR_VV "vector load positive word" z13 zarch vx
+e700000030df vlpg VRR_VV "vector load positive doubleword" z13 zarch vx
+e700000000ff vmx VRR_VVV0U "vector maximum" z13 zarch vx
+e700000000ff vmxb VRR_VVV "vector maximum byte" z13 zarch vx
+e700000010ff vmxh VRR_VVV "vector maximum halfword" z13 zarch vx
+e700000020ff vmxf VRR_VVV "vector maximum word" z13 zarch vx
+e700000030ff vmxg VRR_VVV "vector maximum doubleword" z13 zarch vx
+e700000000fd vmxl VRR_VVV0U "vector maximum logical" z13 zarch vx
+e700000000fd vmxlb VRR_VVV "vector maximum logical byte" z13 zarch vx
+e700000010fd vmxlh VRR_VVV "vector maximum logical halfword" z13 zarch vx
+e700000020fd vmxlf VRR_VVV "vector maximum logical word" z13 zarch vx
+e700000030fd vmxlg VRR_VVV "vector maximum logical doubleword" z13 zarch vx
+e700000000fe vmn VRR_VVV0U "vector minimum" z13 zarch vx
+e700000000fe vmnb VRR_VVV "vector minimum byte" z13 zarch vx
+e700000010fe vmnh VRR_VVV "vector minimum halfword" z13 zarch vx
+e700000020fe vmnf VRR_VVV "vector minimum word" z13 zarch vx
+e700000030fe vmng VRR_VVV "vector minimum doubleword" z13 zarch vx
+e700000000fc vmnl VRR_VVV0U "vector minimum logical" z13 zarch vx
+e700000000fc vmnlb VRR_VVV "vector minimum logical byte" z13 zarch vx
+e700000010fc vmnlh VRR_VVV "vector minimum logical halfword" z13 zarch vx
+e700000020fc vmnlf VRR_VVV "vector minimum logical word" z13 zarch vx
+e700000030fc vmnlg VRR_VVV "vector minimum logical doubleword" z13 zarch vx
+e700000000aa vmal VRR_VVVU0V "vector multiply and add low" z13 zarch vx
+e700000000aa vmalb VRR_VVV0V "vector multiply and add low byte" z13 zarch vx
+e700010000aa vmalhw VRR_VVV0V "vector multiply and add low halfword" z13 zarch vx
+e700020000aa vmalf VRR_VVV0V "vector multiply and add low word" z13 zarch vx
+e700000000ab vmah VRR_VVVU0V "vector multiply and add high" z13 zarch vx
+e700000000ab vmahb VRR_VVV0V "vector multiply and add high byte" z13 zarch vx
+e700010000ab vmahh VRR_VVV0V "vector multiply and add high halfword" z13 zarch vx
+e700020000ab vmahf VRR_VVV0V "vector multiply and add high word" z13 zarch vx
+e700000000a9 vmalh VRR_VVVU0V "vector multiply and add logical high" z13 zarch vx
+e700000000a9 vmalhb VRR_VVV0V "vector multiply and add logical high byte" z13 zarch vx
+e700010000a9 vmalhh VRR_VVV0V "vector multiply and add logical high halfword" z13 zarch vx
+e700020000a9 vmalhf VRR_VVV0V "vector multiply and add logical high word" z13 zarch vx
+e700000000ae vmae VRR_VVVU0V "vector multiply and add even" z13 zarch vx
+e700000000ae vmaeb VRR_VVV0V "vector multiply and add even byte" z13 zarch vx
+e700010000ae vmaeh VRR_VVV0V "vector multiply and add even halfword" z13 zarch vx
+e700020000ae vmaef VRR_VVV0V "vector multiply and add even word" z13 zarch vx
+e700000000ac vmale VRR_VVVU0V "vector multiply and add logical even" z13 zarch vx
+e700000000ac vmaleb VRR_VVV0V "vector multiply and add logical even byte" z13 zarch vx
+e700010000ac vmaleh VRR_VVV0V "vector multiply and add logical even halfword" z13 zarch vx
+e700020000ac vmalef VRR_VVV0V "vector multiply and add logical even word" z13 zarch vx
+e700000000af vmao VRR_VVVU0V "vector multiply and add odd" z13 zarch vx
+e700000000af vmaob VRR_VVV0V "vector multiply and add odd byte" z13 zarch vx
+e700010000af vmaoh VRR_VVV0V "vector multiply and add odd halfword" z13 zarch vx
+e700020000af vmaof VRR_VVV0V "vector multiply and add odd word" z13 zarch vx
+e700000000ad vmalo VRR_VVVU0V "vector multiply and add logical odd" z13 zarch vx
+e700000000ad vmalob VRR_VVV0V "vector multiply and add logical odd byte" z13 zarch vx
+e700010000ad vmaloh VRR_VVV0V "vector multiply and add logical odd halfword" z13 zarch vx
+e700020000ad vmalof VRR_VVV0V "vector multiply and add logical odd word" z13 zarch vx
+e700000000a3 vmh VRR_VVV0U "vector multiply high" z13 zarch vx
+e700000000a3 vmhb VRR_VVV "vector multiply high byte" z13 zarch vx
+e700000010a3 vmhh VRR_VVV "vector multiply high halfword" z13 zarch vx
+e700000020a3 vmhf VRR_VVV "vector multiply high word" z13 zarch vx
+e700000000a1 vmlh VRR_VVV0U "vector multiply logical high" z13 zarch vx
+e700000000a1 vmlhb VRR_VVV "vector multiply logical high byte" z13 zarch vx
+e700000010a1 vmlhh VRR_VVV "vector multiply logical high halfword" z13 zarch vx
+e700000020a1 vmlhf VRR_VVV "vector multiply logical high word" z13 zarch vx
+e700000000a2 vml VRR_VVV0U "vector multiply low" z13 zarch vx
+e700000000a2 vmlb VRR_VVV "vector multiply low byte" z13 zarch vx
+e700000010a2 vmlhw VRR_VVV "vector multiply low halfword" z13 zarch vx
+e700000020a2 vmlf VRR_VVV "vector multiply low word" z13 zarch vx
+e700000000a6 vme VRR_VVV0U "vector multiply even" z13 zarch vx
+e700000000a6 vmeb VRR_VVV "vector multiply even byte" z13 zarch vx
+e700000010a6 vmeh VRR_VVV "vector multiply even halfword" z13 zarch vx
+e700000020a6 vmef VRR_VVV "vector multiply even word" z13 zarch vx
+e700000000a4 vmle VRR_VVV0U "vector multiply logical even" z13 zarch vx
+e700000000a4 vmleb VRR_VVV "vector multiply logical even byte" z13 zarch vx
+e700000010a4 vmleh VRR_VVV "vector multiply logical even halfword" z13 zarch vx
+e700000020a4 vmlef VRR_VVV "vector multiply logical even word" z13 zarch vx
+e700000000a7 vmo VRR_VVV0U "vector multiply odd" z13 zarch vx
+e700000000a7 vmob VRR_VVV "vector multiply odd byte" z13 zarch vx
+e700000010a7 vmoh VRR_VVV "vector multiply odd halfword" z13 zarch vx
+e700000020a7 vmof VRR_VVV "vector multiply odd word" z13 zarch vx
+e700000000a5 vmlo VRR_VVV0U "vector multiply logical odd" z13 zarch vx
+e700000000a5 vmlob VRR_VVV "vector multiply logical odd byte" z13 zarch vx
+e700000010a5 vmloh VRR_VVV "vector multiply logical odd halfword" z13 zarch vx
+e700000020a5 vmlof VRR_VVV "vector multiply logical odd word" z13 zarch vx
+e7000000006b vno VRR_VVV "vector nor" z13 zarch vx
+e7000000006b vnot VRR_VVV2 "vector not" z13 zarch vx
+e7000000006a vo VRR_VVV "vector or" z13 zarch vx
+e70000000050 vpopct VRR_VV0U "vector population count" z13 zarch vx
+e70000000073 verllv VRR_VVV0U "vector element rotate left logical reg" z13 zarch vx
+e70000000073 verllvb VRR_VVV "vector element rotate left logical reg byte" z13 zarch vx
+e70000001073 verllvh VRR_VVV "vector element rotate left logical reg halfword" z13 zarch vx
+e70000002073 verllvf VRR_VVV "vector element rotate left logical reg word" z13 zarch vx
+e70000003073 verllvg VRR_VVV "vector element rotate left logical reg doubleword" z13 zarch vx
+e70000000033 verll VRS_VVRDU "vector element rotate left logical mem" z13 zarch vx
+e70000000033 verllb VRS_VVRD "vector element rotate left logical mem byte" z13 zarch vx
+e70000001033 verllh VRS_VVRD "vector element rotate left logical mem halfword" z13 zarch vx
+e70000002033 verllf VRS_VVRD "vector element rotate left logical mem word" z13 zarch vx
+e70000003033 verllg VRS_VVRD "vector element rotate left logical mem doubleword" z13 zarch vx
+e70000000072 verim VRI_VVV0UU "vector element rotate and insert under mask" z13 zarch vx
+e70000000072 verimb VRI_VVV0U "vector element rotate and insert under mask byte" z13 zarch vx
+e70000001072 verimh VRI_VVV0U "vector element rotate and insert under mask halfword" z13 zarch vx
+e70000002072 verimf VRI_VVV0U "vector element rotate and insert under mask word" z13 zarch vx
+e70000003072 verimg VRI_VVV0U "vector element rotate and insert under mask doubleword" z13 zarch vx
+e70000000070 veslv VRR_VVV0U "vector element shift left reg" z13 zarch vx
+e70000000070 veslvb VRR_VVV "vector element shift left reg byte" z13 zarch vx
+e70000001070 veslvh VRR_VVV "vector element shift left reg halfword" z13 zarch vx
+e70000002070 veslvf VRR_VVV "vector element shift left reg word" z13 zarch vx
+e70000003070 veslvg VRR_VVV "vector element shift left reg doubleword" z13 zarch vx
+e70000000030 vesl VRS_VVRDU "vector element shift left mem" z13 zarch vx
+e70000000030 veslb VRS_VVRD "vector element shift left mem byte" z13 zarch vx
+e70000001030 veslh VRS_VVRD "vector element shift left mem halfword" z13 zarch vx
+e70000002030 veslf VRS_VVRD "vector element shift left mem word" z13 zarch vx
+e70000003030 veslg VRS_VVRD "vector element shift left mem doubleword" z13 zarch vx
+e7000000007a vesrav VRR_VVV0U "vector element shift right arithmetic reg" z13 zarch vx
+e7000000007a vesravb VRR_VVV "vector element shift right arithmetic reg byte" z13 zarch vx
+e7000000107a vesravh VRR_VVV "vector element shift right arithmetic reg halfword" z13 zarch vx
+e7000000207a vesravf VRR_VVV "vector element shift right arithmetic reg word" z13 zarch vx
+e7000000307a vesravg VRR_VVV "vector element shift right arithmetic reg doubleword" z13 zarch vx
+e7000000003a vesra VRS_VVRDU "vector element shift right arithmetic mem" z13 zarch vx
+e7000000003a vesrab VRS_VVRD "vector element shift right arithmetic mem byte" z13 zarch vx
+e7000000103a vesrah VRS_VVRD "vector element shift right arithmetic mem halfword" z13 zarch vx
+e7000000203a vesraf VRS_VVRD "vector element shift right arithmetic mem word" z13 zarch vx
+e7000000303a vesrag VRS_VVRD "vector element shift right arithmetic mem doubleword" z13 zarch vx
+e70000000078 vesrlv VRR_VVV0U "vector element shift right logical reg" z13 zarch vx
+e70000000078 vesrlvb VRR_VVV "vector element shift right logical reg byte" z13 zarch vx
+e70000001078 vesrlvh VRR_VVV "vector element shift right logical reg halfword" z13 zarch vx
+e70000002078 vesrlvf VRR_VVV "vector element shift right logical reg word" z13 zarch vx
+e70000003078 vesrlvg VRR_VVV "vector element shift right logical reg doubleword" z13 zarch vx
+e70000000038 vesrl VRS_VVRDU "vector element shift right logical mem" z13 zarch vx
+e70000000038 vesrlb VRS_VVRD "vector element shift right logical mem byte" z13 zarch vx
+e70000001038 vesrlh VRS_VVRD "vector element shift right logical mem halfword" z13 zarch vx
+e70000002038 vesrlf VRS_VVRD "vector element shift right logical mem word" z13 zarch vx
+e70000003038 vesrlg VRS_VVRD "vector element shift right logical mem doubleword" z13 zarch vx
+e70000000074 vsl VRR_VVV "vector shift left" z13 zarch vx
+e70000000075 vslb VRR_VVV "vector shift left by byte" z13 zarch vx
+e70000000077 vsldb VRI_VVV0U "vector shift left double by byte" z13 zarch vx
+e7000000007e vsra VRR_VVV "vector shift right arithmetic" z13 zarch vx
+e7000000007f vsrab VRR_VVV "vector shift right arithmetic by byte" z13 zarch vx
+e7000000007c vsrl VRR_VVV "vector shift right logical" z13 zarch vx
+e7000000007d vsrlb VRR_VVV "vector shift right logical by byte" z13 zarch vx
+e700000000f7 vs VRR_VVV0U "vector subtract" z13 zarch vx
+e700000000f7 vsb VRR_VVV "vector subtract byte" z13 zarch vx
+e700000010f7 vsh VRR_VVV "vector subtract halfword" z13 zarch vx
+e700000020f7 vsf VRR_VVV "vector subtract word" z13 zarch vx
+e700000030f7 vsg VRR_VVV "vector subtract doubleword" z13 zarch vx
+e700000040f7 vsq VRR_VVV "vector subtract quadword" z13 zarch vx
+e700000000f5 vscbi VRR_VVV0U "vector subtract compute borrow indication" z13 zarch vx
+e700000000f5 vscbib VRR_VVV "vector subtract compute borrow indication byte" z13 zarch vx
+e700000010f5 vscbih VRR_VVV "vector subtract compute borrow indication halfword" z13 zarch vx
+e700000020f5 vscbif VRR_VVV "vector subtract compute borrow indication word" z13 zarch vx
+e700000030f5 vscbig VRR_VVV "vector subtract compute borrow indication doubleword" z13 zarch vx
+e700000040f5 vscbiq VRR_VVV "vector subtract compute borrow indication quadword" z13 zarch vx
+e700000000bf vsbi VRR_VVVU0V "vector subtract with borrow indication" z13 zarch vx
+e700040000bf vsbiq VRR_VVV0V "vector subtract with borrow indication quadword" z13 zarch vx
+e700000000bd vsbcbi VRR_VVVU0V "vector subtract with borrow compute borrow indication" z13 zarch vx
+e700040000bd vsbcbiq VRR_VVV0V "vector subtract with borrow compute borrow indication quadword" z13 zarch vx
+e70000000065 vsumg VRR_VVV0U "vector sum across doubleword" z13 zarch vx
+e70000001065 vsumgh VRR_VVV "vector sum across doubleword - halfword" z13 zarch vx
+e70000002065 vsumgf VRR_VVV "vector sum across doubleword - word" z13 zarch vx
+e70000000067 vsumq VRR_VVV0U "vector sum across quadword" z13 zarch vx
+e70000002067 vsumqf VRR_VVV "vector sum across quadword - word elements" z13 zarch vx
+e70000003067 vsumqg VRR_VVV "vector sum across quadword - doubleword elements" z13 zarch vx
+e70000000064 vsum VRR_VVV0U "vector sum across word" z13 zarch vx
+e70000000064 vsumb VRR_VVV "vector sum across word - byte elements" z13 zarch vx
+e70000001064 vsumh VRR_VVV "vector sum across word - halfword elements" z13 zarch vx
+e700000000d8 vtm VRR_VV "vector test under mask" z13 zarch vx