-#define arch_sh1_base 0x0001
-#define arch_sh2_base 0x0002
-#define arch_sh3_base 0x0004
-#define arch_sh4_base 0x0008
-#define arch_sh4a_base 0x0010
-#define arch_sh2a_base 0x0020
-
-/* This is an annotation on instruction types, but we abuse the arch
- field in instructions to denote it. */
-#define arch_op32 0x00100000 /* This is a 32-bit opcode. */
-
-#define arch_sh_no_mmu 0x04000000
-#define arch_sh_has_mmu 0x08000000
-#define arch_sh_no_co 0x10000000 /* neither FPU nor DSP co-processor */
-#define arch_sh_sp_fpu 0x20000000 /* single precision FPU */
-#define arch_sh_dp_fpu 0x40000000 /* double precision FPU */
-#define arch_sh_has_dsp 0x80000000
-
-
-#define arch_sh_base_mask 0x0000003f
-#define arch_opann_mask 0x00100000
-#define arch_sh_mmu_mask 0x0c000000
-#define arch_sh_co_mask 0xf0000000
-
-
-#define arch_sh1 (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)
-#define arch_sh2 (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)
-#define arch_sh2a (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
-#define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
-#define arch_sh2e (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
-#define arch_sh_dsp (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)
-#define arch_sh3_nommu (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)
-#define arch_sh3 (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)
-#define arch_sh3e (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)
-#define arch_sh3_dsp (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)
-#define arch_sh4 (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)
-#define arch_sh4a (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
-#define arch_sh4al_dsp (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
-#define arch_sh4_nofpu (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)
-#define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
-#define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)
+/* Return a mask with bits LO to HI (inclusive) set. */
+#define MASK(LO,HI) ( LO < 1 ? ((1 << (HI + 1)) - 1) \
+ : HI > 30 ? (-1 << LO) \
+ : LO == HI ? (1 << LO) \
+ : (((1 << (HI + 1)) - 1) & (-1 << LO)))
+
+#define arch_sh1_base (1 << 0)
+#define arch_sh2_base (1 << 1)
+#define arch_sh2a_sh3_base (1 << 2)
+#define arch_sh3_base (1 << 3)
+#define arch_sh2a_sh4_base (1 << 4)
+#define arch_sh4_base (1 << 5)
+#define arch_sh4a_base (1 << 6)
+#define arch_sh2a_base (1 << 7)
+#define arch_sh_base_mask MASK (0, 7)
+
+/* Bits 8 ... 24 are currently free. */
+
+/* This is an annotation on instruction types, but we
+ abuse the arch field in instructions to denote it. */
+#define arch_op32 (1 << 25) /* This is a 32-bit opcode. */
+#define arch_opann_mask MASK (25, 25)
+
+#define arch_sh_no_mmu (1 << 26)
+#define arch_sh_has_mmu (1 << 27)
+#define arch_sh_mmu_mask MASK (26, 27)
+
+#define arch_sh_no_co (1 << 28) /* Neither FPU nor DSP co-processor. */
+#define arch_sh_sp_fpu (1 << 29) /* Single precision FPU. */
+#define arch_sh_dp_fpu (1 << 30) /* Double precision FPU. */
+#define arch_sh_has_dsp (1 << 31)
+#define arch_sh_co_mask MASK (28, 31)
+
+
+#define arch_sh1 (arch_sh1_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2 (arch_sh2_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a (arch_sh2a_base |arch_sh_no_mmu |arch_sh_dp_fpu)
+#define arch_sh2a_nofpu (arch_sh2a_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2e (arch_sh2_base |arch_sh_no_mmu |arch_sh_sp_fpu)
+#define arch_sh_dsp (arch_sh2_base |arch_sh_no_mmu |arch_sh_has_dsp)
+#define arch_sh3_nommu (arch_sh3_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh3 (arch_sh3_base |arch_sh_has_mmu|arch_sh_no_co)
+#define arch_sh3e (arch_sh3_base |arch_sh_has_mmu|arch_sh_sp_fpu)
+#define arch_sh3_dsp (arch_sh3_base |arch_sh_has_mmu|arch_sh_has_dsp)
+#define arch_sh4 (arch_sh4_base |arch_sh_has_mmu|arch_sh_dp_fpu)
+#define arch_sh4a (arch_sh4a_base |arch_sh_has_mmu|arch_sh_dp_fpu)
+#define arch_sh4al_dsp (arch_sh4a_base |arch_sh_has_mmu|arch_sh_has_dsp)
+#define arch_sh4_nofpu (arch_sh4_base |arch_sh_has_mmu|arch_sh_no_co)
+#define arch_sh4a_nofpu (arch_sh4a_base |arch_sh_has_mmu|arch_sh_no_co)
+#define arch_sh4_nommu_nofpu (arch_sh4_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a_nofpu_or_sh4_nommu_nofpu (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
+#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)