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* arc-opc.c: Include bfd.h.
[deliverable/binutils-gdb.git]
/
opcodes
/
sparc-dis.c
diff --git
a/opcodes/sparc-dis.c
b/opcodes/sparc-dis.c
index 9fbdb60c8c22e5cba493bc775521e93305bc05ad..47ebb313744842a62aaf005a2c6dc5d88013ef0f 100644
(file)
--- a/
opcodes/sparc-dis.c
+++ b/
opcodes/sparc-dis.c
@@
-1,5
+1,6
@@
/* Print SPARC instructions.
/* Print SPARC instructions.
- Copyright (C) 1989, 91-97, 1998 Free Software Foundation, Inc.
+ Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+ 2000, 2002 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@
-17,7
+18,6
@@
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include <stdio.h>
-#include "ansidecl.h"
#include "sysdep.h"
#include "opcode/sparc.h"
#include "dis-asm.h"
#include "sysdep.h"
#include "opcode/sparc.h"
#include "dis-asm.h"
@@
-26,7
+26,8
@@
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* Bitmask of v9 architectures. */
#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
/* Bitmask of v9 architectures. */
#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
- | (1 << SPARC_OPCODE_ARCH_V9A))
+ | (1 << SPARC_OPCODE_ARCH_V9A) \
+ | (1 << SPARC_OPCODE_ARCH_V9B))
/* 1 if INSN is for v9 only. */
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
/* 1 if INSN is for v9. */
/* 1 if INSN is for v9 only. */
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
/* 1 if INSN is for v9. */
@@
-96,7
+97,7
@@
static char *v9_priv_reg_names[] =
static char *v9a_asr_reg_names[] =
{
"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
static char *v9a_asr_reg_names[] =
{
"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
- "softint", "tick_cmpr"
+ "softint", "tick_cmpr"
, "sys_tick", "sys_tick_cmpr"
};
/* Macros used to extract instruction fields. Not all fields have
};
/* Macros used to extract instruction fields. Not all fields have
@@
-187,7
+188,7
@@
is_delayed_branch (insn)
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
-
CONST
struct sparc_opcode *opcode = op->opcode;
+
const
struct sparc_opcode *opcode = op->opcode;
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
return (opcode->flags & F_DELAYED);
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
return (opcode->flags & F_DELAYED);
@@
-271,7
+272,7
@@
print_insn_sparc (memaddr, info)
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
-
CONST
struct sparc_opcode *opcode = op->opcode;
+
const
struct sparc_opcode *opcode = op->opcode;
/* If the insn isn't supported by the current architecture, skip it. */
if (! (opcode->architecture & current_arch_mask))
/* If the insn isn't supported by the current architecture, skip it. */
if (! (opcode->architecture & current_arch_mask))
@@
-311,7
+312,7
@@
print_insn_sparc (memaddr, info)
(*info->fprintf_func) (stream, opcode->name);
{
(*info->fprintf_func) (stream, opcode->name);
{
- register
CONST
char *s;
+ register
const
char *s;
if (opcode->args[0] != ',')
(*info->fprintf_func) (stream, " ");
if (opcode->args[0] != ',')
(*info->fprintf_func) (stream, " ");
@@
-418,7
+419,7
@@
print_insn_sparc (memaddr, info)
case 'h':
(*info->fprintf_func) (stream, "%%hi(%#x)",
case 'h':
(*info->fprintf_func) (stream, "%%hi(%#x)",
- (0xFFFFFFFF
+ (
(unsigned)
0xFFFFFFFF
& ((int) X_IMM22 (insn) << 10)));
break;
& ((int) X_IMM22 (insn) << 10)));
break;
@@
-464,6
+465,10
@@
print_insn_sparc (memaddr, info)
}
break;
}
break;
+ case '3':
+ (info->fprintf_func) (stream, "%d", X_IMM (insn, 3));
+ break;
+
case 'K':
{
int mask = X_MEMBAR (insn);
case 'K':
{
int mask = X_MEMBAR (insn);
@@
-552,7
+557,7
@@
print_insn_sparc (memaddr, info)
break;
case '/':
break;
case '/':
- if (X_RS1 (insn) < 16 || X_RS1 (insn) > 2
3
)
+ if (X_RS1 (insn) < 16 || X_RS1 (insn) > 2
5
)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
@@
-560,7
+565,7
@@
print_insn_sparc (memaddr, info)
break;
case '_':
break;
case '_':
- if (X_RD (insn) < 16 || X_RD (insn) > 2
3
)
+ if (X_RD (insn) < 16 || X_RD (insn) > 2
5
)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
@@
-711,7
+716,8
@@
print_insn_sparc (memaddr, info)
{
(*info->fprintf_func) (stream, "\t! ");
info->target =
{
(*info->fprintf_func) (stream, "\t! ");
info->target =
- (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10);
+ ((unsigned) 0xFFFFFFFF
+ & ((int) X_IMM22 (prev_insn) << 10));
if (imm_added_to_rs1)
info->target += X_SIMM (insn, 13);
else
if (imm_added_to_rs1)
info->target += X_SIMM (insn, 13);
else
@@
-771,6
+777,9
@@
compute_arch_mask (mach)
case bfd_mach_sparc_v8plusa :
case bfd_mach_sparc_v9a :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
case bfd_mach_sparc_v8plusa :
case bfd_mach_sparc_v9a :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
+ case bfd_mach_sparc_v8plusb :
+ case bfd_mach_sparc_v9b :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
}
abort ();
}
}
abort ();
}
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