- Copyright 1999, 2000, 2001, 2005, 2007, 2009 Free Software Foundation, Inc.
+ Copyright (C) 1999-2016 Free Software Foundation, Inc.
{ "AR0", 16 }, { "ar0", 16 },
{ "AR1", 17 }, { "ar1", 17 },
{ "AR2", 18 }, { "ar2", 18 },
{ "AR0", 16 }, { "ar0", 16 },
{ "AR1", 17 }, { "ar1", 17 },
{ "AR2", 18 }, { "ar2", 18 },
/* status bits, MM registers, condition codes, etc */
/* some symbols are only valid for certain chips... */
/* status bits, MM registers, condition codes, etc */
/* some symbols are only valid for certain chips... */
{ "IMR", 0 }, { "imr", 0 },
{ "IFR", 1 }, { "ifr", 1 },
{ "ST0", 6 }, { "st0", 6 },
{ "IMR", 0 }, { "imr", 0 },
{ "IFR", 1 }, { "ifr", 1 },
{ "ST0", 6 }, { "st0", 6 },
/* condition codes */
{ "UNC", 0 }, { "unc", 0 },
#define CC1 0x40
/* condition codes */
{ "UNC", 0 }, { "unc", 0 },
#define CC1 0x40
{ "UNC", 0 }, { "unc", 0 },
{ "AEQ", 5 }, { "aeq", 5 },
{ "ANEQ", 4 }, { "aneq", 4 },
{ "UNC", 0 }, { "unc", 0 },
{ "AEQ", 5 }, { "aeq", 5 },
{ "ANEQ", 4 }, { "aneq", 4 },
{ "EQ", 0x0000 }, { "eq", 0x0000 },
{ "LT", 0x0100 }, { "lt", 0x0100 },
{ "GT", 0x0200 }, { "gt", 0x0200 },
{ "EQ", 0x0000 }, { "eq", 0x0000 },
{ "LT", 0x0100 }, { "lt", 0x0100 },
{ "GT", 0x0200 }, { "gt", 0x0200 },
/* status register 0 */
{ "TC", 12 }, { "tc", 12 },
{ "C", 11 }, { "c", 11 },
/* status register 0 */
{ "TC", 12 }, { "tc", 12 },
{ "C", 11 }, { "c", 11 },