* aclocal.m4, configure: Rebuilt.

[deliverable/binutils-gdb.git] / opcodes / tic80-opc.c

diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c
index 2a534126da818293be8380f03d7c34143032eeef..061b63761c4d13ac6c5d9349d98342f94c93ea87 100644 (file)
--- a/opcodes/tic80-opc.c
+++ b/opcodes/tic80-opc.c
@@ -79,10 +79,10 @@ const struct predefined_symbol tic80_predefined_symbols[] =
   { "ECOMCNTL",        TIC80_OPERAND_CR | 0x33 },
   { "EIP",     TIC80_OPERAND_CR | 1 },
   { "EPC",     TIC80_OPERAND_CR | 0 },
   { "ECOMCNTL",        TIC80_OPERAND_CR | 0x33 },
   { "EIP",     TIC80_OPERAND_CR | 1 },
   { "EPC",     TIC80_OPERAND_CR | 0 },

-  { "eq.b",    TIC80_OPERAND_BITNUM  | (~0 & 0x1F) },
-  { "eq.f",    TIC80_OPERAND_BITNUM  | (~20 & 0x1F) },
-  { "eq.h",    TIC80_OPERAND_BITNUM  | (~10 & 0x1F) },
-  { "eq.w",    TIC80_OPERAND_BITNUM  | (~20 & 0x1F) },
+  { "eq.b",    TIC80_OPERAND_BITNUM  | 0 },
+  { "eq.f",    TIC80_OPERAND_BITNUM  | 20 },
+  { "eq.h",    TIC80_OPERAND_BITNUM  | 10 },
+  { "eq.w",    TIC80_OPERAND_BITNUM  | 20 },

   { "eq0.b",   TIC80_OPERAND_CC | 2 },
   { "eq0.h",   TIC80_OPERAND_CC | 10 },
   { "eq0.w",   TIC80_OPERAND_CC | 18 },
   { "eq0.b",   TIC80_OPERAND_CC | 2 },
   { "eq0.h",   TIC80_OPERAND_CC | 10 },
   { "eq0.w",   TIC80_OPERAND_CC | 18 },


@@ -92,30 +92,30 @@ const struct predefined_symbol tic80_predefined_symbols[] =
   { "FLTOP",   TIC80_OPERAND_CR | 0x10 },
   { "FLTTAG",  TIC80_OPERAND_CR | 0x12 },
   { "FPST",    TIC80_OPERAND_CR | 8 },
   { "FLTOP",   TIC80_OPERAND_CR | 0x10 },
   { "FLTTAG",  TIC80_OPERAND_CR | 0x12 },
   { "FPST",    TIC80_OPERAND_CR | 8 },

-  { "ge.b",    TIC80_OPERAND_BITNUM  | (~5 & 0x1F) },
-  { "ge.f",    TIC80_OPERAND_BITNUM  | (~25 & 0x1F) },
-  { "ge.h",    TIC80_OPERAND_BITNUM  | (~15 & 0x1F) },
-  { "ge.w",    TIC80_OPERAND_BITNUM  | (~25 & 0x1F) },
+  { "ge.b",    TIC80_OPERAND_BITNUM  | 5 },
+  { "ge.f",    TIC80_OPERAND_BITNUM  | 25 },
+  { "ge.h",    TIC80_OPERAND_BITNUM  | 15 },
+  { "ge.w",    TIC80_OPERAND_BITNUM  | 25 },

   { "ge0.b",   TIC80_OPERAND_CC | 3 },
   { "ge0.h",   TIC80_OPERAND_CC | 11 },
   { "ge0.w",   TIC80_OPERAND_CC | 19 },
   { "ge0.b",   TIC80_OPERAND_CC | 3 },
   { "ge0.h",   TIC80_OPERAND_CC | 11 },
   { "ge0.w",   TIC80_OPERAND_CC | 19 },

-  { "gt.b",    TIC80_OPERAND_BITNUM  | (~2 & 0x1F) },
-  { "gt.f",    TIC80_OPERAND_BITNUM  | (~22 & 0x1F) },
-  { "gt.h",    TIC80_OPERAND_BITNUM  | (~12 & 0x1F) },
-  { "gt.w",    TIC80_OPERAND_BITNUM  | (~22 & 0x1F) },
+  { "gt.b",    TIC80_OPERAND_BITNUM  | 2 },
+  { "gt.f",    TIC80_OPERAND_BITNUM  | 22 },
+  { "gt.h",    TIC80_OPERAND_BITNUM  | 12 },
+  { "gt.w",    TIC80_OPERAND_BITNUM  | 22 },

   { "gt0.b",   TIC80_OPERAND_CC | 1 },
   { "gt0.h",   TIC80_OPERAND_CC | 9 },
   { "gt0.w",   TIC80_OPERAND_CC | 17 },
   { "gt0.b",   TIC80_OPERAND_CC | 1 },
   { "gt0.h",   TIC80_OPERAND_CC | 9 },
   { "gt0.w",   TIC80_OPERAND_CC | 17 },

-  { "hi.b",    TIC80_OPERAND_BITNUM  | (~6 & 0x1F) },
-  { "hi.h",    TIC80_OPERAND_BITNUM  | (~16 & 0x1F) },
-  { "hi.w",    TIC80_OPERAND_BITNUM  | (~26 & 0x1F) },
-  { "hs.b",    TIC80_OPERAND_BITNUM  | (~9 & 0x1F) },
-  { "hs.h",    TIC80_OPERAND_BITNUM  | (~19 & 0x1F) },
-  { "hs.w",    TIC80_OPERAND_BITNUM  | (~29 & 0x1F) },
-  { "ib.f",    TIC80_OPERAND_BITNUM  | (~28 & 0x1F) },
+  { "hi.b",    TIC80_OPERAND_BITNUM  | 6 },
+  { "hi.h",    TIC80_OPERAND_BITNUM  | 16 },
+  { "hi.w",    TIC80_OPERAND_BITNUM  | 26 },
+  { "hs.b",    TIC80_OPERAND_BITNUM  | 9 },
+  { "hs.h",    TIC80_OPERAND_BITNUM  | 19 },
+  { "hs.w",    TIC80_OPERAND_BITNUM  | 29 },
+  { "ib.f",    TIC80_OPERAND_BITNUM  | 28 },

   { "IE",      TIC80_OPERAND_CR | 6 },
   { "ILRU",    TIC80_OPERAND_CR | 0x300 },
   { "IE",      TIC80_OPERAND_CR | 6 },
   { "ILRU",    TIC80_OPERAND_CR | 0x300 },

-  { "in.f",    TIC80_OPERAND_BITNUM  | (~27 & 0x1F) },
+  { "in.f",    TIC80_OPERAND_BITNUM  | 27 },

   { "IN0P",    TIC80_OPERAND_CR | 0x4000 },
   { "IN1P",    TIC80_OPERAND_CR | 0x4001 },
   { "INTPEN",  TIC80_OPERAND_CR | 4 },
   { "IN0P",    TIC80_OPERAND_CR | 0x4000 },
   { "IN1P",    TIC80_OPERAND_CR | 0x4001 },
   { "INTPEN",  TIC80_OPERAND_CR | 4 },


@@ -135,41 +135,41 @@ const struct predefined_symbol tic80_predefined_symbols[] =
   { "ITAG7",   TIC80_OPERAND_CR | 0x207 },
   { "ITAG8",   TIC80_OPERAND_CR | 0x208 },
   { "ITAG9",   TIC80_OPERAND_CR | 0x209 },
   { "ITAG7",   TIC80_OPERAND_CR | 0x207 },
   { "ITAG8",   TIC80_OPERAND_CR | 0x208 },
   { "ITAG9",   TIC80_OPERAND_CR | 0x209 },

-  { "le.b",    TIC80_OPERAND_BITNUM  | (~3 & 0x1F) },
-  { "le.f",    TIC80_OPERAND_BITNUM  | (~23 & 0x1F) },
-  { "le.h",    TIC80_OPERAND_BITNUM  | (~13 & 0x1F) },
-  { "le.w",    TIC80_OPERAND_BITNUM  | (~23 & 0x1F) },
+  { "le.b",    TIC80_OPERAND_BITNUM  | 3 },
+  { "le.f",    TIC80_OPERAND_BITNUM  | 23 },
+  { "le.h",    TIC80_OPERAND_BITNUM  | 13 },
+  { "le.w",    TIC80_OPERAND_BITNUM  | 23 },

   { "le0.b",   TIC80_OPERAND_CC | 6 },
   { "le0.h",   TIC80_OPERAND_CC | 14 },
   { "le0.w",   TIC80_OPERAND_CC | 22 },
   { "le0.b",   TIC80_OPERAND_CC | 6 },
   { "le0.h",   TIC80_OPERAND_CC | 14 },
   { "le0.w",   TIC80_OPERAND_CC | 22 },

-  { "lo.b",    TIC80_OPERAND_BITNUM  | (~8 & 0x1F) },
-  { "lo.h",    TIC80_OPERAND_BITNUM  | (~18 & 0x1F) },
-  { "lo.w",    TIC80_OPERAND_BITNUM  | (~28 & 0x1F) },
-  { "ls.b",    TIC80_OPERAND_BITNUM  | (~7 & 0x1F) },
-  { "ls.h",    TIC80_OPERAND_BITNUM  | (~17 & 0x1F) },
-  { "ls.w",    TIC80_OPERAND_BITNUM  | (~27 & 0x1F) },
-  { "lt.b",    TIC80_OPERAND_BITNUM  | (~4 & 0x1F) },
-  { "lt.f",    TIC80_OPERAND_BITNUM  | (~24 & 0x1F) },
-  { "lt.h",    TIC80_OPERAND_BITNUM  | (~14 & 0x1F) },
-  { "lt.w",    TIC80_OPERAND_BITNUM  | (~24 & 0x1F) },
+  { "lo.b",    TIC80_OPERAND_BITNUM  | 8 },
+  { "lo.h",    TIC80_OPERAND_BITNUM  | 18 },
+  { "lo.w",    TIC80_OPERAND_BITNUM  | 28 },
+  { "ls.b",    TIC80_OPERAND_BITNUM  | 7 },
+  { "ls.h",    TIC80_OPERAND_BITNUM  | 17 },
+  { "ls.w",    TIC80_OPERAND_BITNUM  | 27 },
+  { "lt.b",    TIC80_OPERAND_BITNUM  | 4 },
+  { "lt.f",    TIC80_OPERAND_BITNUM  | 24 },
+  { "lt.h",    TIC80_OPERAND_BITNUM  | 14 },
+  { "lt.w",    TIC80_OPERAND_BITNUM  | 24 },

   { "lt0.b",   TIC80_OPERAND_CC | 4 },
   { "lt0.h",   TIC80_OPERAND_CC | 12 },
   { "lt0.w",   TIC80_OPERAND_CC | 20 },
   { "MIP",     TIC80_OPERAND_CR | 0x31 },
   { "MPC",     TIC80_OPERAND_CR | 0x30 },
   { "lt0.b",   TIC80_OPERAND_CC | 4 },
   { "lt0.h",   TIC80_OPERAND_CC | 12 },
   { "lt0.w",   TIC80_OPERAND_CC | 20 },
   { "MIP",     TIC80_OPERAND_CR | 0x31 },
   { "MPC",     TIC80_OPERAND_CR | 0x30 },

-  { "ne.b",    TIC80_OPERAND_BITNUM  | (~1 & 0x1F) },
-  { "ne.f",    TIC80_OPERAND_BITNUM  | (~21 & 0x1F) },
-  { "ne.h",    TIC80_OPERAND_BITNUM  | (~11 & 0x1F) },
-  { "ne.w",    TIC80_OPERAND_BITNUM  | (~21 & 0x1F) },
+  { "ne.b",    TIC80_OPERAND_BITNUM  | 1 },
+  { "ne.f",    TIC80_OPERAND_BITNUM  | 21 },
+  { "ne.h",    TIC80_OPERAND_BITNUM  | 11 },
+  { "ne.w",    TIC80_OPERAND_BITNUM  | 21 },

   { "ne0.b",   TIC80_OPERAND_CC | 5 },
   { "ne0.h",   TIC80_OPERAND_CC | 13 },
   { "ne0.w",   TIC80_OPERAND_CC | 21 },
   { "nev.b",   TIC80_OPERAND_CC | 0 },
   { "nev.h",   TIC80_OPERAND_CC | 8 },
   { "nev.w",   TIC80_OPERAND_CC | 16 },
   { "ne0.b",   TIC80_OPERAND_CC | 5 },
   { "ne0.h",   TIC80_OPERAND_CC | 13 },
   { "ne0.w",   TIC80_OPERAND_CC | 21 },
   { "nev.b",   TIC80_OPERAND_CC | 0 },
   { "nev.h",   TIC80_OPERAND_CC | 8 },
   { "nev.w",   TIC80_OPERAND_CC | 16 },

-  { "ob.f",    TIC80_OPERAND_BITNUM  | (~29 & 0x1F) },
-  { "or.f",    TIC80_OPERAND_BITNUM  | (~31 & 0x1F) },
-  { "ou.f",    TIC80_OPERAND_BITNUM  | (~26 & 0x1F) },
+  { "ob.f",    TIC80_OPERAND_BITNUM  | 29 },
+  { "or.f",    TIC80_OPERAND_BITNUM  | 31 },
+  { "ou.f",    TIC80_OPERAND_BITNUM  | 26 },

   { "OUTP",    TIC80_OPERAND_CR | 0x4002 },
   { "PKTREQ",  TIC80_OPERAND_CR | 0xD },
   { "PPERROR", TIC80_OPERAND_CR | 0xA },
   { "OUTP",    TIC80_OPERAND_CR | 0x4002 },
   { "PKTREQ",  TIC80_OPERAND_CR | 0xD },
   { "PPERROR", TIC80_OPERAND_CR | 0xA },


@@ -191,7 +191,7 @@ const struct predefined_symbol tic80_predefined_symbols[] =
   { "r22",     TIC80_OPERAND_GPR | 22 },
   { "r23",     TIC80_OPERAND_GPR | 23 },
   { "r24",     TIC80_OPERAND_GPR | 24 },
   { "r22",     TIC80_OPERAND_GPR | 22 },
   { "r23",     TIC80_OPERAND_GPR | 23 },
   { "r24",     TIC80_OPERAND_GPR | 24 },

-  { "r24",     TIC80_OPERAND_GPR | 24 },
+  { "r25",     TIC80_OPERAND_GPR | 25 },

   { "r26",     TIC80_OPERAND_GPR | 26 },
   { "r27",     TIC80_OPERAND_GPR | 27 },
   { "r28",     TIC80_OPERAND_GPR | 28 },
   { "r26",     TIC80_OPERAND_GPR | 26 },
   { "r27",     TIC80_OPERAND_GPR | 27 },
   { "r28",     TIC80_OPERAND_GPR | 28 },


@@ -209,7 +209,7 @@ const struct predefined_symbol tic80_predefined_symbols[] =
   { "SYSTMP",  TIC80_OPERAND_CR | 0x21 },
   { "TCOUNT",  TIC80_OPERAND_CR | 0xE },
   { "TSCALE",  TIC80_OPERAND_CR | 0xF },
   { "SYSTMP",  TIC80_OPERAND_CR | 0x21 },
   { "TCOUNT",  TIC80_OPERAND_CR | 0xE },
   { "TSCALE",  TIC80_OPERAND_CR | 0xF },

-  { "uo.f",    TIC80_OPERAND_BITNUM  | (~30 & 0x1F) },
+  { "uo.f",    TIC80_OPERAND_BITNUM  | 30 },

 };
 
 const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol);
 };
 
 const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol);


@@ -429,7 +429,7 @@ const struct tic80_operand tic80_operands[] =
   /* Long signed PC word offset in following 32 bit word */
 
 #define OFF_SL_PC (OFF_SS_PC + 1)
   /* Long signed PC word offset in following 32 bit word */
 
 #define OFF_SL_PC (OFF_SS_PC + 1)

-  {32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
+  { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },

 
   /* Short signed base relative byte offset in bits 14-0 */
 
 
   /* Short signed base relative byte offset in bits 14-0 */
 


@@ -439,11 +439,17 @@ const struct tic80_operand tic80_operands[] =
   /* Long signed base relative byte offset in following 32 bit word */
 
 #define OFF_SL_BR (OFF_SS_BR + 1)
   /* Long signed base relative byte offset in following 32 bit word */
 
 #define OFF_SL_BR (OFF_SS_BR + 1)

-  {32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
+  { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
+
+  /* Long signed base relative byte offset in following 32 bit word
+     with optional ":s" modifier flag in bit 11 */
+
+#define OFF_SL_BR_SCALED (OFF_SL_BR + 1)
+  { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },

 
   /* BITNUM in bits 31-27 */
 
 
   /* BITNUM in bits 31-27 */
 

-#define BITNUM (OFF_SL_BR + 1)
+#define BITNUM (OFF_SL_BR_SCALED + 1)

   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
 
   /* Condition code in bits 31-27 */
   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
 
   /* Condition code in bits 31-27 */


@@ -483,15 +489,9 @@ const struct tic80_operand tic80_operands[] =
 #define REG_SCALED (REG_BASE_M_LI + 1)
   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
 
 #define REG_SCALED (REG_BASE_M_LI + 1)
   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
 

-  /* Long signed immediate in following 32 bit word, with optional ":s" modifier
-     flag in bit 11 */
-
-#define LSI_SCALED (REG_SCALED + 1)
-  { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
-

   /* Unsigned immediate in bits 4-0, used only for shift instructions */
 
   /* Unsigned immediate in bits 4-0, used only for shift instructions */
 

-#define ROTATE (LSI_SCALED + 1)
+#define ROTATE (REG_SCALED + 1)

   { 5, 0, NULL, NULL, 0 },
 
   /* Unsigned immediate in bits 9-5, used only for shift instructions */
   { 5, 0, NULL, NULL, 0 },
 
   /* Unsigned immediate in bits 9-5, used only for shift instructions */


@@ -589,7 +589,9 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
  entries with the same mnemonic are sorted so that they are adjacent in the table,
  allowing the use of a hash table to locate the first of a sequence of opcodes that have
  a particular name.  The short immediate forms also come before the long immediate forms
  entries with the same mnemonic are sorted so that they are adjacent in the table,
  allowing the use of a hash table to locate the first of a sequence of opcodes that have
  a particular name.  The short immediate forms also come before the long immediate forms

- so that the assembler will pick the "best fit" for the size of the operand. */
+ so that the assembler will pick the "best fit" for the size of the operand, except for
+ the case of the PC relative forms, where the long forms come first and are the default
+ forms. */

 
 const struct tic80_opcode tic80_opcodes[] = {
 
 
 const struct tic80_opcode tic80_opcodes[] = {
 


@@ -602,11 +604,11 @@ const struct tic80_opcode tic80_opcodes[] = {
   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
      this specific bit pattern will get disassembled as a br rather than bbz. */
 
   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
      this specific bit pattern will get disassembled as a br rather than bbz. */
 

-  {"br",       OP_SI(0x48),    0xFFFF8000,     0,      {OFF_SS_PC}     },

   {"br",       OP_LI(0x391),   0xFFFFF000,     0,      {OFF_SL_PC}     },
   {"br",       OP_LI(0x391),   0xFFFFF000,     0,      {OFF_SL_PC}     },

+  {"br",       OP_SI(0x48),    0xFFFF8000,     0,      {OFF_SS_PC}     },

   {"br",       OP_REG(0x390),  0xFFFFF000,     0,      {REG_0}         },
   {"br",       OP_REG(0x390),  0xFFFFF000,     0,      {REG_0}         },

-  {"br.a",     OP_SI(0x49),    0xFFFF8000,     0,      {OFF_SS_PC}     },

   {"br.a",     OP_LI(0x393),   0xFFFFF000,     0,      {OFF_SL_PC}     },
   {"br.a",     OP_LI(0x393),   0xFFFFF000,     0,      {OFF_SL_PC}     },

+  {"br.a",     OP_SI(0x49),    0xFFFF8000,     0,      {OFF_SS_PC}     },

   {"br.a",     OP_REG(0x392),  0xFFFFF000,     0,      {REG_0}         },
 
   /* Signed integer ADD */
   {"br.a",     OP_REG(0x392),  0xFFFFF000,     0,      {REG_0}         },
 
   /* Signed integer ADD */


@@ -650,38 +652,38 @@ const struct tic80_opcode tic80_opcodes[] = {
 
   /* Branch Bit One - nonannulled */
 
 
   /* Branch Bit One - nonannulled */
 

-  {"bbo",      OP_SI(0x4A),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },

   {"bbo",      OP_LI(0x395),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbo",      OP_LI(0x395),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },

+  {"bbo",      OP_SI(0x4A),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },

   {"bbo",      OP_REG(0x394),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit One - annulled */
 
   {"bbo",      OP_REG(0x394),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit One - annulled */
 

-  {"bbo.a",    OP_SI(0x4B),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },

   {"bbo.a",    OP_LI(0x397),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbo.a",    OP_LI(0x397),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },

+  {"bbo.a",    OP_SI(0x4B),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },

   {"bbo.a",    OP_REG(0x396),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit Zero - nonannulled */
 
   {"bbo.a",    OP_REG(0x396),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit Zero - nonannulled */
 

-  {"bbz",      OP_SI(0x48),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },

   {"bbz",      OP_LI(0x391),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbz",      OP_LI(0x391),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },

+  {"bbz",      OP_SI(0x48),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },

   {"bbz",      OP_REG(0x390),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit Zero - annulled */
 
   {"bbz",      OP_REG(0x390),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Bit Zero - annulled */
 

-  {"bbz.a",    OP_SI(0x49),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },

   {"bbz.a",    OP_LI(0x393),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },
   {"bbz.a",    OP_LI(0x393),   MASK_LI,        0,      {OFF_SL_PC, REG_22, BITNUM}     },

+  {"bbz.a",    OP_SI(0x49),    MASK_SI,        0,      {OFF_SS_PC, REG_22, BITNUM}     },

   {"bbz.a",    OP_REG(0x392),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Conditional - nonannulled */
 
   {"bbz.a",    OP_REG(0x392),  MASK_REG,       0,      {REG_0, REG_22, BITNUM}         },
 
   /* Branch Conditional - nonannulled */
 

-  {"bcnd",     OP_SI(0x4C),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },

   {"bcnd",     OP_LI(0x399),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
   {"bcnd",     OP_LI(0x399),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },

+  {"bcnd",     OP_SI(0x4C),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },

   {"bcnd",     OP_REG(0x398),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 
   /* Branch Conditional - annulled */
 
   {"bcnd",     OP_REG(0x398),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 
   /* Branch Conditional - annulled */
 

-  {"bcnd.a",   OP_SI(0x4D),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },

   {"bcnd.a",   OP_LI(0x39B),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },
   {"bcnd.a",   OP_LI(0x39B),   MASK_LI,        0,      {OFF_SL_PC, REG_22, CC} },

+  {"bcnd.a",   OP_SI(0x4D),    MASK_SI,        0,      {OFF_SS_PC, REG_22, CC} },

   {"bcnd.a",   OP_REG(0x39A),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 
   /* Branch Control Register */
   {"bcnd.a",   OP_REG(0x39A),  MASK_REG,       0,      {REG_0, REG_22, CC}     },
 
   /* Branch Control Register */


@@ -692,14 +694,14 @@ const struct tic80_opcode tic80_opcodes[] = {
 
   /* Branch and save return - nonannulled */
 
 
   /* Branch and save return - nonannulled */
 

-  {"bsr",      OP_SI(0x40),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },

   {"bsr",      OP_LI(0x381),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
   {"bsr",      OP_LI(0x381),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },

+  {"bsr",      OP_SI(0x40),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },

   {"bsr",      OP_REG(0x380),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 
   /* Branch and save return - annulled */
 
   {"bsr",      OP_REG(0x380),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 
   /* Branch and save return - annulled */
 

-  {"bsr.a",    OP_SI(0x41),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },

   {"bsr.a",    OP_LI(0x383),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },
   {"bsr.a",    OP_LI(0x383),   MASK_LI,        0,      {OFF_SL_PC, REG_DEST}   },

+  {"bsr.a",    OP_SI(0x41),    MASK_SI,        0,      {OFF_SS_PC, REG_DEST}   },

   {"bsr.a",    OP_REG(0x382),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 
   /* Send command */
   {"bsr.a",    OP_REG(0x382),  MASK_REG,       0,      {REG_0, REG_DEST}       },
 
   /* Send command */


@@ -728,32 +730,32 @@ const struct tic80_opcode tic80_opcodes[] = {
 
   /* Direct load signed data into register */
 
 
   /* Direct load signed data into register */
 

-  {"dld",      OP_LI(0x345)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dld",      OP_REG(0x344) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dld.b",    OP_LI(0x341)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dld.b",    OP_REG(0x340) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dld.d",    OP_LI(0x347)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} },
-  {"dld.d",    OP_REG(0x346) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
-  {"dld.h",    OP_LI(0x343)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dld.h",    OP_REG(0x342) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
+  {"dld",      OP_LI(0x345)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"dld",      OP_REG(0x344) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"dld.b",    OP_LI(0x341)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"dld.b",    OP_REG(0x340) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"dld.d",    OP_LI(0x347)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E}   },
+  {"dld.d",    OP_REG(0x346) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST_E}         },
+  {"dld.h",    OP_LI(0x343)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"dld.h",    OP_REG(0x342) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },

 
   /* Direct load unsigned data into register */
 
 
   /* Direct load unsigned data into register */
 

-  {"dld.ub",   OP_LI(0x351)  | D(1),   (MASK_LI  &  ~M_REG(1)) | D(1), 0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dld.ub",   OP_REG(0x350) | D(1),   (MASK_REG & ~M_REG(1))  | D(1), 0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dld.uh",   OP_LI(0x353)  | D(1),   (MASK_LI  &  ~M_REG(1)) | D(1), 0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dld.uh",   OP_REG(0x352) | D(1),   (MASK_REG & ~M_REG(1))  | D(1), 0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
+  {"dld.ub",   OP_LI(0x351)  | D(1),   (MASK_LI  &  ~M_REG(1)) | D(1), 0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"dld.ub",   OP_REG(0x350) | D(1),   (MASK_REG & ~M_REG(1))  | D(1), 0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"dld.uh",   OP_LI(0x353)  | D(1),   (MASK_LI  &  ~M_REG(1)) | D(1), 0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"dld.uh",   OP_REG(0x352) | D(1),   (MASK_REG & ~M_REG(1))  | D(1), 0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },

 
   /* Direct store data into memory */
 
 
   /* Direct store data into memory */
 

-  {"dst",      OP_LI(0x365)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dst",      OP_REG(0x364) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dst.b",    OP_LI(0x361)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dst.b",    OP_REG(0x360) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dst.d",    OP_LI(0x367)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} },
-  {"dst.d",    OP_REG(0x366) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
-  {"dst.h",    OP_LI(0x363)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"dst.h",    OP_REG(0x362) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
+  {"dst",      OP_LI(0x365)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"dst",      OP_REG(0x364) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"dst.b",    OP_LI(0x361)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"dst.b",    OP_REG(0x360) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"dst.d",    OP_LI(0x367)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E}   },
+  {"dst.d",    OP_REG(0x366) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST_E}         },
+  {"dst.h",    OP_LI(0x363)  | D(1),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"dst.h",    OP_REG(0x362) | D(1),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },

 
   /* Emulation stop */
 
 
   /* Emulation stop */
 


@@ -938,27 +940,27 @@ const struct tic80_opcode tic80_opcodes[] = {
 
   /* Load Signed Data Into Register */
 
 
   /* Load Signed Data Into Register */
 

-  {"ld",       OP_SI(0x22),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
-  {"ld",       OP_LI(0x345)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"ld",       OP_REG(0x344) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"ld.b",     OP_SI(0x20),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
-  {"ld.b",     OP_LI(0x341)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"ld.b",     OP_REG(0x340) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"ld.d",     OP_SI(0x23),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST_E}                },
-  {"ld.d",     OP_LI(0x347)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} },
-  {"ld.d",     OP_REG(0x346) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
-  {"ld.h",     OP_SI(0x21),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
-  {"ld.h",     OP_LI(0x343)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"ld.h",     OP_REG(0x342) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
+  {"ld",       OP_SI(0x22),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}            },
+  {"ld",       OP_LI(0x345)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"ld",       OP_REG(0x344) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"ld.b",     OP_SI(0x20),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}            },
+  {"ld.b",     OP_LI(0x341)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"ld.b",     OP_REG(0x340) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"ld.d",     OP_SI(0x23),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E}          },
+  {"ld.d",     OP_LI(0x347)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E}   },
+  {"ld.d",     OP_REG(0x346) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST_E}         },
+  {"ld.h",     OP_SI(0x21),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}            },
+  {"ld.h",     OP_LI(0x343)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"ld.h",     OP_REG(0x342) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },

 
   /* Load Unsigned Data Into Register */
 
 
   /* Load Unsigned Data Into Register */
 

-  {"ld.ub",    OP_SI(0x28),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
-  {"ld.ub",    OP_LI(0x351)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"ld.ub",    OP_REG(0x350) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"ld.uh",    OP_SI(0x29),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}          },
-  {"ld.uh",    OP_LI(0x353)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"ld.uh",    OP_REG(0x352) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
+  {"ld.ub",    OP_SI(0x28),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}            },
+  {"ld.ub",    OP_LI(0x351)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"ld.ub",    OP_REG(0x350) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"ld.uh",    OP_SI(0x29),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}            },
+  {"ld.uh",    OP_LI(0x353)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"ld.uh",    OP_REG(0x352) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },

 
   /* Leftmost one */
 
 
   /* Leftmost one */
 


@@ -1089,18 +1091,18 @@ const struct tic80_opcode tic80_opcodes[] = {
 
   /* Store Data into Memory */
 
 
   /* Store Data into Memory */
 

-  {"st",       OP_SI(0x32),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}},
-  {"st",       OP_LI(0x365)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"st",       OP_REG(0x364) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"st.b",     OP_SI(0x30),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}},
-  {"st.b",     OP_LI(0x361)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"st.b",     OP_REG(0x360) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"st.d",     OP_SI(0x33),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST_E}},
-  {"st.d",     OP_LI(0x367)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} },
-  {"st.d",     OP_REG(0x366) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} },
-  {"st.h",     OP_SI(0x31),            (MASK_SI  & ~M_SI(1)),          0,      {SSI, REG_BASE_M_SI, REG_DEST}},
-  {"st.h",     OP_LI(0x363)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {LSI_SCALED, REG_BASE_M_LI, REG_DEST}   },
-  {"st.h",     OP_REG(0x362) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}   },
+  {"st",       OP_SI(0x32),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}            },
+  {"st",       OP_LI(0x365)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"st",       OP_REG(0x364) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"st.b",     OP_SI(0x30),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}            },
+  {"st.b",     OP_LI(0x361)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"st.b",     OP_REG(0x360) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },
+  {"st.d",     OP_SI(0x33),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E}          },
+  {"st.d",     OP_LI(0x367)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E}   },
+  {"st.d",     OP_REG(0x366) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST_E}         },
+  {"st.h",     OP_SI(0x31),            (MASK_SI  & ~M_SI(1)),          0,      {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}            },
+  {"st.h",     OP_LI(0x363)  | D(0),   (MASK_LI  & ~M_REG(1)) | D(1),  0,      {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}     },
+  {"st.h",     OP_REG(0x362) | D(0),   (MASK_REG & ~M_REG(1)) | D(1),  0,      {REG_SCALED, REG_BASE_M_LI, REG_DEST}           },

 
   /* Signed Integer Subtract */
 
 
   /* Signed Integer Subtract */