-{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
-{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
-{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
-{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
-/* end-sanitize-v850e */
-{ "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-
-/* start-sanitize-v850eq */
-{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ },
-{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ },
-{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ },
-{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ },
-{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ },
-{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ },
-{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ },
-{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ },
-/* end-sanitize-v850eq */
-
-{ "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL },
-{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
-/* start-sanitize-v850e */
-{ "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
-/* end-sanitize-v850e */
-{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL },
-{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL },
-{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL },
-{ "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL },
-{ "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL },
-{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL },
-{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL },
-
-/* saturated operation instructions */
-{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
+ pp = (cacheop & 0x60) >> 5;
+ PPPPP = (cacheop & 0x1f);
+
+ ret = insn | (pp << 11) | (PPPPP << 27);
+
+ return ret;
+}
+
+static unsigned long
+extract_CACHEOP (unsigned long insn, int * invalid)
+{
+ unsigned long ret;
+ unsigned long pp,PPPPP;
+ unsigned long insn2;
+
+ insn2 = insn >> 16;
+
+ PPPPP = ((insn2 & 0xf800) >> 11);
+ pp = ((insn & 0x1800) >> 11);
+
+ ret = (pp << 5) | PPPPP;
+
+ if (invalid != 0)
+ *invalid = 0;
+
+ return ret;
+}
+
+static unsigned long
+insert_PREFOP (unsigned long insn, long prefop, const char ** errmsg ATTRIBUTE_UNUSED)
+{
+ unsigned long ret;
+ unsigned long PPPPP;
+
+ PPPPP = (prefop & 0x1f);
+
+ ret = insn | (PPPPP << 27);
+
+ return ret;
+}
+
+static unsigned long
+extract_PREFOP (unsigned long insn, int * invalid)
+{
+ unsigned long ret;
+ unsigned long PPPPP;
+ unsigned long insn2;
+
+ insn2 = insn >> 16;
+
+ PPPPP = (insn2 & 0xf800) >> 11;
+
+ ret = PPPPP;
+
+ if (invalid != 0)
+ *invalid = 0;
+
+ return ret;
+}
+
+static unsigned long
+insert_IMM10U (unsigned long insn, long value, const char ** errmsg)
+{
+ unsigned long imm10, ret;
+ unsigned long iiiii,IIIII;
+
+ if (value > 0x3ff || value < 0)
+ * errmsg = _(imm10_out_of_range);
+
+ imm10 = ((unsigned long) value) & 0x3ff;
+ IIIII = (imm10 >> 5) & 0x1f;
+ iiiii = imm10 & 0x1f;
+
+ ret = insn | IIIII << 27 | iiiii;
+
+ return ret;
+}
+
+static unsigned long
+extract_IMM10U (unsigned long insn, int * invalid)
+{
+ unsigned long ret;
+ unsigned long iiiii,IIIII;
+ unsigned long insn2;
+ insn2 = insn >> 16;
+
+ IIIII = ((insn2 & 0xf800) >> 11);
+ iiiii = (insn & 0x001f);
+
+ ret = (IIIII << 5) | iiiii;
+
+ if (invalid != 0)
+ *invalid = 0;
+
+ return ret;
+}
+
+static unsigned long
+insert_SRSEL1 (unsigned long insn, long value, const char ** errmsg)
+{
+ unsigned long imm10, ret;
+ unsigned long sr,selid;
+
+ if (value > 0x3ff || value < 0)
+ * errmsg = _(sr_selid_out_of_range);
+
+ imm10 = (unsigned long) value;
+ selid = (imm10 & 0x3e0) >> 5;
+ sr = imm10 & 0x1f;
+
+ ret = insn | selid << 27 | sr;
+
+ return ret;
+}
+
+static unsigned long
+extract_SRSEL1 (unsigned long insn, int * invalid)
+{
+ unsigned long ret;
+ unsigned long sr, selid;
+ unsigned long insn2;
+
+ insn2 = insn >> 16;
+
+ selid = ((insn2 & 0xf800) >> 11);
+ sr = (insn & 0x001f);
+
+ ret = (selid << 5) | sr;
+
+ if (invalid != 0)
+ *invalid = 0;
+
+ return ret;
+}
+
+static unsigned long
+insert_SRSEL2 (unsigned long insn, long value, const char ** errmsg)
+{
+ unsigned long imm10, ret;
+ unsigned long sr, selid;
+
+ if (value > 0x3ff || value < 0)
+ * errmsg = _(sr_selid_out_of_range);
+
+ imm10 = (unsigned long) value;
+ selid = (imm10 & 0x3e0) >> 5;
+ sr = imm10 & 0x1f;
+
+ ret = insn | selid << 27 | sr << 11;
+
+ return ret;
+}
+
+static unsigned long
+extract_SRSEL2 (unsigned long insn, int * invalid)
+{
+ unsigned long ret;
+ unsigned long sr, selid;
+ unsigned long insn2;
+
+ insn2 = insn >> 16;
+
+ selid = ((insn2 & 0xf800) >> 11);
+ sr = ((insn & 0xf800) >> 11);
+
+ ret = (selid << 5) | sr;
+
+ if (invalid != 0)
+ *invalid = 0;
+
+ return ret;
+}
+\f
+/* Warning: code in gas/config/tc-v850.c examines the contents of this array.
+ If you change any of the values here, be sure to look for side effects in
+ that code. */
+const struct v850_operand v850_operands[] =
+{
+#define UNUSED 0
+ { 0, 0, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The R1 field in a format 1, 6, 7, 9, C insn. */
+#define R1 (UNUSED + 1)
+ { 5, 0, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
+
+/* As above, but register 0 is not allowed. */
+#define R1_NOTR0 (R1 + 1)
+ { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
+
+/* Even register is allowed. */
+#define R1_EVEN (R1_NOTR0 + 1)
+ { 4, 1, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
+
+/* Bang (bit reverse). */
+#define R1_BANG (R1_EVEN + 1)
+ { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_BANG, BFD_RELOC_NONE },
+
+/* Percent (modulo). */
+#define R1_PERCENT (R1_BANG + 1)
+ { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_OPERAND_PERCENT, BFD_RELOC_NONE },
+
+/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9, C insn. */
+#define R2 (R1_PERCENT + 1)
+ { 5, 11, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
+
+/* As above, but register 0 is not allowed. */
+#define R2_NOTR0 (R2 + 1)
+ { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
+
+/* Even register is allowed. */
+#define R2_EVEN (R2_NOTR0 + 1)
+ { 4, 12, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
+
+/* Reg2 in dispose instruction. */
+#define R2_DISPOSE (R2_EVEN + 1)
+ { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
+
+/* The R3 field in a format 11, 12, C insn. */
+#define R3 (R2_DISPOSE + 1)
+ { 5, 27, NULL, NULL, V850_OPERAND_REG, BFD_RELOC_NONE },
+
+/* As above, but register 0 is not allowed. */
+#define R3_NOTR0 (R3 + 1)
+ { 5, 27, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0, BFD_RELOC_NONE },
+
+/* As above, but odd number registers are not allowed. */
+#define R3_EVEN (R3_NOTR0 + 1)
+ { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
+
+/* As above, but register 0 is not allowed. */
+#define R3_EVEN_NOTR0 (R3_EVEN + 1)
+ { 4, 28, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN | V850_NOT_R0, BFD_RELOC_NONE },
+
+/* Forth register in FPU Instruction. */
+#define R4 (R3_EVEN_NOTR0 + 1)
+ { 5, 0, insert_r4, extract_r4, V850_OPERAND_REG, BFD_RELOC_NONE },
+
+/* As above, but odd number registers are not allowed. */
+#define R4_EVEN (R4 + 1)
+ { 4, 17, NULL, NULL, V850_OPERAND_REG | V850_REG_EVEN, BFD_RELOC_NONE },
+
+/* Stack pointer in prepare instruction. */
+#define SP (R4_EVEN + 1)
+ { 2, 0, insert_spe, extract_spe, V850_OPERAND_REG, BFD_RELOC_NONE },
+
+/* EP Register. */
+#define EP (SP + 1)
+ { 0, 0, NULL, NULL, V850_OPERAND_EP, BFD_RELOC_NONE },
+
+/* A list of registers in a prepare/dispose instruction. */
+#define LIST12 (EP + 1)
+ { -1, 0xffe00001, NULL, NULL, V850E_OPERAND_REG_LIST, BFD_RELOC_NONE },
+
+/* System register operands. */
+#define OLDSR1 (LIST12 + 1)
+ { 5, 0, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
+
+#define SR1 (OLDSR1 + 1)
+ { 0, 0, insert_SRSEL1, extract_SRSEL1, V850_OPERAND_SRG, BFD_RELOC_NONE },
+
+/* The R2 field as a system register. */
+#define OLDSR2 (SR1 + 1)
+ { 5, 11, NULL, NULL, V850_OPERAND_SRG, BFD_RELOC_NONE },
+
+#define SR2 (OLDSR2 + 1)
+ { 0, 0, insert_SRSEL2, extract_SRSEL2, V850_OPERAND_SRG, BFD_RELOC_NONE },
+
+/* FPU CC bit position. */
+#define FFF (SR2 + 1)
+ { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 4 bit condition code in a setf instruction. */
+#define CCCC (FFF + 1)
+ { 4, 0, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
+
+/* Condition code in adf,sdf. */
+#define CCCC_NOTSA (CCCC + 1)
+ { 4, 17, NULL, NULL, V850_OPERAND_CC|V850_NOT_SA, BFD_RELOC_NONE },
+
+/* Condition code in conditional moves. */
+#define MOVCC (CCCC_NOTSA + 1)
+ { 4, 17, NULL, NULL, V850_OPERAND_CC, BFD_RELOC_NONE },
+
+/* Condition code in FPU. */
+#define FLOAT_CCCC (MOVCC + 1)
+ { 4, 27, NULL, NULL, V850_OPERAND_FLOAT_CC, BFD_RELOC_NONE },
+
+/* The 1 bit immediate field in format C insn. */
+#define VI1 (FLOAT_CCCC + 1)
+ { 1, 3, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 1 bit immediate field in format C insn. */
+#define VC1 (VI1 + 1)
+ { 1, 0, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 2 bit immediate field in format C insn. */
+#define DI2 (VC1 + 1)
+ { 2, 17, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 2 bit immediate field in format C insn. */
+#define VI2 (DI2 + 1)
+ { 2, 0, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 2 bit immediate field in format C - DUP insn. */
+#define VI2DUP (VI2 + 1)
+ { 2, 2, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 3 bit immediate field in format 8 insn. */
+#define B3 (VI2DUP + 1)
+ { 3, 11, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 3 bit immediate field in format C insn. */
+#define DI3 (B3 + 1)
+ { 3, 17, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 3 bit immediate field in format C insn. */
+#define I3U (DI3 + 1)
+ { 3, 0, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 4 bit immediate field in format C insn. */
+#define I4U (I3U + 1)
+ { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The 4 bit immediate field in fetrap. */
+#define I4U_NOTIMM0 (I4U + 1)
+ { 4, 11, NULL, NULL, V850_NOT_IMM0, BFD_RELOC_NONE },
+
+/* The unsigned disp4 field in a sld.bu. */
+#define D4U (I4U_NOTIMM0 + 1)
+ { 4, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_4_OFFSET },
+
+/* The imm5 field in a format 2 insn. */
+#define I5 (D4U + 1)
+ { 5, 0, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
+
+/* The imm5 field in a format 11 insn. */
+#define I5DIV1 (I5 + 1)
+ { 5, 0, insert_i5div1, extract_i5div1, 0, BFD_RELOC_NONE },
+
+#define I5DIV2 (I5DIV1 + 1)
+ { 5, 0, insert_i5div2, extract_i5div2, 0, BFD_RELOC_NONE },
+
+#define I5DIV3 (I5DIV2 + 1)
+ { 5, 0, insert_i5div3, extract_i5div3, 0, BFD_RELOC_NONE },
+
+/* The unsigned imm5 field in a format 2 insn. */
+#define I5U (I5DIV3 + 1)
+ { 5, 0, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The imm5 field in a prepare/dispose instruction. */
+#define IMM5 (I5U + 1)
+ { 5, 1, NULL, NULL, 0, BFD_RELOC_NONE },
+
+/* The unsigned disp5 field in a sld.hu. */
+#define D5_4U (IMM5 + 1)
+ { 5, 0, insert_d5_4, extract_d5_4, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_4_5_OFFSET },
+
+/* The IMM6 field in a callt instruction. */
+#define IMM6 (D5_4U + 1)
+ { 6, 0, NULL, NULL, 0, BFD_RELOC_V850_CALLT_6_7_OFFSET },
+
+/* The signed disp7 field in a format 4 insn. */
+#define D7U (IMM6 + 1)
+ { 7, 0, NULL, NULL, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_7_OFFSET },
+
+/* The unsigned DISP8 field in a format 4 insn. */
+#define D8_7U (D7U + 1)
+ { 8, 0, insert_d8_7, extract_d8_7, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_7_8_OFFSET },
+
+/* The unsigned DISP8 field in a format 4 insn. */
+#define D8_6U (D8_7U + 1)
+ { 8, 0, insert_d8_6, extract_d8_6, V850_OPERAND_DISP, BFD_RELOC_V850_TDA_6_8_OFFSET },
+
+/* The unsigned DISP8 field in a format 4 insn. */
+#define V8 (D8_6U + 1)
+ { 8, 0, insert_v8, extract_v8, 0, BFD_RELOC_NONE },
+
+/* The imm9 field in a multiply word. */
+#define I9 (V8 + 1)
+ { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED, BFD_RELOC_NONE },
+
+/* The unsigned imm9 field in a multiply word. */
+#define U9 (I9 + 1)
+ { 9, 0, insert_u9, extract_u9, 0, BFD_RELOC_NONE },
+
+/* The DISP9 field in a format 3 insn. */
+#define D9 (U9 + 1)
+ { 9, 0, insert_d9, extract_d9, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
+
+/* The DISP9 field in a format 3 insn, relaxable. */
+#define D9_RELAX (D9 + 1)
+ { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_9_PCREL },
+
+/* The imm16 field in a format 6 insn. */
+#define I16 (D9_RELAX + 1)
+ { 16, 16, NULL, NULL, V850_OPERAND_SIGNED, BFD_RELOC_16 },
+
+/* The signed 16 bit immediate following a prepare instruction. */
+#define IMM16LO (I16 + 1)
+ { 16, 32, NULL, NULL, V850E_IMMEDIATE16 | V850_OPERAND_SIGNED, BFD_RELOC_LO16 },
+
+/* The hi 16 bit immediate following a 32 bit instruction. */
+#define IMM16HI (IMM16LO + 1)
+ { 16, 16, NULL, NULL, V850E_IMMEDIATE16HI, BFD_RELOC_HI16 },
+
+/* The unsigned imm16 in a format 6 insn. */
+#define I16U (IMM16HI + 1)
+ { 16, 16, NULL, NULL, 0, BFD_RELOC_16 },
+
+/* The disp16 field in a format 8 insn. */
+#define D16 (I16U + 1)
+ { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_16 },
+
+/* The disp16 field in an format 7 unsigned byte load insn. */
+#define D16_16 (D16 + 1)
+ { 16, 0, insert_d16_16, extract_d16_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_16_SPLIT_OFFSET },
+
+/* The disp16 field in a format 6 insn. */
+#define D16_15 (D16_16 + 1)
+ { 16, 0, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED | V850_OPERAND_DISP , BFD_RELOC_V850_16_S1 },
+
+/* The unsigned DISP16 field in a format 7 insn. */
+#define D16_LOOP (D16_15 + 1)
+ { 16, 0, insert_u16_loop, extract_u16_loop, V850_OPERAND_RELAX | V850_OPERAND_DISP | V850_PCREL | V850_INVERSE_PCREL, BFD_RELOC_V850_16_PCREL },
+
+/* The DISP17 field in a format 7 insn. */
+#define D17_16 (D16_LOOP + 1)
+ { 17, 0, insert_d17_16, extract_d17_16, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_17_PCREL },
+
+/* The DISP22 field in a format 4 insn, relaxable.
+ This _must_ follow D9_RELAX; the assembler assumes that the longer
+ version immediately follows the shorter version for relaxing. */
+#define D22 (D17_16 + 1)
+ { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_22_PCREL },
+
+#define D23 (D22 + 1)
+ { 23, 0, insert_d23, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
+
+#define D23_ALIGN1 (D23 + 1)
+ { 23, 0, insert_d23_align1, extract_d23, V850E_IMMEDIATE23 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_23 },
+
+/* The 32 bit immediate following a 32 bit instruction. */
+#define IMM32 (D23_ALIGN1 + 1)
+ { 32, 32, NULL, NULL, V850E_IMMEDIATE32, BFD_RELOC_32 },
+
+#define D32_31 (IMM32 + 1)
+ { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP, BFD_RELOC_V850_32_ABS },
+
+#define D32_31_PCREL (D32_31 + 1)
+ { 32, 32, NULL, NULL, V850E_IMMEDIATE32 | V850_OPERAND_SIGNED | V850_OPERAND_DISP | V850_PCREL, BFD_RELOC_V850_32_PCREL },
+
+#define POS_U (D32_31_PCREL + 1)
+ { 0, 0, insert_POS, extract_POS_U, 0, BFD_RELOC_NONE },
+
+#define POS_M (POS_U + 1)
+ { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
+
+#define POS_L (POS_M + 1)
+ { 0, 0, insert_POS, extract_POS_L, 0, BFD_RELOC_NONE },
+
+#define WIDTH_U (POS_L + 1)
+ { 0, 0, insert_WIDTH, extract_WIDTH_U, 0, BFD_RELOC_NONE },
+
+#define WIDTH_M (WIDTH_U + 1)
+ { 0, 0, insert_WIDTH, extract_WIDTH_M, 0, BFD_RELOC_NONE },
+
+#define WIDTH_L (WIDTH_M + 1)
+ { 0, 0, insert_WIDTH, extract_WIDTH_L, 0, BFD_RELOC_NONE },
+
+#define SELID (WIDTH_L + 1)
+ { 5, 27, insert_SELID, extract_SELID, 0, BFD_RELOC_NONE },
+
+#define RIE_IMM5 (SELID + 1)
+ { 5, 11, NULL, NULL, 0, BFD_RELOC_NONE },
+
+#define RIE_IMM4 (RIE_IMM5 + 1)
+ { 4, 0, NULL, NULL, 0, BFD_RELOC_NONE },
+
+#define VECTOR8 (RIE_IMM4 + 1)
+ { 0, 0, insert_VECTOR8, extract_VECTOR8, 0, BFD_RELOC_NONE },
+
+#define VECTOR5 (VECTOR8 + 1)
+ { 0, 0, insert_VECTOR5, extract_VECTOR5, 0, BFD_RELOC_NONE },
+
+#define VR1 (VECTOR5 + 1)
+ { 5, 0, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
+
+#define VR2 (VR1 + 1)
+ { 5, 11, NULL, NULL, V850_OPERAND_VREG, BFD_RELOC_NONE },
+
+#define CACHEOP (VR2 + 1)
+ { 0, 0, insert_CACHEOP, extract_CACHEOP, V850_OPERAND_CACHEOP, BFD_RELOC_NONE },
+
+#define PREFOP (CACHEOP + 1)
+ { 0, 0, insert_PREFOP, extract_PREFOP, V850_OPERAND_PREFOP, BFD_RELOC_NONE },
+
+#define IMM10U (PREFOP + 1)
+ { 0, 0, insert_IMM10U, extract_IMM10U, 0, BFD_RELOC_NONE },
+};
+
+\f
+/* Reg - Reg instruction format (Format I). */
+#define IF1 {R1, R2}
+
+/* Imm - Reg instruction format (Format II). */
+#define IF2 {I5, R2}
+
+/* Conditional branch instruction format (Format III). */
+#define IF3 {D9_RELAX}
+
+/* 3 operand instruction (Format VI). */
+#define IF6 {I16, R1, R2}
+
+/* 3 operand instruction (Format VI). */
+#define IF6U {I16U, R1, R2}
+
+/* Conditional branch instruction format (Format VII). */
+#define IF7 {D17_16}
+
+\f
+/* The opcode table.
+
+ The format of the opcode table is:
+
+ NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR
+
+ NAME is the name of the instruction.
+ OPCODE is the instruction opcode.
+ MASK is the opcode mask; this is used to tell the disassembler
+ which bits in the actual opcode must match OPCODE.
+ OPERANDS is the list of operands.
+ MEMOP specifies which operand (if any) is a memory operand.
+ PROCESSORS specifies which CPU(s) support the opcode.
+
+ The disassembler reads the table in order and prints the first
+ instruction which matches, so this table is sorted to put more
+ specific instructions before more general instructions. It is also
+ sorted by major opcode.
+
+ The table is also sorted by name. This is used by the assembler.
+ When parsing an instruction the assembler finds the first occurance
+ of the name of the instruciton in this table and then attempts to
+ match the instruction's arguments with description of the operands
+ associated with the entry it has just found in this table. If the
+ match fails the assembler looks at the next entry in this table.
+ If that entry has the same name as the previous entry, then it
+ tries to match the instruction against that entry and so on. This
+ is how the assembler copes with multiple, different formats of the
+ same instruction. */
+
+const struct v850_opcode v850_opcodes[] =
+{
+/* Standard instructions. */
+{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL },
+{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL },
+
+{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL },
+
+{ "adf", two (0x07e0, 0x03a0), two (0x07e0, 0x07e1), {CCCC_NOTSA, R1, R2, R3}, 0, PROCESSOR_V850E2_UP },