+void
+aarch64_set_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp, int32_t val)
+{
+ if (reg == R31 && ! r31_is_sp)
+ {
+ TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
+ return;
+ }
+
+ if (val != cpu->gr[reg].s32)
+ TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
+ reg, cpu->gr[reg].s32, val);
+
+ /* The ARM ARM states that (C1.2.4):
+ When the data size is 32 bits, the lower 32 bits of the
+ register are used and the upper 32 bits are ignored on
+ a read and cleared to zero on a write.
+ We simulate this by first clearing the whole 64-bits and
+ then writing to the 32-bit value in the GRegister union. */
+ cpu->gr[reg].s64 = 0;
+ cpu->gr[reg].s32 = val;
+}
+
+void
+aarch64_set_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint32_t val)
+{
+ if (reg == R31 && ! r31_is_sp)
+ {
+ TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
+ return;
+ }
+
+ if (val != cpu->gr[reg].u32)
+ TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
+ reg, cpu->gr[reg].u32, val);
+
+ cpu->gr[reg].u64 = 0;
+ cpu->gr[reg].u32 = val;
+}
+