- if ((BITS(4,7) & 0x9) == 0x9) {
- /* LDR immediate offset, write-back, up, pre indexed */
- LHPREUPWB() ;
- /* continue instruction decoding */
- }
-#endif
- dest = ~DPSRegRHS ;
- WRITESDEST(dest) ;
- break ;
-
-/***************************************************************************\
-* Data Processing Immediate RHS Instructions *
-\***************************************************************************/
-
- case 0x20 : /* AND immed */
- dest = LHS & DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x21 : /* ANDS immed */
- DPSImmRHS ;
- dest = LHS & rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x22 : /* EOR immed */
- dest = LHS ^ DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x23 : /* EORS immed */
- DPSImmRHS ;
- dest = LHS ^ rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x24 : /* SUB immed */
- dest = LHS - DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x25 : /* SUBS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = lhs - rhs ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x26 : /* RSB immed */
- dest = DPImmRHS - LHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x27 : /* RSBS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = rhs - lhs ;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,rhs,lhs,dest) ;
- ARMul_SubOverflow(state,rhs,lhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x28 : /* ADD immed */
- dest = LHS + DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x29 : /* ADDS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = lhs + rhs ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x2a : /* ADC immed */
- dest = LHS + DPImmRHS + CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x2b : /* ADCS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = lhs + rhs + CFLAG ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x2c : /* SBC immed */
- dest = LHS - DPImmRHS - !CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x2d : /* SBCS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = lhs - rhs - !CFLAG ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x2e : /* RSC immed */
- dest = DPImmRHS - LHS - !CFLAG ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x2f : /* RSCS immed */
- lhs = LHS ;
- rhs = DPImmRHS ;
- dest = rhs - lhs - !CFLAG ;
- if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,rhs,lhs,dest) ;
- ARMul_SubOverflow(state,rhs,lhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- WRITESDEST(dest) ;
- break ;
-
- case 0x30 : /* TST immed */
- UNDEF_Test ;
- break ;
-
- case 0x31 : /* TSTP immed */
- if (DESTReg == 15) { /* TSTP immed */
-#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
-#else
- temp = LHS & DPImmRHS ;
- SETR15PSR(temp) ;
-#endif
- }
- else {
- DPSImmRHS ; /* TST immed */
- dest = LHS & rhs ;
- ARMul_NegZero(state,dest) ;
- }
- break ;
-
- case 0x32 : /* TEQ immed and MSR immed to CPSR */
- if (DESTReg==15 && BITS(17,18)==0) { /* MSR immed to CPSR */
- ARMul_FixCPSR(state,instr,DPImmRHS) ;
- }
- else {
- UNDEF_Test ;
- }
- break ;
-
- case 0x33 : /* TEQP immed */
- if (DESTReg == 15) { /* TEQP immed */
-#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
-#else
- temp = LHS ^ DPImmRHS ;
- SETR15PSR(temp) ;
-#endif
- }
- else {
- DPSImmRHS ; /* TEQ immed */
- dest = LHS ^ rhs ;
- ARMul_NegZero(state,dest) ;
- }
- break ;
-
- case 0x34 : /* CMP immed */
- UNDEF_Test ;
- break ;
-
- case 0x35 : /* CMPP immed */
- if (DESTReg == 15) { /* CMPP immed */
-#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
-#else
- temp = LHS - DPImmRHS ;
- SETR15PSR(temp) ;
-#endif
- break ;
- }
- else {
- lhs = LHS ; /* CMP immed */
- rhs = DPImmRHS ;
- dest = lhs - rhs ;
- ARMul_NegZero(state,dest) ;
- if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
- ARMul_SubCarry(state,lhs,rhs,dest) ;
- ARMul_SubOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARC ;
- CLEARV ;
- }
- }
- break ;
-
- case 0x36 : /* CMN immed and MSR immed to SPSR */
- if (DESTReg==15 && BITS(17,18)==0) /* MSR */
- ARMul_FixSPSR(state, instr, DPImmRHS) ;
- else {
- UNDEF_Test ;
- }
- break ;
-
- case 0x37 : /* CMNP immed */
- if (DESTReg == 15) { /* CMNP immed */
-#ifdef MODE32
- state->Cpsr = GETSPSR(state->Bank) ;
- ARMul_CPSRAltered(state) ;
-#else
- temp = LHS + DPImmRHS ;
- SETR15PSR(temp) ;
-#endif
- break ;
- }
- else {
- lhs = LHS ; /* CMN immed */
- rhs = DPImmRHS ;
- dest = lhs + rhs ;
- ASSIGNZ(dest==0) ;
- if ((lhs | rhs) >> 30) { /* possible C,V,N to set */
- ASSIGNN(NEG(dest)) ;
- ARMul_AddCarry(state,lhs,rhs,dest) ;
- ARMul_AddOverflow(state,lhs,rhs,dest) ;
- }
- else {
- CLEARN ;
- CLEARC ;
- CLEARV ;
- }
- }
- break ;
-
- case 0x38 : /* ORR immed */
- dest = LHS | DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x39 : /* ORRS immed */
- DPSImmRHS ;
- dest = LHS | rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x3a : /* MOV immed */
- dest = DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x3b : /* MOVS immed */
- DPSImmRHS ;
- WRITESDEST(rhs) ;
- break ;
-
- case 0x3c : /* BIC immed */
- dest = LHS & ~DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x3d : /* BICS immed */
- DPSImmRHS ;
- dest = LHS & ~rhs ;
- WRITESDEST(dest) ;
- break ;
-
- case 0x3e : /* MVN immed */
- dest = ~DPImmRHS ;
- WRITEDEST(dest) ;
- break ;
-
- case 0x3f : /* MVNS immed */
- DPSImmRHS ;
- WRITESDEST(~rhs) ;
- break ;
-
-/***************************************************************************\
-* Single Data Transfer Immediate RHS Instructions *
-\***************************************************************************/
-
- case 0x40 : /* Store Word, No WriteBack, Post Dec, Immed */
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- break ;
-
- case 0x41 : /* Load Word, No WriteBack, Post Dec, Immed */
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- break ;
-
- case 0x42 : /* Store Word, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- temp = lhs - LSImmRHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = temp ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x43 : /* Load Word, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x44 : /* Store Byte, No WriteBack, Post Dec, Immed */
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- break ;
-
- case 0x45 : /* Load Byte, No WriteBack, Post Dec, Immed */
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSImmRHS ;
- break ;
-
- case 0x46 : /* Store Byte, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x47 : /* Load Byte, WriteBack, Post Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x48 : /* Store Word, No WriteBack, Post Inc, Immed */
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- break ;
-
- case 0x49 : /* Load Word, No WriteBack, Post Inc, Immed */
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- break ;
-
- case 0x4a : /* Store Word, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x4b : /* Load Word, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x4c : /* Store Byte, No WriteBack, Post Inc, Immed */
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- break ;
-
- case 0x4d : /* Load Byte, No WriteBack, Post Inc, Immed */
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSImmRHS ;
- break ;
-
- case 0x4e : /* Store Byte, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x4f : /* Load Byte, WriteBack, Post Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSImmRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
-
- case 0x50 : /* Store Word, No WriteBack, Pre Dec, Immed */
- (void)StoreWord(state,instr,LHS - LSImmRHS) ;
- break ;
-
- case 0x51 : /* Load Word, No WriteBack, Pre Dec, Immed */
- (void)LoadWord(state,instr,LHS - LSImmRHS) ;
- break ;
-
- case 0x52 : /* Store Word, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS - LSImmRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x53 : /* Load Word, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS - LSImmRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x54 : /* Store Byte, No WriteBack, Pre Dec, Immed */
- (void)StoreByte(state,instr,LHS - LSImmRHS) ;
- break ;
-
- case 0x55 : /* Load Byte, No WriteBack, Pre Dec, Immed */
- (void)LoadByte(state,instr,LHS - LSImmRHS,LUNSIGNED) ;
- break ;
-
- case 0x56 : /* Store Byte, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS - LSImmRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x57 : /* Load Byte, WriteBack, Pre Dec, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS - LSImmRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
-
- case 0x58 : /* Store Word, No WriteBack, Pre Inc, Immed */
- (void)StoreWord(state,instr,LHS + LSImmRHS) ;
- break ;
-
- case 0x59 : /* Load Word, No WriteBack, Pre Inc, Immed */
- (void)LoadWord(state,instr,LHS + LSImmRHS) ;
- break ;
-
- case 0x5a : /* Store Word, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS + LSImmRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x5b : /* Load Word, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS + LSImmRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x5c : /* Store Byte, No WriteBack, Pre Inc, Immed */
- (void)StoreByte(state,instr,LHS + LSImmRHS) ;
- break ;
-
- case 0x5d : /* Load Byte, No WriteBack, Pre Inc, Immed */
- (void)LoadByte(state,instr,LHS + LSImmRHS,LUNSIGNED) ;
- break ;
-
- case 0x5e : /* Store Byte, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS + LSImmRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x5f : /* Load Byte, WriteBack, Pre Inc, Immed */
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- temp = LHS + LSImmRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
-
-/***************************************************************************\
-* Single Data Transfer Register RHS Instructions *
-\***************************************************************************/
-
- case 0x60 : /* Store Word, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x61 : /* Load Word, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x62 : /* Store Word, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x63 : /* Load Word, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x64 : /* Store Byte, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x65 : /* Load Byte, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x66 : /* Store Byte, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x67 : /* Load Byte, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x68 : /* Store Word, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x69 : /* Load Word, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6a : /* Store Word, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6b : /* Load Word, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6c : /* Store Byte, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6d : /* Load Byte, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6e : /* Store Byte, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6f : /* Load Byte, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
-
- case 0x70 : /* Store Word, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreWord(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x71 : /* Load Word, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadWord(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x72 : /* Store Word, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x73 : /* Load Word, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x74 : /* Store Byte, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreByte(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x75 : /* Load Byte, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadByte(state,instr,LHS - LSRegRHS,LUNSIGNED) ;
- break ;
-
- case 0x76 : /* Store Byte, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x77 : /* Load Byte, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
-
- case 0x78 : /* Store Word, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreWord(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x79 : /* Load Word, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadWord(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x7a : /* Store Word, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7b : /* Load Word, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7c : /* Store Byte, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreByte(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x7d : /* Load Byte, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadByte(state,instr,LHS + LSRegRHS,LUNSIGNED) ;
- break ;
-
- case 0x7e : /* Store Byte, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7f : /* Load Byte, WriteBack, Pre Inc, Reg */
- if (BIT(4))
- {
- /* Check for the special breakpoint opcode.
- This value should correspond to the value defined
- as ARM_BE_BREAKPOINT in gdb/arm-tdep.c. */
- if (BITS (0,19) == 0xfdefe)
- {
- if (! ARMul_OSHandleSWI (state, SWI_Breakpoint))
- ARMul_Abort (state, ARMul_SWIV);
- }
- else
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
-
-/***************************************************************************\
-* Multiple Data Transfer Instructions *
-\***************************************************************************/
-
- case 0x80 : /* Store, No WriteBack, Post Dec */
- STOREMULT(instr,LSBase - LSMNumRegs + 4L,0L) ;
- break ;
-
- case 0x81 : /* Load, No WriteBack, Post Dec */
- LOADMULT(instr,LSBase - LSMNumRegs + 4L,0L) ;
- break ;
-
- case 0x82 : /* Store, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs ;
- STOREMULT(instr,temp + 4L,temp) ;
- break ;
-
- case 0x83 : /* Load, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs ;
- LOADMULT(instr,temp + 4L,temp) ;
- break ;
-
- case 0x84 : /* Store, Flags, No WriteBack, Post Dec */
- STORESMULT(instr,LSBase - LSMNumRegs + 4L,0L) ;
- break ;
-
- case 0x85 : /* Load, Flags, No WriteBack, Post Dec */
- LOADSMULT(instr,LSBase - LSMNumRegs + 4L,0L) ;
- break ;
-
- case 0x86 : /* Store, Flags, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs ;
- STORESMULT(instr,temp + 4L,temp) ;
- break ;
-
- case 0x87 : /* Load, Flags, WriteBack, Post Dec */
- temp = LSBase - LSMNumRegs ;
- LOADSMULT(instr,temp + 4L,temp) ;
- break ;
-
-
- case 0x88 : /* Store, No WriteBack, Post Inc */
- STOREMULT(instr,LSBase,0L) ;
- break ;
-
- case 0x89 : /* Load, No WriteBack, Post Inc */
- LOADMULT(instr,LSBase,0L) ;
- break ;
-
- case 0x8a : /* Store, WriteBack, Post Inc */
- temp = LSBase ;
- STOREMULT(instr,temp,temp + LSMNumRegs) ;
- break ;
-
- case 0x8b : /* Load, WriteBack, Post Inc */
- temp = LSBase ;
- LOADMULT(instr,temp,temp + LSMNumRegs) ;
- break ;
-
- case 0x8c : /* Store, Flags, No WriteBack, Post Inc */
- STORESMULT(instr,LSBase,0L) ;
- break ;
-
- case 0x8d : /* Load, Flags, No WriteBack, Post Inc */
- LOADSMULT(instr,LSBase,0L) ;
- break ;
-
- case 0x8e : /* Store, Flags, WriteBack, Post Inc */
- temp = LSBase ;
- STORESMULT(instr,temp,temp + LSMNumRegs) ;
- break ;
-
- case 0x8f : /* Load, Flags, WriteBack, Post Inc */
- temp = LSBase ;
- LOADSMULT(instr,temp,temp + LSMNumRegs) ;
- break ;
-
-
- case 0x90 : /* Store, No WriteBack, Pre Dec */
- STOREMULT(instr,LSBase - LSMNumRegs,0L) ;
- break ;
-
- case 0x91 : /* Load, No WriteBack, Pre Dec */
- LOADMULT(instr,LSBase - LSMNumRegs,0L) ;
- break ;
-
- case 0x92 : /* Store, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs ;
- STOREMULT(instr,temp,temp) ;
- break ;
-
- case 0x93 : /* Load, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs ;
- LOADMULT(instr,temp,temp) ;
- break ;
-
- case 0x94 : /* Store, Flags, No WriteBack, Pre Dec */
- STORESMULT(instr,LSBase - LSMNumRegs,0L) ;
- break ;
-
- case 0x95 : /* Load, Flags, No WriteBack, Pre Dec */
- LOADSMULT(instr,LSBase - LSMNumRegs,0L) ;
- break ;
-
- case 0x96 : /* Store, Flags, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs ;
- STORESMULT(instr,temp,temp) ;
- break ;
-
- case 0x97 : /* Load, Flags, WriteBack, Pre Dec */
- temp = LSBase - LSMNumRegs ;
- LOADSMULT(instr,temp,temp) ;
- break ;
-
-
- case 0x98 : /* Store, No WriteBack, Pre Inc */
- STOREMULT(instr,LSBase + 4L,0L) ;
- break ;
-
- case 0x99 : /* Load, No WriteBack, Pre Inc */
- LOADMULT(instr,LSBase + 4L,0L) ;
- break ;
-
- case 0x9a : /* Store, WriteBack, Pre Inc */
- temp = LSBase ;
- STOREMULT(instr,temp + 4L,temp + LSMNumRegs) ;
- break ;
-
- case 0x9b : /* Load, WriteBack, Pre Inc */
- temp = LSBase ;
- LOADMULT(instr,temp + 4L,temp + LSMNumRegs) ;
- break ;
-
- case 0x9c : /* Store, Flags, No WriteBack, Pre Inc */
- STORESMULT(instr,LSBase + 4L,0L) ;
- break ;
-
- case 0x9d : /* Load, Flags, No WriteBack, Pre Inc */
- LOADSMULT(instr,LSBase + 4L,0L) ;
- break ;
-
- case 0x9e : /* Store, Flags, WriteBack, Pre Inc */
- temp = LSBase ;
- STORESMULT(instr,temp + 4L,temp + LSMNumRegs) ;
- break ;
-
- case 0x9f : /* Load, Flags, WriteBack, Pre Inc */
- temp = LSBase ;
- LOADSMULT(instr,temp + 4L,temp + LSMNumRegs) ;
- break ;
-
-/***************************************************************************\
-* Branch forward *
-\***************************************************************************/
-
- case 0xa0 : case 0xa1 : case 0xa2 : case 0xa3 :
- case 0xa4 : case 0xa5 : case 0xa6 : case 0xa7 :
- state->Reg[15] = pc + 8 + POSBRANCH ;
- FLUSHPIPE ;
- break ;
-
-/***************************************************************************\
-* Branch backward *
-\***************************************************************************/
-
- case 0xa8 : case 0xa9 : case 0xaa : case 0xab :
- case 0xac : case 0xad : case 0xae : case 0xaf :
- state->Reg[15] = pc + 8 + NEGBRANCH ;
- FLUSHPIPE ;
- break ;
-
-/***************************************************************************\
-* Branch and Link forward *
-\***************************************************************************/
-
- case 0xb0 : case 0xb1 : case 0xb2 : case 0xb3 :
- case 0xb4 : case 0xb5 : case 0xb6 : case 0xb7 :
-#ifdef MODE32
- state->Reg[14] = pc + 4 ; /* put PC into Link */