- case 0x60 : /* Store Word, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x61 : /* Load Word, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x62 : /* Store Word, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x63 : /* Load Word, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x64 : /* Store Byte, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x65 : /* Load Byte, No WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSRegRHS ;
- break ;
-
- case 0x66 : /* Store Byte, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x67 : /* Load Byte, WriteBack, Post Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs - LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x68 : /* Store Word, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x69 : /* Load Word, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6a : /* Store Word, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6b : /* Load Word, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadWord(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6c : /* Store Byte, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6d : /* Load Byte, No WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSRegRHS ;
- break ;
-
- case 0x6e : /* Store Byte, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (StoreByte(state,instr,lhs))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
- case 0x6f : /* Load Byte, WriteBack, Post Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- lhs = LHS ;
- state->NtransSig = LOW ;
- if (LoadByte(state,instr,lhs,LUNSIGNED))
- LSBase = lhs + LSRegRHS ;
- state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
- break ;
-
-
- case 0x70 : /* Store Word, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreWord(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x71 : /* Load Word, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadWord(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x72 : /* Store Word, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x73 : /* Load Word, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x74 : /* Store Byte, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreByte(state,instr,LHS - LSRegRHS) ;
- break ;
-
- case 0x75 : /* Load Byte, No WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadByte(state,instr,LHS - LSRegRHS,LUNSIGNED) ;
- break ;
-
- case 0x76 : /* Store Byte, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x77 : /* Load Byte, WriteBack, Pre Dec, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS - LSRegRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
-
- case 0x78 : /* Store Word, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreWord(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x79 : /* Load Word, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadWord(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x7a : /* Store Word, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (StoreWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7b : /* Load Word, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (LoadWord(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7c : /* Store Byte, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)StoreByte(state,instr,LHS + LSRegRHS) ;
- break ;
-
- case 0x7d : /* Load Byte, No WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- (void)LoadByte(state,instr,LHS + LSRegRHS,LUNSIGNED) ;
- break ;
-
- case 0x7e : /* Store Byte, WriteBack, Pre Inc, Reg */
- if (BIT(4)) {
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (StoreByte(state,instr,temp))
- LSBase = temp ;
- break ;
-
- case 0x7f : /* Load Byte, WriteBack, Pre Inc, Reg */
- if (BIT(4))
- {
- /* Check for the special breakpoint opcode.
- This value should correspond to the value defined
- as ARM_BE_BREAKPOINT in gdb/arm-tdep.c. */
- if (BITS (0,19) == 0xfdefe)
- {
- if (! ARMul_OSHandleSWI (state, SWI_Breakpoint))
- ARMul_Abort (state, ARMul_SWIV);
- }
- else
- ARMul_UndefInstr(state,instr) ;
- break ;
- }
- UNDEF_LSRBaseEQOffWb ;
- UNDEF_LSRBaseEQDestWb ;
- UNDEF_LSRPCBaseWb ;
- UNDEF_LSRPCOffWb ;
- temp = LHS + LSRegRHS ;
- if (LoadByte(state,instr,temp,LUNSIGNED))
- LSBase = temp ;
- break ;
+ case 0x60: /* Store Word, No WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ break;
+
+ case 0x61: /* Load Word, No WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ break;
+
+ case 0x62: /* Store Word, WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x63: /* Load Word, WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ break;
+
+ case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs - LSRegRHS;
+ break;
+
+ case 0x66: /* Store Byte, WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs - LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x67: /* Load Byte, WriteBack, Post Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs - LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x68: /* Store Word, No WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ break;
+
+ case 0x69: /* Load Word, No WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ break;
+
+ case 0x6a: /* Store Word, WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreWord (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x6b: /* Load Word, WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadWord (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ break;
+
+ case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs + LSRegRHS;
+ break;
+
+ case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (StoreByte (state, instr, lhs))
+ LSBase = lhs + LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+ case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ lhs = LHS;
+ state->NtransSig = LOW;
+ if (LoadByte (state, instr, lhs, LUNSIGNED))
+ LSBase = lhs + LSRegRHS;
+ state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
+ break;
+
+
+ case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) StoreWord (state, instr, LHS - LSRegRHS);
+ break;
+
+ case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) LoadWord (state, instr, LHS - LSRegRHS);
+ break;
+
+ case 0x72: /* Store Word, WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS - LSRegRHS;
+ if (StoreWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x73: /* Load Word, WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS - LSRegRHS;
+ if (LoadWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) StoreByte (state, instr, LHS - LSRegRHS);
+ break;
+
+ case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED);
+ break;
+
+ case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS - LSRegRHS;
+ if (StoreByte (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS - LSRegRHS;
+ if (LoadByte (state, instr, temp, LUNSIGNED))
+ LSBase = temp;
+ break;
+
+ case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) StoreWord (state, instr, LHS + LSRegRHS);
+ break;
+
+ case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) LoadWord (state, instr, LHS + LSRegRHS);
+ break;
+
+ case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS + LSRegRHS;
+ if (StoreWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS + LSRegRHS;
+ if (LoadWord (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) StoreByte (state, instr, LHS + LSRegRHS);
+ break;
+
+ case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ (void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED);
+ break;
+
+ case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS + LSRegRHS;
+ if (StoreByte (state, instr, temp))
+ LSBase = temp;
+ break;
+
+ case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg */
+ if (BIT (4))
+ {
+ /* Check for the special breakpoint opcode.
+ This value should correspond to the value defined
+ as ARM_BE_BREAKPOINT in gdb/arm-tdep.c. */
+ if (BITS (0, 19) == 0xfdefe)
+ {
+ if (!ARMul_OSHandleSWI (state, SWI_Breakpoint))
+ ARMul_Abort (state, ARMul_SWIV);
+ }
+ else
+ ARMul_UndefInstr (state, instr);
+ break;
+ }
+ UNDEF_LSRBaseEQOffWb;
+ UNDEF_LSRBaseEQDestWb;
+ UNDEF_LSRPCBaseWb;
+ UNDEF_LSRPCOffWb;
+ temp = LHS + LSRegRHS;
+ if (LoadByte (state, instr, temp, LUNSIGNED))
+ LSBase = temp;
+ break;