- temp = state->Reg[15] ;
- else
- temp = R15PC | ECC | ER15INT | EMODE ;
-
- switch (vector) {
- case ARMul_ResetV : /* RESET */
- state->Spsr[SVCBANK] = CPSR ;
- SETABORT(INTBITS,state->prog32Sig?SVC32MODE:SVC26MODE) ;
- ARMul_CPSRAltered(state) ;
- state->Reg[14] = temp ;
- break ;
- case ARMul_UndefinedInstrV : /* Undefined Instruction */
- state->Spsr[state->prog32Sig?UNDEFBANK:SVCBANK] = CPSR ;
- SETABORT(IBIT,state->prog32Sig?UNDEF32MODE:SVC26MODE) ;
- ARMul_CPSRAltered(state) ;
- state->Reg[14] = temp - 4 ;
- break ;
- case ARMul_SWIV : /* Software Interrupt */
- state->Spsr[SVCBANK] = CPSR ;
- SETABORT(IBIT,state->prog32Sig?SVC32MODE:SVC26MODE) ;
- ARMul_CPSRAltered(state) ;
- state->Reg[14] = temp - 4 ;
- break ;
- case ARMul_PrefetchAbortV : /* Prefetch Abort */
- state->AbortAddr = 1 ;
- state->Spsr[state->prog32Sig?ABORTBANK:SVCBANK] = CPSR ;
- SETABORT(IBIT,state->prog32Sig?ABORT32MODE:SVC26MODE) ;
- ARMul_CPSRAltered(state) ;
- state->Reg[14] = temp - 4 ;
- break ;
- case ARMul_DataAbortV : /* Data Abort */
- state->Spsr[state->prog32Sig?ABORTBANK:SVCBANK] = CPSR ;
- SETABORT(IBIT,state->prog32Sig?ABORT32MODE:SVC26MODE) ;
- ARMul_CPSRAltered(state) ;
- state->Reg[14] = temp - 4 ; /* the PC must have been incremented */
- break ;
- case ARMul_AddrExceptnV : /* Address Exception */
- state->Spsr[SVCBANK] = CPSR ;
- SETABORT(IBIT,SVC26MODE) ;
- ARMul_CPSRAltered(state) ;
- state->Reg[14] = temp - 4 ;
- break ;
- case ARMul_IRQV : /* IRQ */
- state->Spsr[IRQBANK] = CPSR ;
- SETABORT(IBIT,state->prog32Sig?IRQ32MODE:IRQ26MODE) ;
- ARMul_CPSRAltered(state) ;
- state->Reg[14] = temp - 4 ;
- break ;
- case ARMul_FIQV : /* FIQ */
- state->Spsr[FIQBANK] = CPSR ;
- SETABORT(INTBITS,state->prog32Sig?FIQ32MODE:FIQ26MODE) ;
- ARMul_CPSRAltered(state) ;
- state->Reg[14] = temp - 4 ;
- break ;
+ temp = state->Reg[15];
+ else
+ temp = R15PC | ECC | ER15INT | EMODE;
+
+ switch (vector)
+ {
+ case ARMul_ResetV: /* RESET */
+ SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0);
+ break;
+ case ARMul_UndefinedInstrV: /* Undefined Instruction */
+ SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize);
+ break;
+ case ARMul_SWIV: /* Software Interrupt */
+ SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize);
+ break;
+ case ARMul_PrefetchAbortV: /* Prefetch Abort */
+ state->AbortAddr = 1;
+ SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize);
+ break;
+ case ARMul_DataAbortV: /* Data Abort */
+ SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size);
+ break;
+ case ARMul_AddrExceptnV: /* Address Exception */
+ SETABORT (IBIT, SVC26MODE, isize);
+ break;
+ case ARMul_IRQV: /* IRQ */
+ if ( ! state->is_XScale
+ || ! state->CPRead[13] (state, 0, & temp)
+ || (temp & ARMul_CP13_R0_IRQ))
+ SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
+ break;
+ case ARMul_FIQV: /* FIQ */
+ if ( ! state->is_XScale
+ || ! state->CPRead[13] (state, 0, & temp)
+ || (temp & ARMul_CP13_R0_FIQ))
+ SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
+ break;
+ }
+ if (ARMul_MODE32BIT)
+ ARMul_SetR15 (state, vector);
+ else
+ ARMul_SetR15 (state, R15CCINTMODE | vector);
+
+ if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0)
+ {
+ /* No vector has been installed. Rather than simulating whatever
+ random bits might happen to be at address 0x20 onwards we elect
+ to stop. */
+ switch (vector)
+ {
+ case ARMul_ResetV: state->EndCondition = RDIError_Reset; break;
+ case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break;
+ case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break;
+ case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break;
+ case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break;
+ case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break;
+ case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break;
+ case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break;
+ default: break;
+ }
+ state->Emulate = FALSE;