Remove i386_elf_emit_arch_note

[deliverable/binutils-gdb.git] / sim / arm / armos.c

diff --git a/sim/arm/armos.c b/sim/arm/armos.c
index 4635932b497af395b1df33e8e312e98299c806aa..e5c218d0c6f4069f8a89c755daf96fbc0787700f 100644 (file)
--- a/sim/arm/armos.c
+++ b/sim/arm/armos.c
@@ -3,7 +3,7 @@
  
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
  
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by

-    the Free Software Foundation; either version 2 of the License, or
+    the Free Software Foundation; either version 3 of the License, or

     (at your option) any later version.
  
     This program is distributed in the hope that it will be useful,
     (at your option) any later version.
  
     This program is distributed in the hope that it will be useful,


@@ -12,8 +12,7 @@
     GNU General Public License for more details.
  
     You should have received a copy of the GNU General Public License
     GNU General Public License for more details.
  
     You should have received a copy of the GNU General Public License

-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+    along with this program; if not, see <http://www.gnu.org/licenses/>. */

 
 /* This file contains a model of Demon, ARM Ltd's Debug Monitor,
    including all the SWI's required to support the C library. The code in
 
 /* This file contains a model of Demon, ARM Ltd's Debug Monitor,
    including all the SWI's required to support the C library. The code in


@@ -27,24 +26,12 @@
 
 #include <time.h>
 #include <errno.h>
 
 #include <time.h>
 #include <errno.h>

+#include <limits.h>

 #include <string.h>
 #include <string.h>

-#include <fcntl.h>
+#include "targ-vals.h"

 
 

-#ifndef O_RDONLY
-#define O_RDONLY 0
-#endif
-#ifndef O_WRONLY
-#define O_WRONLY 1
-#endif
-#ifndef O_RDWR
-#define O_RDWR   2
-#endif
-#ifndef O_BINARY
-#define O_BINARY 0
-#endif
-
-#ifdef __STDC__
-#define unlink(s) remove(s)
+#ifndef TARGET_O_BINARY
+#define TARGET_O_BINARY 0

 #endif
 
 #ifdef HAVE_UNISTD_H
 #endif
 
 #ifdef HAVE_UNISTD_H


@@ -83,7 +70,7 @@ extern int _fisatty (FILE *);
 /* For RDIError_BreakpointReached.  */
 #include "dbg_rdi.h"
 
 /* For RDIError_BreakpointReached.  */
 #include "dbg_rdi.h"
 

-#include "callback.h"
+#include "gdb/callback.h"

 extern host_callback *sim_callback;
 
 extern unsigned ARMul_OSInit       (ARMul_State *);
 extern host_callback *sim_callback;
 
 extern unsigned ARMul_OSInit       (ARMul_State *);


@@ -98,6 +85,9 @@ extern ARMword  ARMul_Debug        (ARMul_State *, ARMword, ARMword);
 #define FOPEN_MAX 64
 #endif
 #define UNIQUETEMPS 256
 #define FOPEN_MAX 64
 #endif
 #define UNIQUETEMPS 256

+#ifndef PATH_MAX
+#define PATH_MAX 1024
+#endif

 
 /* OS private Information.  */
 
 
 /* OS private Information.  */
 


@@ -131,8 +121,11 @@ unsigned int swi_mask = -1;
 
 static ARMword softvectorcode[] =
 {
 
 static ARMword softvectorcode[] =
 {

-  /* Basic: swi tidyexception + event; mov pc, lr;
-     ldmia r11,{r11,pc}; swi generateexception  + event.  */
+  /* Installed instructions:
+       swi    tidyexception + event;
+       mov    lr, pc;
+       ldmia  fp, {fp, pc};
+       swi    generateexception  + event.  */

   0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
   0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
   0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */
   0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
   0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
   0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */


@@ -205,11 +198,15 @@ ARMul_OSInit (ARMul_State * state)
     /* Copy the code.  */
     ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
 
     /* Copy the code.  */
     ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
 

+  /* Scan backwards from the end of the code.  */

   for (i = FPESTART + fpesize;; i -= 4)
     {
   for (i = FPESTART + fpesize;; i -= 4)
     {

-      /* Reverse the error strings.  */
+      /* When we reach the marker value, break out of
+        the loop, leaving i pointing at the maker.  */

       if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
        break;
       if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
        break;

+
+      /* If necessary, reverse the error strings.  */

       if (state->bigendSig && j < 0x80000000)
        {
          /* It's part of the string so swap it.  */
       if (state->bigendSig && j < 0x80000000)
        {
          /* It's part of the string so swap it.  */


@@ -221,9 +218,9 @@ ARMul_OSInit (ARMul_State * state)
     }
 
   /* Copy old illegal instr vector.  */
     }
 
   /* Copy old illegal instr vector.  */

-  ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, 4));
+  ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV));

   /* Install new vector.  */
   /* Install new vector.  */

-  ARMul_WriteWord (state, 4, FPENEWVECT (ARMul_ReadWord (state, i - 4)));
+  ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4)));

   ARMul_ConsolePrint (state, ", FPE");
 
 /* #endif  ASIM */
   ARMul_ConsolePrint (state, ", FPE");
 
 /* #endif  ASIM */


@@ -253,18 +250,18 @@ ARMword ARMul_OSLastErrorP (ARMul_State * state)
 
 static int translate_open_mode[] =
 {
 
 static int translate_open_mode[] =
 {

-  O_RDONLY,                    /* "r"   */
-  O_RDONLY + O_BINARY,         /* "rb"  */
-  O_RDWR,                      /* "r+"  */
-  O_RDWR + O_BINARY,           /* "r+b" */
-  O_WRONLY + O_CREAT + O_TRUNC,        /* "w"   */
-  O_WRONLY + O_BINARY + O_CREAT + O_TRUNC,     /* "wb"  */
-  O_RDWR + O_CREAT + O_TRUNC,  /* "w+"  */
-  O_RDWR + O_BINARY + O_CREAT + O_TRUNC,       /* "w+b" */
-  O_WRONLY + O_APPEND + O_CREAT,       /* "a"   */
-  O_WRONLY + O_BINARY + O_APPEND + O_CREAT,    /* "ab"  */
-  O_RDWR + O_APPEND + O_CREAT, /* "a+"  */
-  O_RDWR + O_BINARY + O_APPEND + O_CREAT       /* "a+b" */
+  TARGET_O_RDONLY,             /* "r"   */
+  TARGET_O_RDONLY + TARGET_O_BINARY,   /* "rb"  */
+  TARGET_O_RDWR,               /* "r+"  */
+  TARGET_O_RDWR + TARGET_O_BINARY,             /* "r+b" */
+  TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC,   /* "w"   */
+  TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "wb"  */
+  TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC,     /* "w+"  */
+  TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC,   /* "w+b" */
+  TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT,  /* "a"   */
+  TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT,        /* "ab"  */
+  TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT,    /* "a+"  */
+  TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT   /* "a+b" */

 };
 
 static void
 };
 
 static void


@@ -274,7 +271,13 @@ SWIWrite0 (ARMul_State * state, ARMword addr)
   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 
   while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)
   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 
   while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)

-    (void) sim_callback->write_stdout (sim_callback, (char *) &temp, 1);
+    {
+      char buffer = temp;
+      /* Note - we cannot just cast 'temp' to a (char *) here,
+        since on a big-endian host the byte value will end
+        up in the wrong place and a nul character will be printed.  */
+      (void) sim_callback->write_stdout (sim_callback, & buffer, 1);
+    }

 
   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 }
 
   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 }


@@ -295,31 +298,44 @@ WriteCommandLineTo (ARMul_State * state, ARMword addr)
   while (temp != 0);
 }
 
   while (temp != 0);
 }
 

+static int
+ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n)
+{
+  struct OSblock *OSptr = (struct OSblock *) state->OSptr;
+  char *p = buf;
+
+  while (n--)
+    if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0')
+      return 0;
+  OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG);
+  state->Reg[0] = -1;
+  return -1;
+}
+

 static void
 SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
 {
   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
 static void
 SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
 {
   struct OSblock *OSptr = (struct OSblock *) state->OSptr;

-  char dummy[2000];
+  char buf[PATH_MAX];

   int flags;
   int flags;

-  int i;

 
 

-  for (i = 0; (dummy[i] = ARMul_SafeReadByte (state, name + i)); i++)
-    ;
+  if (ReadFileName (state, buf, name, sizeof buf) == -1)
+    return;

 
   /* Now we need to decode the Demon open mode.  */
   flags = translate_open_mode[SWIflags];
 
   /* Filename ":tt" is special: it denotes stdin/out.  */
 
   /* Now we need to decode the Demon open mode.  */
   flags = translate_open_mode[SWIflags];
 
   /* Filename ":tt" is special: it denotes stdin/out.  */

-  if (strcmp (dummy, ":tt") == 0)
+  if (strcmp (buf, ":tt") == 0)

     {
     {

-      if (flags == O_RDONLY)   /* opening tty "r" */
+      if (flags == TARGET_O_RDONLY) /* opening tty "r" */

        state->Reg[0] = 0;      /* stdin */
       else
        state->Reg[0] = 1;      /* stdout */
     }
   else
     {
        state->Reg[0] = 0;      /* stdin */
       else
        state->Reg[0] = 1;      /* stdout */
     }
   else
     {

-      state->Reg[0] = sim_callback->open (sim_callback, dummy, flags);
+      state->Reg[0] = sim_callback->open (sim_callback, buf, flags);

       OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
     }
 }
       OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
     }
 }


@@ -384,7 +400,7 @@ SWIflen (ARMul_State * state, ARMword fh)
   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
   ARMword addr;
 
   struct OSblock *OSptr = (struct OSblock *) state->OSptr;
   ARMword addr;
 

-  if (fh == 0 || fh > FOPEN_MAX)
+  if (fh > FOPEN_MAX)

     {
       OSptr->ErrorNo = EBADF;
       state->Reg[0] = -1L;
     {
       OSptr->ErrorNo = EBADF;
       state->Reg[0] = -1L;


@@ -399,6 +415,33 @@ SWIflen (ARMul_State * state, ARMword fh)
   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 }
 
   OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
 }
 

+static void
+SWIremove (ARMul_State * state, ARMword path)
+{
+  char buf[PATH_MAX];
+
+  if (ReadFileName (state, buf, path, sizeof buf) != -1)
+    {
+      struct OSblock *OSptr = (struct OSblock *) state->OSptr;
+      state->Reg[0] = sim_callback->unlink (sim_callback, buf);
+      OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+    }
+}
+
+static void
+SWIrename (ARMul_State * state, ARMword old, ARMword new)
+{
+  char oldbuf[PATH_MAX], newbuf[PATH_MAX];
+
+  if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1
+      && ReadFileName (state, newbuf, new, sizeof newbuf) != -1)
+    {
+      struct OSblock *OSptr = (struct OSblock *) state->OSptr;
+      state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf);
+      OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+    }
+}
+

 /* The emulator calls this routine when a SWI instruction is encuntered.
    The parameter passed is the SWI number (lower 24 bits of the instruction).  */
 
 /* The emulator calls this routine when a SWI instruction is encuntered.
    The parameter passed is the SWI number (lower 24 bits of the instruction).  */
 


@@ -540,6 +583,30 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
       state->Emulate = FALSE;
       break;
 
       state->Emulate = FALSE;
       break;
 

+    case SWI_Remove:
+      if (swi_mask & SWI_MASK_DEMON)
+       SWIremove (state, state->Reg[0]);
+      else
+       unhandled = TRUE;
+      break;
+
+    case SWI_Rename:
+      if (swi_mask & SWI_MASK_DEMON)
+       SWIrename (state, state->Reg[0], state->Reg[1]);
+      else
+       unhandled = TRUE;
+      break;
+
+    case SWI_IsTTY:
+      if (swi_mask & SWI_MASK_DEMON)
+       {
+         state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]);
+         OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+       }
+      else
+       unhandled = TRUE;
+      break;
+

       /* Handle Angel SWIs as well as Demon ones.  */
     case AngelSWI_ARM:
     case AngelSWI_Thumb:
       /* Handle Angel SWIs as well as Demon ones.  */
     case AngelSWI_ARM:
     case AngelSWI_Thumb:


@@ -553,12 +620,16 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
          /* R0 is a reason code.  */
          switch (state->Reg[0])
            {
          /* R0 is a reason code.  */
          switch (state->Reg[0])
            {

+           case -1:
+             /* This can happen when a SWI is interrupted (eg receiving a
+                ctrl-C whilst processing SWIRead()).  The SWI will complete
+                returning -1 in r0 to the caller.  If GDB is then used to
+                resume the system call the reason code will now be -1.  */
+             return TRUE;
+         

              /* Unimplemented reason codes.  */
            case AngelSWI_Reason_ReadC:
              /* Unimplemented reason codes.  */
            case AngelSWI_Reason_ReadC:

-           case AngelSWI_Reason_IsTTY:

            case AngelSWI_Reason_TmpNam:
            case AngelSWI_Reason_TmpNam:

-           case AngelSWI_Reason_Remove:
-           case AngelSWI_Reason_Rename:

            case AngelSWI_Reason_System:
            case AngelSWI_Reason_EnterSVC:
            default:
            case AngelSWI_Reason_System:
            case AngelSWI_Reason_EnterSVC:
            default:


@@ -673,18 +744,62 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
                        ARMul_ReadWord (state, addr + 4),
                        ARMul_ReadWord (state, addr + 8));
              break;
                        ARMul_ReadWord (state, addr + 4),
                        ARMul_ReadWord (state, addr + 8));
              break;

+
+           case AngelSWI_Reason_IsTTY:
+             state->Reg[0] = sim_callback->isatty (sim_callback,
+                                                   ARMul_ReadWord (state, addr));
+             OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+             break;
+
+           case AngelSWI_Reason_Remove:
+             SWIremove (state,
+                        ARMul_ReadWord (state, addr));
+
+           case AngelSWI_Reason_Rename:
+             SWIrename (state,
+                        ARMul_ReadWord (state, addr),
+                        ARMul_ReadWord (state, addr + 4));

            }
        }
       else
        unhandled = TRUE;
       break;
 
            }
        }
       else
        unhandled = TRUE;
       break;
 

-    case 0x90:
-    case 0x91:
-    case 0x92:
-      /* These are used by the FPE code.  */
+      /* The following SWIs are generated by the softvectorcode[]
+        installed by default by the simulator.  */
+    case 0x91: /* Undefined Instruction.  */
+      {
+       ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
+       
+       sim_callback->printf_filtered
+         (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x.  Stopping.\n",
+          ARMul_ReadWord (state, addr), addr);
+       state->EndCondition = RDIError_SoftwareInterrupt;
+       state->Emulate = FALSE;
+       return FALSE;
+      }      
+
+    case 0x90: /* Reset.  */
+    case 0x92: /* SWI.  */
+      /* These two can be safely ignored.  */

       break;
       break;

-      
+
+    case 0x93: /* Prefetch Abort.  */
+    case 0x94: /* Data Abort.  */
+    case 0x95: /* Address Exception.  */
+    case 0x96: /* IRQ.  */
+    case 0x97: /* FIQ.  */
+    case 0x98: /* Error.  */
+      unhandled = TRUE;
+      break;
+
+    case -1:
+      /* This can happen when a SWI is interrupted (eg receiving a
+        ctrl-C whilst processing SWIRead()).  The SWI will complete
+        returning -1 in r0 to the caller.  If GDB is then used to
+        resume the system call the reason code will now be -1.  */
+      return TRUE;
+         

     case 0x180001: /* RedBoot's Syscall SWI in ARM mode.  */
       if (swi_mask & SWI_MASK_REDBOOT)
        {
     case 0x180001: /* RedBoot's Syscall SWI in ARM mode.  */
       if (swi_mask & SWI_MASK_REDBOOT)
        {


@@ -743,9 +858,26 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
            case 18: /* Time.  */
              sim_callback->printf_filtered
                (sim_callback,
            case 18: /* Time.  */
              sim_callback->printf_filtered
                (sim_callback,

-                "sim: unhandled RedBoot syscall '%d' encountered - ignoring\n",
+                "sim: unhandled RedBoot syscall `%d' encountered - "
+                "returning ENOSYS\n",

                 state->Reg[0]);
                 state->Reg[0]);

-             return FALSE;
+             state->Reg[0] = -1;
+             OSptr->ErrorNo = cb_host_to_target_errno
+               (sim_callback, ENOSYS);
+             break;
+           case 1001: /* Meminfo. */
+             {
+               ARMword totmem = state->Reg[1],
+                       topmem = state->Reg[2];
+               ARMword stack = state->MemSize > 0
+                 ? state->MemSize : ADDRUSERSTACK;
+               if (totmem != 0)
+                 ARMul_WriteWord (state, totmem, stack);
+               if (topmem != 0)
+                 ARMul_WriteWord (state, topmem, stack);
+               state->Reg[0] = 0;
+               break;
+             }

 
            default:
              sim_callback->printf_filtered
 
            default:
              sim_callback->printf_filtered