-
- unsigned type ;
-
- type = (unsigned)(state->Reg[1] & 3L) ;
- getstring(state,state->Reg[0],buffer) ;
- if (strcmp(buffer,":tt")==0 && (type == O_RDONLY )) /* opening tty "r" */
- fptr = stdin ;
- else if (strcmp(buffer,":tt")==0 && (type == O_WRONLY)) /* opening tty "w" */
- fptr = stderr ;
- else
- {
- switch (type)
- {
- case O_RDONLY:
- fptr = fopen(buffer,"r") ;
- break;
- case O_WRONLY:
- fptr = fopen(buffer,"w") ;
- break;
- case O_RDWR:
- fptr = fopen(buffer,"rw") ;
- break;
- }
- }
-
- state->Reg[0] = 0 ;
- if (fptr != NULL) {
- for (temp = 0 ; temp < FOPEN_MAX ; temp++)
- if (OSptr->FileTable[temp] == NULL) {
- OSptr->FileTable[temp] = fptr ;
- OSptr->FileFlags[temp] = type & 1 ; /* preserve the binary bit */
- state->Reg[0] = (ARMword)(temp + 1) ;
- break ;
- }
- if (state->Reg[0] == 0)
- OSptr->ErrorNo = EMFILE ; /* too many open files */
- else
- OSptr->ErrorNo = errno ;
- }
- else
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_Close :
- temp = state->Reg[0] ;
- if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- temp-- ;
- fptr = OSptr->FileTable[temp] ;
- if (fptr == stdin || fptr == stderr)
- state->Reg[0] = 0 ;
- else
- state->Reg[0] = fclose(fptr) ;
- OSptr->FileTable[temp] = NULL ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Write : {
- unsigned size, upto, type ;
- char ch ;
-
- temp = state->Reg[0] ;
- if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- temp-- ;
- fptr = OSptr->FileTable[temp] ;
- type = OSptr->FileFlags[temp] ;
- addr = state->Reg[1] ;
- size = (unsigned)state->Reg[2] ;
-
- if (type & READOP)
- fseek(fptr,0L,SEEK_CUR) ;
- OSptr->FileFlags[temp] = (type & BINARY) | WRITEOP ; ;
- while (size > 0) {
- if (size >= BUFFERSIZE)
- upto = BUFFERSIZE ;
- else
- upto = size ;
- for (cptr = buffer ; (cptr - buffer) < upto ; cptr++) {
- ch = (char)ARMul_ReadByte(state,(ARMword)addr++) ;
- *cptr = FIXCRLF(type,ch) ;
- }
- temp = fwrite(buffer,1,upto,fptr) ;
- if (temp < upto) {
- state->Reg[0] = (ARMword)(size - temp) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
- size -= upto ;
- }
- state->Reg[0] = 0 ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_Read : {
- unsigned size, upto, type ;
- char ch ;
-
- temp = state->Reg[0] ;
- if (temp == 0 || temp > FOPEN_MAX || OSptr->FileTable[temp - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- temp-- ;
- fptr = OSptr->FileTable[temp] ;
- addr = state->Reg[1] ;
- size = (unsigned)state->Reg[2] ;
- type = OSptr->FileFlags[temp] ;
-
- if (type & WRITEOP)
- fseek(fptr,0L,SEEK_CUR) ;
- OSptr->FileFlags[temp] = (type & BINARY) | READOP ; ;
- while (size > 0) {
- if (isatty_(fptr)) {
- upto = (size >= BUFFERSIZE)?BUFFERSIZE:size + 1 ;
- if (fgets(buffer, upto, fptr) != 0)
- temp = strlen(buffer) ;
- else
- temp = 0 ;
- upto-- ; /* 1 char used for terminating null */
- }
- else {
- upto = (size>=BUFFERSIZE)?BUFFERSIZE:size ;
- temp = fread(buffer,1,upto,fptr) ;
- }
- for (cptr = buffer ; (cptr - buffer) < temp ; cptr++) {
- ch = *cptr ;
- ARMul_WriteByte(state,(ARMword)addr++,FIXCRLF(type,ch)) ;
- }
- if (temp < upto) {
- state->Reg[0] = (ARMword)(size - temp) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
- size -= upto ;
- }
- state->Reg[0] = 0 ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_Seek :
- if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX
- || OSptr->FileTable[state->Reg[0] - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- fptr = OSptr->FileTable[state->Reg[0] - 1] ;
- state->Reg[0] = fseek(fptr,(long)state->Reg[1],SEEK_SET) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_Flen :
- if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX
- || OSptr->FileTable[state->Reg[0] - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- fptr = OSptr->FileTable[state->Reg[0] - 1] ;
- addr = (ARMword)ftell(fptr) ;
- if (fseek(fptr,0L,SEEK_END) < 0)
- state->Reg[0] = -1 ;
- else {
- state->Reg[0] = (ARMword)ftell(fptr) ;
- (void)fseek(fptr,addr,SEEK_SET) ;
- }
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_IsTTY :
- if (state->Reg[0] == 0 || state->Reg[0] > FOPEN_MAX
- || OSptr->FileTable[state->Reg[0] - 1] == 0) {
- OSptr->ErrorNo = EBADF ;
- state->Reg[0] = -1L ;
- return(TRUE) ;
- }
- fptr = OSptr->FileTable[state->Reg[0] - 1] ;
- state->Reg[0] = isatty_(fptr) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
-
- case SWI_TmpNam :{
- ARMword size ;
-
- addr = state->Reg[0] ;
- temp = state->Reg[1] & 0xff ;
- size = state->Reg[2] ;
- if (OSptr->tempnames[temp] == NULL) {
- if ((OSptr->tempnames[temp] = malloc(L_tmpnam)) == NULL) {
- state->Reg[0] = 0 ;
- return(TRUE) ;
- }
- (void)tmpnam(OSptr->tempnames[temp]) ;
- }
- cptr = OSptr->tempnames[temp] ;
- if (strlen(cptr) > state->Reg[2])
- state->Reg[0] = 0 ;
- else
- do {
- ARMul_WriteByte(state,addr++,*cptr) ;
- } while (*cptr++ != 0) ;
- OSptr->ErrorNo = errno ;
- return(TRUE) ;
- }
-
- case SWI_InstallHandler:
- { ARMword handlerp = ADDRSOFHANDLERS + state->Reg[0] * 8;
- ARMword oldr1 = ARMul_ReadWord(state, handlerp),
- oldr2 = ARMul_ReadWord(state, handlerp + 4);
- ARMul_WriteWord(state, handlerp, state->Reg[1]);
- ARMul_WriteWord(state, handlerp + 4, state->Reg[2]);
- state->Reg[1] = oldr1;
- state->Reg[2] = oldr2;
- return(TRUE);
- }
-
- case SWI_GenerateError:
- ARMul_Abort(state, ARMSWIV) ;
- if (state->Emulate)
- ARMul_SetR15(state, ARMul_ReadWord(state, ADDRSOFTVECTORS + ARMErrorV));
- return(TRUE);
-
-/* SWI's 0x9x unwind the state of the CPU after an abort of type x */
-
- case 0x90: /* Branch through zero */
- { ARMword oldpsr = ARMul_GetCPSR(state) ;
- ARMul_SetCPSR(state, (oldpsr & 0xffffffc0) | 0x13) ;
- ARMul_SetSPSR(state, SVC32MODE, oldpsr) ;
- state->Reg[14] = 0;
- goto TidyCommon;
- }
-
- case 0x98: /* Error */
- { ARMword errorp = state->Reg[0],
- regp = state->Reg[1];
- unsigned i;
- ARMword errorpsr = ARMul_ReadWord(state, regp + 16*4);
- for (i = 0; i < 15; i++)
- ARMul_SetReg(state,errorpsr,i,ARMul_ReadWord(state, regp + i*4L)) ;
- state->Reg[14] = ARMul_ReadWord(state, regp + 15*4L);
- state->Reg[10] = errorp;
- ARMul_SetSPSR(state,state->Mode,errorpsr) ;
- OSptr->ErrorP = errorp;
- goto TidyCommon;
- }
-
- case 0x94: /* Data abort */
- { ARMword addr = state->Reg[14] - 8;
- ARMword cpsr = ARMul_GetCPSR(state) ;
- if (ARM26BITMODE)
- addr = addr & 0x3fffffc ;
- ARMul_SetCPSR(state,ARMul_GetSPSR(state,cpsr)) ;
- UnwindDataAbort(state, addr);
- if (addr >= FPESTART && addr < FPEEND) { /* in the FPE */
- ARMword sp, spsr ;
- unsigned i ;
-
- sp = state->Reg[13] ;
- state->Reg[13] += 64 ; /* fix the aborting mode sp */
- state->Reg[14] = ARMul_ReadWord(state,sp + 60) ; /* and its lr */
- spsr = ARMul_GetSPSR(state,state->Mode) ;
- state->Mode = ARMul_SwitchMode(state, state->Mode, spsr);
- for (i = 0 ; i < 15 ; i++) {
- ARMul_SetReg(state,spsr,i,ARMul_ReadWord(state,sp)) ;
- sp += 4 ;
- }
- ARMul_SetCPSR(state,cpsr) ;
- state->Reg[14] = ARMul_ReadWord(state,sp) + 4 ; /* botch it */
- ARMul_SetSPSR(state,state->Mode,spsr) ;
- }
- else
- ARMul_SetCPSR(state,cpsr) ;
-
- /* and fall through to correct r14 */
- }
- case 0x95: /* Address Exception */
- state->Reg[14] -= 4;
- case 0x91: /* Undefined instruction */
- case 0x92: /* SWI */
- case 0x93: /* Prefetch abort */
- case 0x96: /* IRQ */
- case 0x97: /* FIQ */
- state->Reg[14] -= 4;
- TidyCommon:
- if (state->VectorCatch & (1 << (number - 0x90))) {
- ARMul_SetR15(state, state->Reg[14] + 8) ; /* the 8 is the pipelining the the RDI will undo */
- ARMul_SetCPSR(state,ARMul_GetSPSR(state,ARMul_GetCPSR(state))) ;
- if (number == 0x90)
- state->EndCondition = 10 ; /* Branch through Zero Error */
- else
- state->EndCondition = (unsigned)number - 0x8f;
- state->Emulate = FALSE ;
- }
- else {
- ARMword sp = state->Reg[13];
- ARMul_WriteWord(state, sp - 4, state->Reg[14]);
- ARMul_WriteWord(state, sp - 8, state->Reg[12]);
- ARMul_WriteWord(state, sp - 12, state->Reg[11]);
- ARMul_WriteWord(state, sp - 16, state->Reg[10]);
- state->Reg[13] = sp - 16;
- state->Reg[11] = ADDRSOFHANDLERS + 8 * (number - 0x90);
- }
- return(TRUE);
-
-/* SWI's 0x8x pass an abort of type x to the debugger if a handler returns */
-
- case 0x80: case 0x81: case 0x82: case 0x83:
- case 0x84: case 0x85: case 0x86: case 0x87: case 0x88:
- { ARMword sp = state->Reg[13];
- state->Reg[10] = ARMul_ReadWord(state, sp);
- state->Reg[11] = ARMul_ReadWord(state, sp + 4);
- state->Reg[12] = ARMul_ReadWord(state, sp + 8);
- state->Reg[14] = ARMul_ReadWord(state, sp + 12);
- state->Reg[13] = sp + 16;
- ARMul_SetR15(state, state->Reg[14] + 8) ; /* the 8 is the pipelining the the RDI will undo */
- ARMul_SetCPSR(state,ARMul_GetSPSR(state,ARMul_GetCPSR(state))) ;
- if (number == 0x80)
- state->EndCondition = 10 ; /* Branch through Zero Error */
- else
- state->EndCondition = (unsigned)number - 0x7f;
- state->Emulate = FALSE ;
- return(TRUE);
- }
-
- default :
- state->Emulate = FALSE ;
- return(FALSE) ;
+ OSptr->ErrorNo = errno;
+ break;
+
+ case AngelSWI_Reason_Time:
+ state->Reg[0] = (ARMword) sim_callback->time (sim_callback, NULL);
+ OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+ break;
+
+ case AngelSWI_Reason_WriteC:
+ {
+ char tmp = ARMul_SafeReadByte (state, addr);
+ (void) sim_callback->write_stdout (sim_callback, &tmp, 1);
+ OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+ break;
+ }
+
+ case AngelSWI_Reason_Write0:
+ SWIWrite0 (state, addr);
+ break;
+
+ case AngelSWI_Reason_Close:
+ state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr));
+ OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+ break;
+
+ case AngelSWI_Reason_Seek:
+ state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4),
+ SEEK_SET);
+ OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+ break;
+
+ case AngelSWI_Reason_FLen:
+ SWIflen (state, ARMul_ReadWord (state, addr));
+ break;
+
+ case AngelSWI_Reason_GetCmdLine:
+ WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
+ break;
+
+ case AngelSWI_Reason_HeapInfo:
+ /* R1 is a pointer to a pointer. */
+ addr = ARMul_ReadWord (state, addr);
+
+ /* Pick up the right memory limit. */
+ if (state->MemSize)
+ temp = state->MemSize;
+ else
+ temp = ADDRUSERSTACK;
+
+ ARMul_WriteWord (state, addr, 0); /* Heap base. */
+ ARMul_WriteWord (state, addr + 4, temp); /* Heap limit. */
+ ARMul_WriteWord (state, addr + 8, temp); /* Stack base. */
+ ARMul_WriteWord (state, addr + 12, temp); /* Stack limit. */
+ break;
+
+ case AngelSWI_Reason_ReportException:
+ if (state->Reg[1] == ADP_Stopped_ApplicationExit)
+ state->Reg[0] = 0;
+ else
+ state->Reg[0] = -1;
+ state->Emulate = FALSE;
+ break;
+
+ case ADP_Stopped_ApplicationExit:
+ state->Reg[0] = 0;
+ state->Emulate = FALSE;
+ break;
+
+ case ADP_Stopped_RunTimeError:
+ state->Reg[0] = -1;
+ state->Emulate = FALSE;
+ break;
+
+ case AngelSWI_Reason_Errno:
+ state->Reg[0] = OSptr->ErrorNo;
+ break;
+
+ case AngelSWI_Reason_Open:
+ SWIopen (state,
+ ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4));
+ break;
+
+ case AngelSWI_Reason_Read:
+ SWIread (state,
+ ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4),
+ ARMul_ReadWord (state, addr + 8));
+ break;
+
+ case AngelSWI_Reason_Write:
+ SWIwrite (state,
+ ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4),
+ ARMul_ReadWord (state, addr + 8));
+ break;
+
+ case AngelSWI_Reason_IsTTY:
+ state->Reg[0] = sim_callback->isatty (sim_callback,
+ ARMul_ReadWord (state, addr));
+ OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+ break;
+
+ case AngelSWI_Reason_Remove:
+ SWIremove (state,
+ ARMul_ReadWord (state, addr));
+
+ case AngelSWI_Reason_Rename:
+ SWIrename (state,
+ ARMul_ReadWord (state, addr),
+ ARMul_ReadWord (state, addr + 4));
+ }
+ }
+ else
+ unhandled = TRUE;
+ break;
+
+ /* The following SWIs are generated by the softvectorcode[]
+ installed by default by the simulator. */
+ case 0x91: /* Undefined Instruction. */
+ {
+ ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
+
+ sim_callback->printf_filtered
+ (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n",
+ ARMul_ReadWord (state, addr), addr);
+ state->EndCondition = RDIError_SoftwareInterrupt;
+ state->Emulate = FALSE;
+ return FALSE;
+ }
+
+ case 0x90: /* Reset. */
+ case 0x92: /* SWI. */
+ /* These two can be safely ignored. */
+ break;
+
+ case 0x93: /* Prefetch Abort. */
+ case 0x94: /* Data Abort. */
+ case 0x95: /* Address Exception. */
+ case 0x96: /* IRQ. */
+ case 0x97: /* FIQ. */
+ case 0x98: /* Error. */
+ unhandled = TRUE;
+ break;
+
+ case -1:
+ /* This can happen when a SWI is interrupted (eg receiving a
+ ctrl-C whilst processing SWIRead()). The SWI will complete
+ returning -1 in r0 to the caller. If GDB is then used to
+ resume the system call the reason code will now be -1. */
+ return TRUE;
+
+ case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */
+ if (swi_mask & SWI_MASK_REDBOOT)
+ {
+ switch (state->Reg[0])
+ {
+ /* These numbers are defined in libgloss/syscall.h
+ but the simulator should not be dependend upon
+ libgloss being installed. */
+ case 1: /* Exit. */
+ state->Emulate = FALSE;
+ /* Copy exit code into r0. */
+ state->Reg[0] = state->Reg[1];
+ break;
+
+ case 2: /* Open. */
+ SWIopen (state, state->Reg[1], state->Reg[2]);
+ break;
+
+ case 3: /* Close. */
+ state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]);
+ OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+ break;
+
+ case 4: /* Read. */
+ SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]);
+ break;
+
+ case 5: /* Write. */
+ SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]);
+ break;
+
+ case 6: /* Lseek. */
+ state->Reg[0] = sim_callback->lseek (sim_callback,
+ state->Reg[1],
+ state->Reg[2],
+ state->Reg[3]);
+ OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+ break;
+
+ case 17: /* Utime. */
+ state->Reg[0] = (ARMword) sim_callback->time (sim_callback,
+ (long *) state->Reg[1]);
+ OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
+ break;
+
+ case 7: /* Unlink. */
+ case 8: /* Getpid. */
+ case 9: /* Kill. */
+ case 10: /* Fstat. */
+ case 11: /* Sbrk. */
+ case 12: /* Argvlen. */
+ case 13: /* Argv. */
+ case 14: /* ChDir. */
+ case 15: /* Stat. */
+ case 16: /* Chmod. */
+ case 18: /* Time. */
+ sim_callback->printf_filtered
+ (sim_callback,
+ "sim: unhandled RedBoot syscall `%d' encountered - "
+ "returning ENOSYS\n",
+ state->Reg[0]);
+ state->Reg[0] = -1;
+ OSptr->ErrorNo = cb_host_to_target_errno
+ (sim_callback, ENOSYS);
+ break;
+ case 1001: /* Meminfo. */
+ {
+ ARMword totmem = state->Reg[1],
+ topmem = state->Reg[2];
+ ARMword stack = state->MemSize > 0
+ ? state->MemSize : ADDRUSERSTACK;
+ if (totmem != 0)
+ ARMul_WriteWord (state, totmem, stack);
+ if (topmem != 0)
+ ARMul_WriteWord (state, topmem, stack);
+ state->Reg[0] = 0;
+ break;
+ }
+
+ default:
+ sim_callback->printf_filtered
+ (sim_callback,
+ "sim: unknown RedBoot syscall '%d' encountered - ignoring\n",
+ state->Reg[0]);
+ return FALSE;
+ }
+ break;
+ }
+
+ default:
+ unhandled = TRUE;
+ }
+
+ if (unhandled)
+ {
+ if (SWI_vector_installed)
+ {
+ ARMword cpsr;
+ ARMword i_size;
+
+ cpsr = ARMul_GetCPSR (state);
+ i_size = INSN_SIZE;
+
+ ARMul_SetSPSR (state, SVC32MODE, cpsr);
+
+ cpsr &= ~0xbf;
+ cpsr |= SVC32MODE | 0x80;
+ ARMul_SetCPSR (state, cpsr);
+
+ state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
+ state->NextInstr = RESUME;
+ state->Reg[15] = state->pc = ARMSWIV;
+ FLUSHPIPE;
+ }
+ else
+ {
+ sim_callback->printf_filtered
+ (sim_callback,
+ "sim: unknown SWI encountered - %x - ignoring\n",
+ number);
+ return FALSE;
+ }