+ switch ((enum sim_arm_regs) rn)
+ {
+ case SIM_ARM_R0_REGNUM:
+ case SIM_ARM_R1_REGNUM:
+ case SIM_ARM_R2_REGNUM:
+ case SIM_ARM_R3_REGNUM:
+ case SIM_ARM_R4_REGNUM:
+ case SIM_ARM_R5_REGNUM:
+ case SIM_ARM_R6_REGNUM:
+ case SIM_ARM_R7_REGNUM:
+ case SIM_ARM_R8_REGNUM:
+ case SIM_ARM_R9_REGNUM:
+ case SIM_ARM_R10_REGNUM:
+ case SIM_ARM_R11_REGNUM:
+ case SIM_ARM_R12_REGNUM:
+ case SIM_ARM_R13_REGNUM:
+ case SIM_ARM_R14_REGNUM:
+ case SIM_ARM_R15_REGNUM: /* PC */
+ regval = ARMul_GetReg (state, state->Mode, rn);
+ break;
+
+ case SIM_ARM_FP0_REGNUM:
+ case SIM_ARM_FP1_REGNUM:
+ case SIM_ARM_FP2_REGNUM:
+ case SIM_ARM_FP3_REGNUM:
+ case SIM_ARM_FP4_REGNUM:
+ case SIM_ARM_FP5_REGNUM:
+ case SIM_ARM_FP6_REGNUM:
+ case SIM_ARM_FP7_REGNUM:
+ case SIM_ARM_FPS_REGNUM:
+ memset (memory, 0, length);
+ return 0;
+
+ case SIM_ARM_PS_REGNUM:
+ regval = ARMul_GetCPSR (state);
+ break;
+
+ case SIM_ARM_MAVERIC_COP0R0_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R1_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R2_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R3_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R4_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R5_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R6_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R7_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R8_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R9_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R10_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R11_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R12_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R13_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R14_REGNUM:
+ case SIM_ARM_MAVERIC_COP0R15_REGNUM:
+ memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
+ sizeof (struct maverick_regs));
+ return sizeof (struct maverick_regs);
+
+ case SIM_ARM_MAVERIC_DSPSC_REGNUM:
+ memcpy (memory, & DSPsc, sizeof DSPsc);
+ return sizeof DSPsc;
+
+ case SIM_ARM_IWMMXT_COP0R0_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R1_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R2_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R3_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R4_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R5_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R6_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R7_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R8_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R9_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R10_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R11_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R12_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R13_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R14_REGNUM:
+ case SIM_ARM_IWMMXT_COP0R15_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R0_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R1_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R2_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R3_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R4_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R5_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R6_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R7_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R8_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R9_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R10_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R11_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R12_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R13_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R14_REGNUM:
+ case SIM_ARM_IWMMXT_COP1R15_REGNUM:
+ return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
+
+ default:
+ return 0;
+ }
+
+ while (len)
+ {
+ tomem (state, memory, regval);
+
+ len -= 4;
+ memory += 4;
+ regval = 0;
+ }
+
+ return length;