+void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_MEM_DI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.mem_di_write.address = address;
+ element->kinds.mem_di_write.value = value;
+}
+
+void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_MEM_DF_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.mem_df_write.address = address;
+ element->kinds.mem_df_write.value = value;
+}
+
+void sim_queue_mem_xi_write (SIM_CPU *cpu, SI address, SI *value)
+{
+ CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
+ CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
+ element->kind = CGEN_MEM_XI_WRITE;
+ element->insn_address = CPU_PC_GET (cpu);
+ element->kinds.mem_xi_write.address = address;
+ element->kinds.mem_xi_write.value[0] = value[0];
+ element->kinds.mem_xi_write.value[1] = value[1];
+ element->kinds.mem_xi_write.value[2] = value[2];
+ element->kinds.mem_xi_write.value[3] = value[3];
+}
+