+#endif
+
+
+/* Remove any memory reference related to this address */
+#if EXTERN_SIM_CORE_P
+static void
+sim_core_map_detach (SIM_DESC sd,
+ sim_core_map *access_map,
+ int level,
+ int space,
+ address_word addr)
+{
+ sim_core_mapping **entry;
+ for (entry = &access_map->first;
+ (*entry) != NULL;
+ entry = &(*entry)->next)
+ {
+ if ((*entry)->base == addr
+ && (*entry)->level == level
+ && (*entry)->space == space)
+ {
+ sim_core_mapping *dead = (*entry);
+ (*entry) = dead->next;
+ if (dead->free_buffer != NULL)
+ free (dead->free_buffer);
+ free (dead);
+ return;
+ }
+ }
+}
+#endif
+
+#if EXTERN_SIM_CORE_P
+void
+sim_core_detach (SIM_DESC sd,
+ sim_cpu *cpu,
+ int level,
+ int address_space,
+ address_word addr)
+{
+ sim_core *memory = STATE_CORE (sd);
+ unsigned map;
+ for (map = 0; map < nr_maps; map++)
+ {
+ sim_core_map_detach (sd, &memory->common.map[map],
+ level, address_space, addr);
+ }
+ /* Just copy this update to each of the processor specific data
+ structures. FIXME - later this will be replaced by true
+ processor specific maps. */
+ {
+ int i;
+ for (i = 0; i < MAX_NR_PROCESSORS; i++)
+ {
+ CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
+ }
+ }
+}
+#endif