+Tue Dec 2 15:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_3A00): For "macu", perform multiply stage using 32
+ bit rather than 16 bit precision.
+ (OP_3C00): For "mulxu", store unsigned product in ACC.
+ (OP_3800): For "msbu", subtract unsigned product from ACC,
+
+Tue Dec 2 11:04:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_1000): For "sub2w", compute carry by comparing
+ inputs.
+
+Mon Nov 17 20:57:21 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_1): Use 32 bit unsigned arithmetic for subtract,
+ carry indicated by value > 0xffff.
+
+Fri Nov 14 12:51:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_resume): Don't set up SIGINT handler using signal,
+ handled by client.
+ (sim_resume): Fix race condition of a direct assignment to
+ stop_simulator, conditionally call sim_stop.
+ (sim_stop_reason): Check stop_simulator returning SIGINT. Clear
+ stop_simulator ready for next sim_resume call.
+ (sim_ctrl_c): Delete function.
+
+Thu Nov 13 19:29:34 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_resume): For "REP", only check/update the PC when
+ a branch instruction has not been executed.
+
+Mon Nov 10 17:50:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. Sign
+ extend bit 44 all constants.
+ (OP_4201): Replace GCC specific 0x..LL with SIGNED64 macro.
+
+Fri Oct 24 10:26:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h: Include sim-types.h.
+ (uint8, in816, uiny16, int32, uint32, int64, uint64): Typedef
+ using unsigned8 et.al. from sim-types.h.
+ (SEXT32, SEXT40, SEXT44, SEXT60): Replace GCC specific 0x..LL with
+ SIGNED64 macro.
+
+Wed Oct 22 14:43:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_write_phys): New function, write to physical
+ instead of virtual memory.
+
+ * interp.c (sim_load): Pass lma_p and sim_write_phys to
+ sim_load_file.
+
+Mon Oct 13 10:55:07 1997 Fred Fish <cygnus.com>
+
+ * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and move
+ exception generation code to OP_6E01.
+ (OP_6E01): Change OP_POSTINC to OP_POSTDEC and insert exception
+ generation code.
+
+Sat Oct 11 09:02:08 1997 Fred Fish <fnf@cygnus.com>
+
+ * simops.c (OP_6401): postdecrement on r15 is OK, remove exception.
+ (OP_6601): Ditto.
+
+Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Sep 27 12:51:34 1997 Fred Fish <fnf@cygnus.com>
+
+ * interp.c (pc_addr): Discard upper bit(s) of PC in case
+ IMAP1 selects unified memory.
+ * d10v_sim.h (INC_ADDR): Align MOD_E to increment before testing
+ for end condition.
+
+Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Sep 10 22:30:24 1997 Martin M. Hunt <hunt@cygnus.com>
+
+ * interp.c (sim_resume): Increment PC at end of rep
+ loop.
+
+ * simops.c (OP_4201): Fix rachi instruction.
+
+Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+