+ int size;
+ switch ((enum sim_d10v_regs) rn)
+ {
+ case SIM_D10V_R0_REGNUM:
+ case SIM_D10V_R1_REGNUM:
+ case SIM_D10V_R2_REGNUM:
+ case SIM_D10V_R3_REGNUM:
+ case SIM_D10V_R4_REGNUM:
+ case SIM_D10V_R5_REGNUM:
+ case SIM_D10V_R6_REGNUM:
+ case SIM_D10V_R7_REGNUM:
+ case SIM_D10V_R8_REGNUM:
+ case SIM_D10V_R9_REGNUM:
+ case SIM_D10V_R10_REGNUM:
+ case SIM_D10V_R11_REGNUM:
+ case SIM_D10V_R12_REGNUM:
+ case SIM_D10V_R13_REGNUM:
+ case SIM_D10V_R14_REGNUM:
+ case SIM_D10V_R15_REGNUM:
+ WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM));
+ size = 2;
+ break;
+ case SIM_D10V_CR0_REGNUM:
+ case SIM_D10V_CR1_REGNUM:
+ case SIM_D10V_CR2_REGNUM:
+ case SIM_D10V_CR3_REGNUM:
+ case SIM_D10V_CR4_REGNUM:
+ case SIM_D10V_CR5_REGNUM:
+ case SIM_D10V_CR6_REGNUM:
+ case SIM_D10V_CR7_REGNUM:
+ case SIM_D10V_CR8_REGNUM:
+ case SIM_D10V_CR9_REGNUM:
+ case SIM_D10V_CR10_REGNUM:
+ case SIM_D10V_CR11_REGNUM:
+ case SIM_D10V_CR12_REGNUM:
+ case SIM_D10V_CR13_REGNUM:
+ case SIM_D10V_CR14_REGNUM:
+ case SIM_D10V_CR15_REGNUM:
+ WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM));
+ size = 2;
+ break;
+ case SIM_D10V_A0_REGNUM:
+ case SIM_D10V_A1_REGNUM:
+ WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM));
+ size = 8;
+ break;
+ case SIM_D10V_SPI_REGNUM:
+ /* PSW_SM indicates that the current SP is the USER
+ stack-pointer. */
+ WRITE_16 (memory, spi_register ());
+ size = 2;
+ break;
+ case SIM_D10V_SPU_REGNUM:
+ /* PSW_SM indicates that the current SP is the USER
+ stack-pointer. */
+ WRITE_16 (memory, spu_register ());
+ size = 2;
+ break;
+ case SIM_D10V_IMAP0_REGNUM:
+ case SIM_D10V_IMAP1_REGNUM:
+ WRITE_16 (memory, imap_register (NULL, rn - SIM_D10V_IMAP0_REGNUM));
+ size = 2;
+ break;
+ case SIM_D10V_DMAP0_REGNUM:
+ case SIM_D10V_DMAP1_REGNUM:
+ case SIM_D10V_DMAP2_REGNUM:
+ case SIM_D10V_DMAP3_REGNUM:
+ WRITE_16 (memory, dmap_register (NULL, rn - SIM_D10V_DMAP0_REGNUM));
+ size = 2;
+ break;
+ case SIM_D10V_TS2_DMAP_REGNUM:
+ size = 0;
+ break;
+ default:
+ size = 0;
+ break;
+ }
+ return size;