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For "msbu", subtract unsigned product from ACC,
[deliverable/binutils-gdb.git]
/
sim
/
d10v
/
simops.c
diff --git
a/sim/d10v/simops.c
b/sim/d10v/simops.c
index 222d2d4f67654429ff66398846996854c464d42c..64c8a33f1efef8de4f1d56bb02174b3ec1aa64e4 100644
(file)
--- a/
sim/d10v/simops.c
+++ b/
sim/d10v/simops.c
@@
-1352,13
+1352,17
@@
OP_1A00 ()
void
OP_3A00 ()
{
void
OP_3A00 ()
{
- int64 tmp;
+ uint64 tmp;
+ uint32 src1;
+ uint32 src2;
trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
+ src1 = (uint16) State.regs[OP[1]];
+ src2 = (uint16) State.regs[OP[2]];
+ tmp = src1 * src2;
if (State.FX)
if (State.FX)
- tmp =
SEXT40( (tmp << 1) & MASK40
);
- State.a[OP[0]] = (S
EXT40 (State.a[OP[0]])
+ tmp) & MASK40;
+ tmp =
(tmp << 1
);
+ State.a[OP[0]] = (S
tate.a[OP[0]]
+ tmp) & MASK40;
trace_output (OP_ACCUM);
}
trace_output (OP_ACCUM);
}
@@
-1514,14
+1518,18
@@
OP_1800 ()
void
OP_3800 ()
{
void
OP_3800 ()
{
- int64 tmp;
+ uint64 tmp;
+ uint32 src1;
+ uint32 src2;
trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
+ src1 = (uint16) State.regs[OP[1]];
+ src2 = (uint16) State.regs[OP[2]];
+ tmp = src1 * src2;
if (State.FX)
if (State.FX)
- tmp =
SEXT40( (tmp << 1) & MASK40
);
+ tmp =
(tmp << 1
);
- State.a[OP[0]] = (S
EXT40 (State.a[OP[0]])
- tmp) & MASK40;
+ State.a[OP[0]] = (S
tate.a[OP[0]]
- tmp) & MASK40;
trace_output (OP_ACCUM);
}
trace_output (OP_ACCUM);
}
@@
-1573,11
+1581,14
@@
OP_1C00 ()
void
OP_3C00 ()
{
void
OP_3C00 ()
{
- int64 tmp;
+ uint64 tmp;
+ uint32 src1;
+ uint32 src2;
trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
- tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
-
+ src1 = (uint16) State.regs[OP[1]];
+ src2 = (uint16) State.regs[OP[2]];
+ tmp = src1 * src2;
if (State.FX)
tmp <<= 1;
if (State.FX)
tmp <<= 1;
@@
-2483,7
+2494,7
@@
OP_1000 ()
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits */
tmp = a - b;
/* see ../common/sim-alu.h for a more extensive discussion on how to
compute the carry/overflow bits */
tmp = a - b;
- State.C = (a
<
b);
+ State.C = (a
>=
b);
State.regs[OP[0]] = (tmp >> 16) & 0xffff;
State.regs[OP[0]+1] = tmp & 0xffff;
trace_output (OP_DREG);
State.regs[OP[0]] = (tmp >> 16) & 0xffff;
State.regs[OP[0]+1] = tmp & 0xffff;
trace_output (OP_DREG);
@@
-2585,7
+2596,8
@@
OP_1 ()
trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
/* see ../common/sim-alu.h for a more extensive discussion on how to
- compute the carry/overflow bits */
+ compute the carry/overflow bits. */
+ /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
+ (unsigned)(unsigned16) ( - OP[1]));
State.C = (tmp >= (1 << 16));
tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
+ (unsigned)(unsigned16) ( - OP[1]));
State.C = (tmp >= (1 << 16));
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