+
+enum {
+ PSW_MASK = (PSW_SM_BIT
+ | PSW_EA_BIT
+ | PSW_DB_BIT
+ | PSW_IE_BIT
+ | PSW_RP_BIT
+ | PSW_MD_BIT
+ | PSW_FX_BIT
+ | PSW_ST_BIT
+ | PSW_F0_BIT
+ | PSW_F1_BIT
+ | PSW_C_BIT),
+ /* The following bits in the PSW _can't_ be set by instructions such
+ as mvtc. */
+ PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
+};
+
+reg_t
+move_to_cr (int cr, reg_t mask, reg_t val, int psw_hw_p)
+{
+ /* A MASK bit is set when the corresponding bit in the CR should
+ be left alone */
+ /* This assumes that (VAL & MASK) == 0 */
+ switch (cr)
+ {
+ case PSW_CR:
+ if (psw_hw_p)
+ val &= PSW_HW_MASK;
+ else
+ val &= PSW_MASK;
+ if ((mask & PSW_SM_BIT) == 0)
+ {
+ int new_psw_sm = (val & PSW_SM_BIT) != 0;
+ /* save old SP */
+ SET_HELD_SP (PSW_SM, GPR (SP_IDX));
+ if (PSW_SM != new_psw_sm)
+ /* restore new SP */
+ SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
+ }
+ if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
+ {
+ if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback,
+ "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
+ PC<<2);
+ State.exception = SIGILL;
+ }
+ }
+ /* keep an up-to-date psw around for tracing */
+ State.trace.psw = (State.trace.psw & mask) | val;
+ break;
+ case BPSW_CR:
+ case DPSW_CR:
+ /* Just like PSW, mask things like DM out. */
+ if (psw_hw_p)
+ val &= PSW_HW_MASK;
+ else
+ val &= PSW_MASK;
+ break;
+ case MOD_S_CR:
+ case MOD_E_CR:
+ val &= ~1;
+ break;
+ default:
+ break;
+ }
+ /* only issue an update if the register is being changed */
+ if ((State.cregs[cr] & ~mask) != val)
+ SLOT_PEND_MASK (State.cregs[cr], mask, val);
+ return val;
+}
+