Emit a warning when -z relro is unsupported

[deliverable/binutils-gdb.git] / sim / frv / cache.c

diff --git a/sim/frv/cache.c b/sim/frv/cache.c
index bfefa87d68e4216d87186f2d5866683b6c8dc29b..60857d9445f2173704663195028efaec0afeb1e6 100644 (file)
--- a/sim/frv/cache.c
+++ b/sim/frv/cache.c
@@ -1,22 +1,21 @@
 /* frv cache model.
 /* frv cache model.

-   Copyright (C) 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
+   Copyright (C) 1999-2020 Free Software Foundation, Inc.

    Contributed by Red Hat.
 
 This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
    Contributed by Red Hat.
 
 This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by

-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.

 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 

-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

 
 #define WANT_CPU frvbf
 #define WANT_CPU_FRVBF
 
 #define WANT_CPU frvbf
 #define WANT_CPU_FRVBF


@@ -38,8 +37,9 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
   switch (STATE_ARCHITECTURE (sd)->mach)
     {
     case bfd_mach_fr400:
   switch (STATE_ARCHITECTURE (sd)->mach)
     {
     case bfd_mach_fr400:

+    case bfd_mach_fr450:

       if (cache->configured_sets == 0)
       if (cache->configured_sets == 0)

-       cache->configured_sets = 128;
+       cache->configured_sets = 512;

       if (cache->configured_ways == 0)
        cache->configured_ways = 2;
       if (cache->line_size == 0)
       if (cache->configured_ways == 0)
        cache->configured_ways = 2;
       if (cache->line_size == 0)


@@ -205,9 +205,11 @@ non_cache_access (FRV_CACHE *cache, USI address)
   switch (STATE_ARCHITECTURE (sd)->mach)
     {
     case bfd_mach_fr400:
   switch (STATE_ARCHITECTURE (sd)->mach)
     {
     case bfd_mach_fr400:

+    case bfd_mach_fr450:

       if (address >= 0xff000000
          || address >= 0xfe000000 && address <= 0xfeffffff)
        return 1; /* non-cache access */
       if (address >= 0xff000000
          || address >= 0xfe000000 && address <= 0xfeffffff)
        return 1; /* non-cache access */

+      break;

     case bfd_mach_fr550:
       if (address >= 0xff000000
          || address >= 0xfeff0000 && address <= 0xfeffffff)
     case bfd_mach_fr550:
       if (address >= 0xff000000
          || address >= 0xfeff0000 && address <= 0xfeffffff)


@@ -219,6 +221,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
        }
       else if (address >= 0xfe400000 && address <= 0xfe407fff)
        return 1; /* non-cache access */
        }
       else if (address >= 0xfe400000 && address <= 0xfe407fff)
        return 1; /* non-cache access */

+      break;

     default:
       if (address >= 0xff000000
          || address >= 0xfeff0000 && address <= 0xfeffffff)
     default:
       if (address >= 0xff000000
          || address >= 0xfeff0000 && address <= 0xfeffffff)


@@ -230,6 +233,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
        }
       else if (address >= 0xfe400000 && address <= 0xfe403fff)
        return 1; /* non-cache access */
        }
       else if (address >= 0xfe400000 && address <= 0xfe403fff)
        return 1; /* non-cache access */

+      break;

     }
 
   hsr0 = GET_HSR0 ();
     }
 
   hsr0 = GET_HSR0 ();


@@ -1109,14 +1113,23 @@ address_interference (FRV_CACHE *cache, SI address, FRV_CACHE_REQUEST *req,
            return 1;
        }
       /* If this is not a WAR request, then yield to any WAR requests in
            return 1;
        }
       /* If this is not a WAR request, then yield to any WAR requests in

-        either pipeline.  */
+        either pipeline or to a higher priority request in the same pipeline.
+      */

       if (req->kind != req_WAR)
        {
          for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j)
            {
              other_req = cache->pipeline[i].stages[j].request;
       if (req->kind != req_WAR)
        {
          for (j = FIRST_STAGE; j < FRV_CACHE_STAGES; ++j)
            {
              other_req = cache->pipeline[i].stages[j].request;

-             if (other_req != NULL && other_req->kind == req_WAR)
-               return 1;
+             if (other_req != NULL)
+               {
+                 if (other_req->kind == req_WAR)
+                   return 1;
+                 if (i == pipe
+                     && (address == (other_req->address & line_mask) 
+                         || address == all_address)
+                     && priority > other_req->priority)
+                   return 1;
+               }

            }
        }
     }
            }
        }
     }