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Don't write to inferior_ptid in corelow.c
[deliverable/binutils-gdb.git]
/
sim
/
m32r
/
modelx.c
diff --git
a/sim/m32r/modelx.c
b/sim/m32r/modelx.c
index 5fe36ccf1351d3e9ffd5115f6a8f0d3213e331dc..a17493ddb8b9a8b2e0f6bb00960480e0dc17cbcf 100644
(file)
--- a/
sim/m32r/modelx.c
+++ b/
sim/m32r/modelx.c
@@
-2,7
+2,7
@@
THIS FILE IS MACHINE GENERATED WITH CGEN.
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-20
1
0 Free Software Foundation, Inc.
+Copyright 1996-20
2
0 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This file is part of the GNU simulators.
@@
-17,8
+17,7
@@
This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
License for more details.
You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+ with this program; if not, see <http://www.gnu.org/licenses/>.
*/
*/
@@
-1823,7
+1822,7
@@
model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
{
static int
model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.
s
fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@
-1901,7
+1900,7
@@
model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
{
static int
model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.
s
fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@
-2615,7
+2614,7
@@
model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
{
static int
model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.
s
fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@
-2721,7
+2720,7
@@
model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
{
static int
model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.
s
fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@
-2740,7
+2739,7
@@
model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
static int
model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
{
static int
model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.
s
fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@
-3011,7
+3010,7
@@
m32rx_model_init (SIM_CPU *cpu)
#define TIMING_DATA(td) 0
#endif
#define TIMING_DATA(td) 0
#endif
-static const MODEL m32rx_models[] =
+static const
SIM_
MODEL m32rx_models[] =
{
{ "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
{ 0 }
{
{ "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
{ 0 }
@@
-3019,7
+3018,7
@@
static const MODEL m32rx_models[] =
/* The properties of this cpu's implementation. */
/* The properties of this cpu's implementation. */
-static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
+static const
SIM_
MACH_IMP_PROPERTIES m32rxf_imp_properties =
{
sizeof (SIM_CPU),
#if WITH_SCACHE
{
sizeof (SIM_CPU),
#if WITH_SCACHE
@@
-3061,7
+3060,7
@@
m32rx_init_cpu (SIM_CPU *cpu)
#endif
}
#endif
}
-const MACH m32rx_mach =
+const
SIM_
MACH m32rx_mach =
{
"m32rx", "m32rx", MACH_M32RX,
32, 32, & m32rx_models[0], & m32rxf_imp_properties,
{
"m32rx", "m32rx", MACH_M32RX,
32, 32, & m32rx_models[0], & m32rxf_imp_properties,
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